CN114334663B - Power device and preparation method thereof - Google Patents
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- CN114334663B CN114334663B CN202210248569.4A CN202210248569A CN114334663B CN 114334663 B CN114334663 B CN 114334663B CN 202210248569 A CN202210248569 A CN 202210248569A CN 114334663 B CN114334663 B CN 114334663B
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Abstract
The invention provides a power device and a preparation method thereof, wherein the method comprises the following steps: forming a photoresist layer covering the leading-out region of the first polycrystalline silicon layer, and etching the first polycrystalline silicon layer in the groove of the unit region back to a preset depth; removing the photoresist layer, and thinning the exposed part of the first silicon oxide layer by wet etching; growing a sacrificial oxide layer on the exposed surface of the first polysilicon layer; removing the sacrificial oxide layer and part of the first silicon oxide layer by wet etching to expose the upper surface of the first polysilicon layer and the part of the side wall of the groove of the unit area, which is positioned above the preset depth; sequentially forming a gate oxide layer and a second polysilicon layer; and removing the part of the second polysilicon layer above the semiconductor layer. On one hand, the invention can avoid the step introduced into the oxide layer of the junction area of the first polycrystalline silicon layer leading-out area and the unit area, thereby enlarging the process window and reducing the risk of over-grinding or under-grinding; on the other hand, the appearance of the top of the first polycrystalline silicon layer can be optimized, and the product yield is greatly improved.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a power device and a preparation method thereof.
Background
In a conventional process of manufacturing a high-voltage Shielded Gate Trench (SGT), an extraction region of a first polysilicon layer is easily undercut by isotropic wet etching, so that the extraction region of the first polysilicon layer is often covered by a photoresist, and the oxide on the upper half of the sidewall of the trench is removed by wet etching, so that a step appears in the oxide layer below the edge region of the photoresist. The specific process flow comprises the steps of firstly carrying out primary photoetching, covering the area which does not need to remove the groove oxide with photoresist, then adopting wet etching to remove the oxide of the area which does not cover the photoresist at one time, and then removing the photoresist. Due to the existence of the step, a stopping point cannot be found during Chemical Mechanical Polishing (CMP) or etch back (etch back) of the second polysilicon layer, so that the second polysilicon chemical mechanical polishing has the risk of over-polishing or under-polishing, and further the gate end and the source end are in short circuit.
Therefore, how to improve the process window and increase the product yield is an important technical problem to be solved.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a power device and a method for manufacturing the same, which are used to solve the problem that the yield of the product is easily reduced in the conventional process.
In order to achieve the above objects and other related objects, the present invention provides a method for manufacturing a power device, including the steps of:
providing a semiconductor layer comprising a unit region and a first polycrystalline silicon layer leading-out region, wherein a plurality of grooves are arranged in the semiconductor layer, a first silicon oxide layer is arranged on the upper surface of the semiconductor layer and the inner wall of each groove, and a first polycrystalline silicon layer positioned on the surface of the first silicon oxide layer is also arranged in each groove;
forming a photoresist layer covering the leading-out region of the first polycrystalline silicon layer on the semiconductor layer, and etching back the first polycrystalline silicon layer in the groove of the unit region to a preset depth;
removing the photoresist layer, and thinning the exposed part of the first silicon oxide layer by wet etching;
growing a sacrificial oxide layer on the exposed surface of the first polycrystalline silicon layer;
removing the sacrificial oxide layer and part of the first silicon oxide layer by wet etching to expose the upper surface of the first polysilicon layer and the part of the side wall of the groove of the unit area, which is positioned above the preset depth;
sequentially forming a gate oxide layer and a second polycrystalline silicon layer, wherein the gate oxide layer covers the exposed surface of the groove of the unit region and the upper part of the semiconductor layer, and the second polycrystalline silicon layer covers the surface of the gate oxide layer;
and removing the part of the second polycrystalline silicon layer above the semiconductor layer.
Optionally, the sacrificial oxide layer has a thickness in a range of 250 angstroms to 500 angstroms.
Optionally, the method for removing the portion of the second polysilicon layer above the semiconductor layer includes chemical mechanical polishing.
Optionally, the step of removing the sacrificial oxide layer and a part of the first silicon oxide layer by wet etching further exposes a part of the sidewall of the first polysilicon layer in the trench of the cell region.
Optionally, the method for growing the sacrificial oxide layer comprises a thermal oxidation method.
Optionally, the method for removing the photoresist layer comprises dry photoresist removal.
Optionally, after the exposed part of the first silicon oxide layer is thinned by wet etching, the side wall of the first polysilicon layer in the trench of the cell region is not exposed, or the exposed side wall thickness is smaller than that of the sacrificial oxide layer.
Optionally, after the exposed part of the first silicon oxide layer is thinned by wet etching, the lateral thickness of the first silicon oxide layer in the trench in the cell region, which is located above the first polysilicon layer, is 1/10-7/10 of the lateral thickness of the first silicon oxide layer, which is located on the side wall of the first polysilicon layer.
Optionally, the semiconductor layer includes a silicon substrate and an epitaxial layer on the silicon substrate, the trench is located in the epitaxial layer, and a bottom surface of the trench is higher than a bottom surface of the epitaxial layer.
The invention also provides a power device, wherein the power device is prepared by adopting the preparation method of the power device.
As described above, the power device and the method for manufacturing the same of the present invention have the following beneficial effects: on one hand, the preparation method of the power device can avoid the step from being introduced into the oxide layer of the junction area of the leading-out area of the first polycrystalline silicon layer and the unit area when the oxide layer of the upper half part of the groove of the unit area is removed, thereby enlarging the process window when the second polycrystalline silicon layer is removed and reducing the risk of over-grinding or under-grinding; on the other hand, the preparation method of the power device can optimize the appearance of the top of the first polycrystalline silicon layer, reduces the risk of larger grid drive leakage current (IGSS)/grid body leakage current (IGSSR), and greatly improves the yield of products.
Drawings
Fig. 1 is a schematic diagram of a semiconductor layer including a cell region and a first polysilicon layer extraction region provided in a process of manufacturing a power device.
Fig. 2 is a schematic diagram illustrating a process of removing the first silicon oxide layer in the upper portion of the trench in the cell region by wet etching in a process of manufacturing a power device.
Fig. 3 is a schematic diagram showing the process of removing the photoresist layer and growing a sacrificial oxide layer in the process of manufacturing a power device.
Fig. 4 is a schematic diagram illustrating the removal of the sacrificial oxide layer during the fabrication of a power device.
Fig. 5 is a schematic diagram illustrating the growth of a gate oxide layer and a second polysilicon layer during the fabrication of a power device.
Fig. 6 is a schematic diagram of polysilicon polishing during the fabrication of a power device.
Fig. 7 shows a process flow diagram of a method for manufacturing a power device according to the present invention.
Fig. 8 is a schematic diagram illustrating a semiconductor layer including a cell region and a first polysilicon layer extension region provided in the method for manufacturing a power device according to the present invention.
Fig. 9 is a schematic diagram illustrating a process of forming a photoresist layer covering the first polysilicon layer lead-out region on the semiconductor layer and etching back the first polysilicon layer in the trench of the cell region to a predetermined depth in the method for manufacturing a power device according to the present invention.
Fig. 10 is a schematic diagram illustrating a process of removing the photoresist layer and thinning the exposed portion of the first silicon oxide layer by wet etching in the method for manufacturing a power device according to the present invention.
Fig. 11 is a schematic diagram illustrating a sacrificial oxide layer grown on an exposed surface of the first polysilicon layer in the method for manufacturing a power device according to the present invention.
Fig. 12 is a schematic diagram illustrating a process of removing the sacrificial oxide layer and a portion of the first silicon oxide layer by wet etching in the method for manufacturing a power device according to the present invention.
Fig. 13 is a schematic view illustrating a gate oxide layer and a second polysilicon layer sequentially formed in the method for manufacturing a power device according to the present invention.
Fig. 14 is a schematic diagram illustrating a method for manufacturing a power device according to the present invention, in which a portion of the second polysilicon layer above the semiconductor layer is removed.
Element number description: 101 silicon substrate, 102 epitaxial layer, 103 first silicon oxide, 104 first polysilicon layer, 105 photoresist layer, 106 steps, 107 sacrificial oxide layer, 108 gate oxide layer, 109 second polysilicon layer, S1-S7 steps, A unit area, B first polysilicon layer lead-out area, 201 trench, 202 first silicon oxide layer, 203 first polysilicon layer, 204 silicon substrate, 205 epitaxial layer, 206 photoresist layer, D predetermined depth, 207 sacrificial oxide layer, 208 gate oxide layer, 209 second polysilicon layer.
Detailed Description
Referring to fig. 1-6, schematic structural diagrams of steps in a process for manufacturing a power device are shown, including the following steps:
as shown in fig. 1, a semiconductor layer including a cell region and a first polysilicon layer extension region is provided, the semiconductor layer includes a silicon substrate 101 and an epitaxial layer 102, a plurality of trenches are formed in the semiconductor layer, first silicon oxide 103 is formed on an upper surface of the semiconductor layer and an inner wall of the trench, and a first polysilicon layer 104 is formed on a surface of the first silicon oxide 103 in the trench; forming a photoresist layer 105 covering the first polysilicon layer lead-out region on the semiconductor layer, and etching back the first polysilicon layer 104 in the trench of the cell region to a predetermined depth.
As shown in fig. 2, a wet etching process is used to remove the first silicon oxide layer 103 in the upper portion of the trench in the cell region. Due to the isotropy of the wet etch, a step 106 may be formed in the first silicon oxide layer 103 under the edge region of the photoresist layer 105.
The photoresist layer is removed and a sacrificial oxide layer 107 is grown, as shown in fig. 3.
As shown in fig. 4, the sacrificial oxide layer 107 is removed.
As shown in fig. 5, a gate oxide layer 108 and a second polysilicon layer 109 are grown.
As shown in fig. 6, a polysilicon polish is performed.
It should be noted that, in the above process, since the oxide layer at the boundary between the first polysilicon layer lead-out region and the cell region has a step, the risk of over-grinding or under-grinding is easily caused when the second polysilicon layer 109 is subjected to chemical mechanical polishing or etching back, so that the gate end and the source end are shorted, and the yield of the product is reduced. The preparation method of the power device solves the step problem by optimizing the process flow, optimizes the appearance of the first polysilicon layer and greatly improves the product yield.
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 7 to 14. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Referring to fig. 7, a process flow diagram of a method for manufacturing a power device according to the present invention is shown, which includes the following steps:
s1: providing a semiconductor layer comprising a unit region and a first polycrystalline silicon layer leading-out region, wherein a plurality of grooves are arranged in the semiconductor layer, a first silicon oxide layer is arranged on the upper surface of the semiconductor layer and the inner wall of each groove, and a first polycrystalline silicon layer positioned on the surface of the first silicon oxide layer is also arranged in each groove;
s2: forming a photoresist layer covering the leading-out region of the first polycrystalline silicon layer on the semiconductor layer, and etching back the first polycrystalline silicon layer in the groove of the unit region to a preset depth;
s3: removing the photoresist layer, and thinning the exposed part of the first silicon oxide layer by wet etching;
s4: growing a sacrificial oxide layer on the exposed surface of the first polycrystalline silicon layer;
s5: removing the sacrificial oxide layer and part of the first silicon oxide layer by wet etching to expose the upper surface of the first polysilicon layer and the part of the side wall of the groove of the unit area, which is positioned above the preset depth;
s6: sequentially forming a gate oxide layer and a second polycrystalline silicon layer, wherein the gate oxide layer covers the exposed surface of the groove of the unit region and the upper part of the semiconductor layer, and the second polycrystalline silicon layer covers the surface of the gate oxide layer;
s7: and removing the part of the second polycrystalline silicon layer above the semiconductor layer.
Referring to fig. 8, the step S1 is executed: providing a semiconductor layer comprising a unit area A and a first polycrystalline silicon layer leading-out area B, wherein a plurality of grooves 201 are arranged in the semiconductor layer, a first silicon oxide layer 202 is arranged on the upper surface of the semiconductor layer and the inner wall of each groove 201, and a first polycrystalline silicon layer 203 positioned on the surface of the first silicon oxide layer 202 is also arranged in each groove 201.
Specifically, the unit region a is adjacent to the first polysilicon layer lead-out region B, the unit region a is used for manufacturing a plurality of transistor units, and the first polysilicon layer lead-out region B is used for leading out a first polysilicon layer. The first polysilicon layer extraction region B may be regarded as a part of the termination region.
As an example, the semiconductor layer includes a silicon substrate 204 and an epitaxial layer 205 located on the silicon substrate 204, the trench 201 is located in the epitaxial layer 205, and a bottom surface of the trench 201 is higher than a bottom surface of the epitaxial layer 205.
As an example, the silicon substrate 204 and the epitaxial layer 205 are both N-type, and the doping concentration of the silicon substrate 204 is higher than that of the epitaxial layer 205. In other embodiments, other suitable materials may be used instead of the silicon substrate 204.
Referring back to fig. 9, the step S2 is executed: forming a photoresist layer 206 covering the first polysilicon layer lead-out region B on the semiconductor layer, and etching back the first polysilicon layer 203 in the trench 201 of the cell region a to a predetermined depth D.
As an example, the photoresist layer 206 may be formed by coating, and the photoresist layer 206 may be patterned by a photolithography process such that the first polysilicon layer lead-out region B is protected by the photoresist layer 206 and the photoresist layer of the cell region a is removed.
Referring back to fig. 10, the step S3 is executed: the photoresist layer 206 is removed and wet etching is used to thin the exposed portion of the first silicon oxide layer 202.
As an example, the method for removing the photoresist layer includes dry photoresist removal, that is, the photoresist layer is removed by using plasma, and the dry photoresist removal is more effective and faster than the wet photoresist removal.
Specifically, the thinned portion of the first silicon oxide layer 202 includes a portion located on the semiconductor and a portion located above the first polysilicon layer 203 in the trench of the cell region.
For example, after the exposed portion of the first silicon oxide layer 202 is thinned by wet etching, the sidewall of the first polysilicon layer 203 in the trench 201 of the cell region a is not exposed, or the exposed sidewall has a thickness smaller than that of the sacrificial oxide layer formed subsequently.
For example, after the exposed portion of the first silicon oxide layer 202 is thinned by wet etching, the lateral thickness of the first silicon oxide layer 202 located above the first polysilicon layer 203 in the trench 201 of the cell region a is 1/10-7/10 of the lateral thickness of the first silicon oxide layer 202 located on the sidewall of the first polysilicon layer 203.
Referring back to fig. 11, the step S4 is executed: a sacrificial oxide layer 207 is grown on the exposed surface of the first polysilicon layer 203.
As an example, the method of growing the sacrificial oxide layer 207 includes a thermal oxidation method. The sacrificial oxide layer has a thickness in the range of 250 angstroms to 500 angstroms.
It should be noted that, after the exposed portion of the first silicon oxide layer 202 is thinned by wet etching, the sidewall of the first polysilicon layer 203 in the trench 201 of the cell region a is not exposed, or the exposed sidewall has a small thickness, so in this step, the sacrificial oxide layer 207 is formed only on the top of the first polysilicon layer 203 in the trench 201 of the cell region a, or the sacrificial oxide layer 207 is formed only on the top and on a small portion of the sidewall (as compared with the scheme shown in fig. 3), which can avoid or reduce the lateral consumption of the first polysilicon layer 203, is beneficial to optimizing the topography of the top of the first polysilicon layer 203, reduces the risk of large gate drive leakage current (IGSS)/gate body leakage current (IGSSR), and further improves the yield of products.
Referring back to fig. 12, the step S5 is executed: wet etching is used to remove the sacrificial oxide layer 207 and a portion of the first silicon oxide layer 202 to expose the upper surface of the first polysilicon layer 203 and a portion of the sidewall of the trench 201 of the cell region a above the predetermined depth D.
It should be noted that, during the wet etching process to remove the sacrificial oxide layer 207 and a portion of the first silicon oxide layer 202, a portion of sidewalls of the first polysilicon layer 203 in the trench 201 of the cell region a is also exposed.
It should be noted that, because the top of the first polysilicon layer in the trench of the first polysilicon layer lead-out region B is also covered by the sacrificial oxide layer, the sacrificial oxide layer can protect the terminal, and reduce the underetching to the first polysilicon layer lead-out region in the wet etching process. On the other hand, since the part of the sidewall of the trench 201 of the cell region a, which is located above the predetermined depth D, has been thinned in the previous step, the wet etching time in this step can be greatly shortened, and the undercutting of the first polysilicon layer lead-out region in the wet etching process is further reduced.
Referring back to fig. 13, the step S6 is executed: and sequentially forming a gate oxide layer 208 and a second polysilicon layer 209, wherein the gate oxide layer 208 covers the exposed surface of the trench 201 of the unit region A and the upper part of the semiconductor layer, and the second polysilicon layer 209 covers the surface of the gate oxide layer 208.
Referring back to fig. 14, the step S7 is executed: the portion of the second polysilicon layer 209 over the semiconductor layer is removed.
As an example, the method for removing the portion of the second polysilicon layer 209 above the semiconductor layer includes chemical mechanical polishing.
It should be noted that, because the oxide layer at the junction between the first polysilicon layer lead-out region B and the cell region a has no step, the stop position of polysilicon grinding can be well controlled, the risk of over-grinding or under-grinding is eliminated, and the second polysilicon in the trench of the cell region a has a sufficient distance from the first polysilicon in the first polysilicon layer lead-out region B, so that short circuit is not easy to occur.
Thus, a power device is manufactured, wherein the first polysilicon layer 203 modulates an electric field and improves the breakdown voltage of the device, the second polysilicon layer 209 is used as a gate, and the first polysilicon layer 203 is connected with a source metal layer through a contact hole of the first polysilicon layer lead-out region B and metal, so that the potentials of the first polysilicon layer 203 and the source region are equal.
In summary, the preparation method of the power device of the present invention can, on one hand, avoid introducing steps into the oxide layer of the boundary region between the first polysilicon layer lead-out region and the cell region when removing the oxide layer of the upper half portion of the trench of the cell region, thereby increasing the process window when removing the second polysilicon layer and reducing the risk of over-grinding or under-grinding; on the other hand, the preparation method of the power device can optimize the appearance of the top of the first polycrystalline silicon layer, reduces the risk of larger grid drive leakage current (IGSS)/grid body leakage current (IGSSR), and greatly improves the yield of products. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A preparation method of a power device is characterized by comprising the following steps:
providing a semiconductor layer comprising a unit region and a first polycrystalline silicon layer leading-out region, wherein a plurality of grooves are arranged in the semiconductor layer, a first silicon oxide layer is arranged on the upper surface of the semiconductor layer and the inner wall of each groove, and a first polycrystalline silicon layer positioned on the surface of the first silicon oxide layer is also arranged in each groove;
forming a photoresist layer covering the leading-out region of the first polycrystalline silicon layer on the semiconductor layer, and etching back the first polycrystalline silicon layer in the groove of the unit region to a preset depth;
removing the photoresist layer, and thinning the exposed part of the first silicon oxide layer by wet etching;
growing a sacrificial oxide layer on the exposed surface of the first polycrystalline silicon layer;
removing the sacrificial oxide layer and part of the first silicon oxide layer by wet etching to expose the upper surface of the first polysilicon layer and the part of the side wall of the groove of the unit area, which is positioned above the preset depth;
sequentially forming a gate oxide layer and a second polycrystalline silicon layer, wherein the gate oxide layer covers the exposed surface of the groove of the unit region and the upper part of the semiconductor layer, and the second polycrystalline silicon layer covers the surface of the gate oxide layer;
and removing the part of the second polycrystalline silicon layer above the semiconductor layer.
2. The method for manufacturing a power device according to claim 1, wherein: the sacrificial oxide layer has a thickness in the range of 250 angstroms to 500 angstroms.
3. The method for manufacturing a power device according to claim 1, wherein: the method for removing the part of the second polycrystalline silicon layer, which is positioned above the semiconductor layer, comprises the step of chemical mechanical polishing.
4. The method for manufacturing a power device according to claim 1, wherein: and the step of removing the sacrificial oxide layer and part of the first silicon oxide layer by wet etching also exposes part of the side wall of the first polysilicon layer in the groove of the unit region.
5. The method for manufacturing a power device according to claim 1, wherein: the method for growing the sacrificial oxide layer comprises a thermal oxidation method.
6. The method for manufacturing a power device according to claim 1, wherein: the method for removing the photoresist layer comprises dry photoresist removal.
7. The method for manufacturing a power device according to claim 1, wherein: and after the exposed part of the first silicon oxide layer is thinned by wet etching, the side wall of the first polysilicon layer in the groove of the unit area is not exposed, or the thickness of the exposed side wall is smaller than that of the sacrificial oxide layer.
8. The method for manufacturing a power device according to claim 1, wherein: adopt wet etching attenuate behind the exposed part of first silicon oxide layer, the unit district be located in the ditch groove more than the first polycrystalline silicon layer the lateral thickness of first silicon oxide layer is for being located the first polycrystalline silicon layer lateral wall 1/10-7/10 of the lateral thickness of first silicon oxide layer.
9. The method for manufacturing a power device according to claim 1, wherein: the semiconductor layer comprises a silicon substrate and an epitaxial layer located on the silicon substrate, the groove is located in the epitaxial layer, and the bottom surface of the groove is higher than the bottom surface of the epitaxial layer.
10. A power device, characterized by: the power device is prepared by the preparation method of the power device according to any one of claims 1 to 9.
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| CN112133637A (en) * | 2020-11-30 | 2020-12-25 | 中芯集成电路制造(绍兴)有限公司 | Method for manufacturing semiconductor device with shielded gate trench |
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| TWI400757B (en) * | 2005-06-29 | 2013-07-01 | Fairchild Semiconductor | Methods for forming shielded gate field effect transistors |
| US20130224919A1 (en) * | 2012-02-28 | 2013-08-29 | Yongping Ding | Method for making gate-oxide with step-graded thickness in trenched dmos device for reduced gate-to-drain capacitance |
| US10163639B2 (en) * | 2015-07-09 | 2018-12-25 | Great Wall Semiconductor Corporation | Trench MOSFET with depleted gate shield and method of manufacture |
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| CN113053738A (en) * | 2019-12-27 | 2021-06-29 | 华润微电子（重庆）有限公司 | Split gate type groove MOS device and preparation method thereof |
| CN113327858A (en) * | 2020-07-15 | 2021-08-31 | 上海先进半导体制造有限公司 | Shielded gate field effect transistor and method of manufacturing the same |
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Address after: 510700 No. 28, Fenghuang fifth road, Huangpu District, Guangzhou, Guangdong Patentee after: Yuexin Semiconductor Technology Co.,Ltd. Address before: 510700 No. 28, Fenghuang fifth road, Huangpu District, Guangzhou, Guangdong Patentee before: Guangzhou Yuexin Semiconductor Technology Co.,Ltd. |
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