CN103560086B - The preparation method of the super-junction semiconductor device of avalanche capacity can be improved - Google Patents
The preparation method of the super-junction semiconductor device of avalanche capacity can be improved Download PDFInfo
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
Abstract
The present invention relates to the preparation method of a kind of super-junction semiconductor device improving avalanche capacity.The higher P post doping content of tradition exacerbates horizontal proliferation conducting resistance is increased accordingly, and the unbalance reduction making breakdown voltage of P post and N post electric charge.The present invention utilizes epitaxy technique, forms N-type epitaxy layer；Carry out boron ion implanting and form p-type N-type epitaxy layer；Boron ion implantation dosage gradually increases, and the most at high temperature knot forms the epitaxial layer that p-type replaces with N-type；Inject boron ion and form Pbody district；Dry etching polysilicon is used to form polygate electrodes；Inject arsenic ion, form N+ source region；Upper surface at whole device deposits one layer of aluminium, and etch aluminum forms source metal electrode, and back face metalization forms drain electrode.The super-junction semiconductor device of gained of the present invention reduces conducting resistance in the avalanche capacity that improve super-junction semiconductor device simultaneously.
Description
Technical field
The invention belongs to semiconductor devices and manufacture field with technique, be specifically related to the preparation method of a kind of super-junction semiconductor device improving avalanche capacity.
Background technology
Hyperconjugation VDMOS be one quickly grow, widely used Novel power semiconductor.It is on the basis of normal vertical double-diffused metal oxide semiconductor (VDMOS), introduce superjunction (Superjunction) structure, be allowed to i.e. have VDMOS input impedance height, switching speed is fast, operating frequency is high, Control of Voltage, Heat stability is good, drive circuit simple, and the conducting resistance overcoming again VDMOS is pressed into, with breakdown potential, the shortcoming that 2.5 power relations sharply increase.Hyperconjugation VDMOS is widely used to computer, mobile phone, illumination and liquid crystal or the power supply of the consumption electronic product such as plasma TV and game machine or adapter at present.
For power semiconductor, avalanche energy is generally measured under the conditions of non-clamper perception switch UIS, and the snowslide under UIS condition of work damages both of which, and cause thermal damage and parasitic triode conducting damage.Cause thermal damage be exactly power device under the effect of output pulses, owing to power consumption increase causes junction temperature to raise, junction temperature be increased to silicon chip characteristic allow critical value and cause burn inefficacy.
The second breakdown effect that during VDMOS avalanche breakdown, parasitism BJT causes seriously constrains the avalanche capacity of VDMOS device, see structure and the parasitic triode schematic diagram of Fig. 1 hyperconjugation VDMOS, inevitably parasitic a bipolar transistor BJT near Pbody district, Pbody district constitutes the base of parasitic BJT, the colelctor electrode of the most parasitic BJT is also respectively drain electrode and the source electrode of VDMOS with emitter stage, and this ectoparasite BJT exists the equivalent resistance R from VDMOS source electrode to Pbody districtB.When VDMOS is in blocking state, along with the increase of drain-source voltage, device inside electric field is gradually increased, and leakage current increases the most therewith.When partial compromise electric current flows through BJT body district, equivalent resistance RBTwo ends produce pressure drop, and this pressure drop is equal to the V of parasitic triode BJTBE, when VDMOS is close to avalanche breakdown, leakage current is increased dramatically, if RBOn pressure drop enough make parasitic triode open, parasitic BJT will cause second breakdown effect.Equivalent resistance RBIncrease with increased temperature, and the cut-in voltage V of emitter stage and base stageBEReducing with the increase of temperature, therefore, the avalanche capacity of VDMOS reduces with the increase of temperature.Second breakdown from bipolar transistor is different, and the second breakdown of VDMOS is general only to be occurred when being in high pressure, big current work state, there is not the effect of hot localised points.
When VDMOS occurs avalanche breakdown, parasitic triode is activated when turning on generation second breakdown, and VDMOS also has fever phenomenon drastically.When there is avalanche breakdown, device temperature is relevant with the performance of size of current and device itself.When, after device generation avalanche breakdown, without suitable buffering, suppression Improving Measurements, along with the increase of voltage x current, device heat-sinking capability can worse and worse, and temperature drastically raises, and can cause the damage of device.Parasitic triode is also possible to cause power MOSFET single event burnout (SEB) phenomenon, so-called single event burnout refers to that its endophyte triode is opened and the local avalanche breakdown phenomenon that formed under heavy ion ionization path is induced, this effect serious threat space flight and the safety of satellite electron system.
The major measure of suppression VDMOS second breakdown has: increases junction depth and the concentration of Pbody, reduces resistance RB.For parasitic BJT, by increasing Pbody concentration, i.e. add the clean dopant concentration Q of baseB, by increasing Pbody junction depth, for parasitic BJT, i.e. it being the increase in unspent base width W, currentamplificationfactorβ can be reduced, second breakdown point increases with Pbody concentration and improves.Traditional solution is by deeply injecting P in P body district+Ion, but the junction depth that this structure makes P body district deepens, and adds the conducting resistance of VDMOS.Nineteen ninety-five K. Fischer and K., Shenai published an article, it is proposed that add an autoregistration shallow diffusion into the surface P+Region, can very effectively suppress parasitic transistor effect, and while reducing current gain and base resistance, not consume extra epitaxy layer thickness.Although it is to be noted that autoregistration shallow diffusion into the surface P+Region inhibits ghost effect and does not increase cell density, but improves the possibility of punch-through breakdown, also needs to combine concrete device operating conditions requirement and weigh when therefore producing.
Avalanche breakdown occurs the ratio in cellular region that more preferable reliability occurs can obtain in termination environment, and the breakdown voltage of cellular region can design realization more easily relative to the breakdown voltage of termination environment, thus in order to improve the reliability of superjunction devices, the design capacity of the breakdown voltage suitably reducing cellular region is more prone to than the breakdown voltage improving termination environment further.Use higher P post doping content can suitably improve the avalanche capacity of power semiconductor, but higher P post doping content exacerbates horizontal proliferation and conducting resistance is increased accordingly, and the unbalance reduction making breakdown voltage of P post and N post electric charge.
Summary of the invention
The technical problem to be solved there is provided the preparation method of a kind of super-junction semiconductor device improving avalanche capacity, and the super-junction semiconductor device of this kind of method gained reduces conducting resistance in the avalanche capacity that improve super-junction semiconductor device simultaneously.
For solving above-mentioned technical problem, the technical scheme that the present invention takes: the preparation method of a kind of super-junction semiconductor device improving avalanche capacity, it is particular in that: realized by following steps:
Step one, utilize epitaxy technique, at N+The N-type epitaxy layer of one layer of 3 ~ 10 μm is formed on substrate；
Step 2, utilize P post mask plate mask to carry out boron ion implanting to form the p-type N-type epitaxy layer that a layer thickness is 3 ~ 6 μm；
Step 3, respectively repeat steps one and step 25 ~ 10 times, boron ion implantation dosage gradually increases by 2% ~ 8% simultaneously, then under 900 ~ 1200 DEG C of high temperature, knot forms the epitaxial layer that the p-type that thickness is 30 ~ 40 μm replaces with N-type, and wherein the doping content scope of N-type epitaxy layer is 0.5 ~ 2.5 × 1015cm-3, cellular region P post doping content scope is 1.0 ~ 5.5 × 1015cm-3；
Step 4, the energy injection dosage of employing 50 ~ 200KeV are 2 ~ 8 × 1013cm-2Boron ion, and knot forms Pbody district in 60 ~ 200 minutes under the high temperature of 900 ~ 1200 DEG C；
Step 5, gate oxide (6) thick for 90 minutes dry oxide growth 50 ~ 200nm at a temperature of 1000 ~ 1200 DEG C, deposit the thick polysilicon of 200 ~ 800nm afterwards, and use dry etching polysilicon to form polygate electrodes；
Step 6, the energy injection dosage of employing 80KeV are 3 × 1015cm-2Arsenic ion, and knot 30 minutes forms N at a temperature of 900 DEG C+Source region；
Step 7, the bpsg layer of deposit 2 ~ 4 μ m-thick, reflux 30 ~ 60 minutes under 900 ~ 1000 DEG C of nitrogen atmospheres, and etch formation contact hole；
Step 8, depositing one layer of aluminium at the upper surface of whole device, and etch aluminum forms source metal electrode, passivation, back face metalization forms drain electrode.
Described step 3 controls the boron ion doping concentration of P post zones of different by regulation P post mask plate, and in the middle of P post, doping content is the highest, and doping content is successively decreased to both sides；
Control the doping content of P post longitudinal direction in described step 3 by gradually increasing the implantation dosage of boron ion, the doping content of P column bottom is minimum, and doping content is gradually increased from bottom to top；
The P post mask plate of each P post is one group of adjacent pattern composition, and the interval of different P posts is more than the width of P post；
Often the pattern of the ion implanted regions of group P post mask plate is the regular pattern that can manufacture.
Often the width of the pattern of the ion implanted regions of group P post mask plate gradually successively decreases to both sides from P post center.
The described regular pattern bar shaped, circular or square manufactured.
Compared with prior art, beneficial effects of the present invention:
The preparation method of a kind of super-junction semiconductor device of the present invention, is the most gradually incremented by longitudinal doping content of hyperconjugation VDMOS device P post, thus reduces the equivalent resistance R of the parasitic BJT below the metal electrode of sourceBResistance value, and make avalanche current from the base of parasitic BJT to the internal transfer along P post, thus inhibit the unlatching of the emitter junction of parasitic BJT dramatically, it is to avoid parasitic BJT causes second breakdown；And this P post regulates in the middle of P post by mask plate and the implantation dosage at edge, reduce the doping content of P post fringe region, thus reduce the doping content gradient of P post edge, efficiently reduce horizontal proliferation, thus the effective width of conductive channel when increasing break-over of device, thus reduce conducting resistance in the avalanche capacity that improve super-junction semiconductor device simultaneously；The compatible existing repeatedly extension repeatedly injection technology of the present invention, does not increase technique manufacturing cost and processing step while promoting avalanche capacity.
Accompanying drawing explanation
Fig. 1 is structure and the parasitic triode equivalent structure schematic diagram of existing super-junction semiconductor device；
Fig. 2 is the cross-sectional view of the super-junction semiconductor device of the repeatedly extension repeatedly injection technology formation of the present invention；
Fig. 3 is the P post mask blank structural representation of the cellular region of the present invention；
Fig. 4 is the net dopant concentration distribution map of AA ' line in Fig. 2；
Fig. 5 is the net dopant concentration distribution map of BB ' line in Fig. 2.
Wherein, 1, N+Substrate, 2, N-type epitaxy layer, 3, P post, 4, Pbody district, 5, N+Source region, 6, gate oxide, 7, polygate electrodes, 8, BPSG dielectric layer, 9, source metal electrode, 10, boron ion implanted regions.
Detailed description of the invention
The present invention is described in detail with detailed description of the invention below in conjunction with the accompanying drawings.
The preparation method of a kind of super-junction semiconductor device improving avalanche capacity, is realized by following steps:
Step one, utilize epitaxy technique, at N+The N-type epitaxy layer 2 of one layer of 3 ~ 10 μm is formed on substrate 1；
Step 2, utilize P post mask plate mask to carry out boron ion implanting to form the p-type N-type epitaxy layer that a layer thickness is 3 ~ 6 μm；
Step 3, respectively repeat steps one and step 25 ~ 10 times, boron ion implantation dosage gradually increases 2%-8% simultaneously, then under 900 ~ 1200 DEG C of high temperature, knot forms the epitaxial layer that the p-type that thickness is 30 ~ 40 μm replaces with N-type, and wherein the doping content scope of N-type epitaxy layer 2 is 0.5 ~ 2.5 × 1015cm-3, cellular region P post doping content scope is 1.0 ~ 5.5 × 1015cm-3；
Step 4, the energy injection dosage of employing 50 ~ 200KeV are 2 ~ 8 × 1013cm-2Boron ion, and knot forms Pbody district 4 in 60 ~ 200 minutes under the high temperature of 900 ~ 1200 DEG C；
Step 5, gate oxide 6 thick for 90 minutes dry oxide growth 50 ~ 200nm at a temperature of 1000 ~ 1200 DEG C, deposit the thick polysilicon of 200 ~ 800nm afterwards, and use dry etching polysilicon to form polygate electrodes 7；
Step 6, the energy injection dosage of employing 80KeV are 3 × 1015cm-2Arsenic ion, and knot 30 minutes forms N at a temperature of 900 DEG C+Source region 5；
Step 7, the bpsg layer of deposit 2 ~ 4 μ m-thick, reflux 30 ~ 60 minutes under 900 ~ 1000 DEG C of nitrogen atmospheres, and etch formation contact hole；
Step 8, depositing one layer of aluminium at the upper surface of whole device, and etch aluminum forms source metal electrode, passivation, back face metalization forms leakage metal electrode 9.
Described step 3 controls the boron ion doping concentration of P post zones of different by regulation P post mask plate, and in the middle of P post, doping content is the highest, and doping content is successively decreased to both sides.
Control the doping content of P post longitudinal direction in described step 3 by gradually increasing the implantation dosage of boron ion, the doping content of P column bottom is minimum, and doping content is gradually increased from bottom to top.
The P post mask plate of each P post is one group of adjacent pattern composition, and the interval of different P posts is more than the width of P post.
Often the pattern of the ion implanted regions of group P post mask plate can be bar shaped, circular or square and other regular pattern that can manufacture.
Often the width of the pattern of the ion implanted regions of group P post mask plate gradually successively decreases to both sides from P post center.
By adjusting the size of ion implanting figure of P post mask plate, number is with spacing thus controls the boron ion doping concentration of P post zones of different, in the middle of P post mask plate, bar paten is the widest, pattern width successively decreases successively to P post both sides, in the middle of the ion populations obtained after making doping at most, successively decrease to both sides successively.
The operation principle of the present invention is: the doping content of source metal electrode 9 P capital end below is the highest, thus reduces the equivalent resistance R of source metal electrode 9 parasitic BJT belowBResistance value, and make avalanche current from the base of parasitic BJT to the internal transfer along P post, thus inhibit the unlatching of the emitter junction of parasitic BJT dramatically, it is to avoid parasitic BJT causes second breakdown；By adjusting the figure of P post mask plate, use discontinuous mask plate figure, it is maximum that boron ion dose is injected at the middle part making P post 3, gradually successively decreased to both sides by its horizontal doping content of long-time high temperature knot, the doping content at the middle edge with P post of regulation P post, efficiently reduce horizontal proliferation, the effective width of conductive channel when increasing break-over of device, thus reduce conducting resistance in the avalanche capacity that improve super-junction semiconductor device simultaneously.
Seeing Fig. 1, inherently parasitic bipolar transistor NPN structure in the structure of hyperconjugation VDMOS, for avoiding this parasitic triode to open, it is necessary to reduce its base stage equivalent resistance RBThe pressure drop at two ends make its emitter junction to open.
Seeing Fig. 2, the superjunction devices of the present invention have employed a kind of uneven doping P post, and the doping content of this P post is the most uneven along AA ' line and BB ' line direction.
See Fig. 3, the mask plate of the uneven doping P post that the superjunction devices of the present invention uses, use discontinuous mask plate figure, by adjusting the figure of P post mask plate, owing to using negative photoresist, thus the region of the ion implanting in the middle part of P post is maximum, so that boron ion dose maximum is injected at the middle part of P post, gradually being successively decreased to both sides from centre by its horizontal doping content of long-time high temperature knot, in figure, fill area is boron ion implanted regions.
See Fig. 4, the P post doping content after long-time high temperature knot of AA ' line shown in Fig. 1 is gradually successively decreased to both sides from centre, the doping content at the middle edge with P post of regulation P post, efficiently reduce horizontal proliferation, the effective width of conductive channel when increasing break-over of device, thus reduce conducting resistance in the avalanche capacity that improve super-junction semiconductor device simultaneously.
Seeing Fig. 5, shown in BB ' line shown in Fig. 1, the doping content of P post is gradually successively decreased to internal by surface, and below the metal electrode of source, the doping content of P capital end is the highest, thus reduces the equivalent resistance R of the parasitic BJT below the metal electrode of sourceBResistance value, and make avalanche current from the base of parasitic BJT to the internal transfer along P post, thus inhibit the unlatching of the emitter junction of parasitic BJT dramatically, it is to avoid parasitic BJT causes second breakdown.
Embodiment:
The present embodiment uses and illustrates with the MOSFET with super-junction structure, but the present invention is not limited to MOSFET.
One, backing material prepares, the N using resistivity to be 0.001 Ω cm+Zone melting single-crystal silicon substrate 1, its crystal orientation is<100>；
Two, at N+Substrate Epitaxial growth 5 μm resistivity is the N-type epitaxy layer of 4 Ω cm, as P post and N+Cushion between substrate；
Three, in the N-type epitaxy layer that silicon chip surface epitaxial growth 5 μm resistivity is 4 Ω cm；
Four, the negative photoresist (place i.e. having P post figure carries out boron ion implanting) of 6 μm is deposited at silicon chip surface, P post mask plate is used to be exposed and develop, then four high-energy boron ion implantings are carried out, injecting boron ion energy and use 3.5MeV, 2.5MeV, 1.2KeV and 200KeV successively, the boron ion dose of injection is 6 × 1011cm-2；
Five, step 3 and step 4 it are repeated 6 times, but the boron ion dose injected when repeating step 4 increases by the boron ion dose of 5% on the basis of front once injection every time, the last high temperature knot carrying out 30 minutes under the nitrogen atmosphere of 1100 DEG C of temperature, forming length and be about the continuous P post of 35 μm, wherein the typical dopant concentrations of N-type epitaxy layer is 1.1 × 1015cm-3, cellular region P post typical dopant concentrations is 3.6 × 1015cm-3；
Six, the energy injection dosage using 120KeV is 5.2 × 1013cm-2Boron ion, and knot forms Pbody district 4 in 120 minutes under the high temperature of 1000 DEG C；
Seven, 90 minutes gate oxides 6 thick for dry oxide growth 100nm at a temperature of 1100 DEG C, polysilicon thick for deposit 400nm afterwards, and use dry etching polysilicon to form polygate electrodes 7；
Eight, the energy injection dosage using 80KeV is 3 × 1015cm-2Arsenic ion, and knot 30 minutes forms N at a temperature of 900 DEG C+Source region 5；
Nine, deposit the bpsg layer 8 of 2 μ m-thick, reflux 30 minutes under 950 DEG C of nitrogen atmospheres, and etch formation contact hole；
Ten, the upper surface at whole device deposits one layer of aluminium, and etch aluminum forms source metal electrode 9, passivation, and back face metalization forms drain electrode.
The present invention can form the P post that internal doping content is progressively successively decreased from source surface to epitaxial layer, parasitic triode effect is inhibited, thus improve the avalanche capacity of super-junction semiconductor device, and efficiently reduce the horizontal proliferation of P post, the transverse width of conductive channel when increasing break-over of device so that the conducting resistance of device is reduced.
Claims (6)
1. the preparation method of the super-junction semiconductor device that can improve avalanche capacity, it is characterised in that: realized by following steps:
Step one, utilize epitaxy technique, at N+The upper N-type epitaxy layer (2) forming one layer of 3 ~ 10 μm of substrate (1)；
Step 2, utilize P post mask plate mask to carry out boron ion implanting to form the territory, p type island region that a layer thickness is 3 ~ 6 μm；
Step 3, respectively repeat steps one and step 25 ~ 10 times, boron ion implantation dosage gradually increases by 2% ~ 8% simultaneously, then under 900 ~ 1200 DEG C of high temperature, knot forms the epitaxial layer that the p-type that thickness is 30 ~ 40 μm replaces with N-type, and wherein the doping content scope of N-type epitaxy layer (2) is 0.5 ~ 2.5 × 1015cm-3, cellular region P post doping content scope is 1.0 ~ 5.5 × 1015cm-3；
Step 4, the energy injection dosage of employing 50 ~ 200KeV are 2 ~ 8 × 1013cm-2Boron ion, and knot forms Pbody district (4) in 60 ~ 200 minutes under the high temperature of 900 ~ 1200 DEG C；
Step 5, gate oxide (6) thick for 90 minutes dry oxide growth 50 ~ 200nm at a temperature of 1000 ~ 1200 DEG C, deposit the thick polysilicon of 200 ~ 800nm afterwards, and use dry etching polysilicon to form polygate electrodes (7)；
Step 6, the energy injection dosage of employing 80KeV are 3 × 1015cm-2Arsenic ion, and knot 30 minutes forms N at a temperature of 900 DEG C+Source region (5)；
Step 7, the bpsg layer of deposit 2 ~ 4 μ m-thick, reflux 30 ~ 60 minutes under 900 ~ 1000 DEG C of nitrogen atmospheres, and etch formation contact hole；
Step 8, whole device upper surface deposit one layer of aluminium, and etch aluminum formed source metal electrode (9), passivation, back face metalization formed drain electrode；
Described step 3 controls the boron ion doping concentration of P post (3) zones of different by regulation P post mask plate, and in the middle of P post (3), doping content is the highest, and doping content is successively decreased to both sides.
The preparation method of the super-junction semiconductor device improving avalanche capacity the most according to claim 1, it is characterized in that: described step 3 controls the doping content of P post (3) longitudinal direction by gradually increasing the implantation dosage of boron ion, the doping content of P post (3) bottom is minimum, and doping content is gradually increased from bottom to top.
The preparation method of the super-junction semiconductor device improving avalanche capacity the most according to claim 1 and 2, it is characterised in that: the P post mask plate of each P post (3) is one group of adjacent pattern composition, and the interval of different P posts is more than the width of P post (3).
The preparation method of the super-junction semiconductor device improving avalanche capacity the most according to claim 3, it is characterised in that: often the pattern of the ion implanted regions of group P post mask plate is the regular pattern that can manufacture.
The preparation method of the super-junction semiconductor device improving avalanche capacity the most according to claim 4, it is characterised in that: often the width of the pattern of the ion implanted regions of group P post mask plate gradually successively decreases to both sides from P post center.
The preparation method of the super-junction semiconductor device improving avalanche capacity the most according to claim 4, it is characterised in that: the described regular pattern that manufactures is bar shaped, circular or square.
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