CN114649406A - Multilevel super junction structure and self-aligned preparation method thereof - Google Patents
Multilevel super junction structure and self-aligned preparation method thereof Download PDFInfo
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
Abstract
The invention relates to a multi-level super junction structure and a self-aligned preparation method thereof. The multilevel super junction structure comprises an epitaxial layer and a multilevel super junction column region, the multilevel super junction column region comprises a plurality of single-stage column regions, the plurality of single-stage column regions correspond to a plurality of single-stage grooves, and the self-aligning preparation method of the multilevel super junction structure comprises the following steps: growing a surface etching mask and forming a groove side wall protection layer for multiple times, and performing self-aligned etching for multiple times by using the surface etching mask and the groove side wall protection layer to form a multilevel groove. The multistage super junction structure and the self-aligning preparation method thereof can realize regulation and control of the inclination angle of the side wall of the super junction groove, and can effectively reduce the influence caused by the side etching effect during deep groove etching by forming the groove side wall protective layer and then performing multistage etching, so that the super junction deep groove keeps relatively high verticality, and the performance of a super junction device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a multi-level super junction structure and a self-aligned preparation method thereof.
Background
In recent years, energy conservation and emission reduction are more and more emphasized internationally, and higher requirements are put forward for loss control and efficiency improvement of large-scale power electronic equipment. Semiconductor power devices have received much attention in the industry as an important component of power electronic equipment. The super junction device can break through the one-dimensional theoretical performance limit of a common device, and has great performance advantages and application potential in the middle and high voltage field.
The mainstream manufacturing technology route of the super junction device at present comprises multiple epitaxy and trench epitaxy backfill processes. The super junction device based on the epitaxial backfill process has the advantages of small cell size and low cost. In the technical route, the appearance and the side wall inclination angle of the groove have great influence on the performance of the device, the blocking performance of the device can be reduced when the inclination angle of the side wall of the P column region of the active region of the super junction device is too large, the effect of local electric field modulation of the active region and the terminal region can be achieved at a proper angle, and the withstand voltage of the super junction device is further improved. The existing groove process is formed at one time, the side wall of the groove is damaged due to the existence of the side etching effect in the etching process, and the appearance degradation is more serious along with the increase of the etching time and the etching depth. Aiming at the silicon carbide material, the etching selection ratio under the nonmetal mask is low, the etching of the super junction deep groove is difficult to realize, and how to etch the deep groove with high depth-to-width ratio and controllable side wall inclination angle becomes the difficulty of the process.
Disclosure of Invention
Aiming at the problems in the prior super junction device technology, the invention provides a multi-stage super junction structure and a self-aligned preparation method thereof, which can form a super junction groove with controllable side wall inclination angle and is beneficial to improving the etching selection ratio.
The embodiment of the invention provides a self-aligned preparation method of a multi-stage super junction structure, which is characterized by comprising the steps of growing a surface etching mask, forming a groove side wall protection layer for multiple times, and performing self-aligned etching for multiple times by using the surface etching mask and the groove side wall protection layer to form a multi-stage groove.
Further, the depth of the trench sidewall protection layer corresponding to each self-aligned etching is greater than the depth of the trench sidewall protection layer corresponding to the previous self-aligned etching.
Further, each self-aligned etching is carried out until the corresponding groove side wall protection layer is consumed; or, the corresponding groove side wall protection layer is reserved after each self-aligned etching.
Further, the depth of the first-stage trench among the multi-stage trenches is determined by the depth of the multi-stage trench and the total number of stages.
Further, forming the trench sidewall protection layer includes: and depositing a protective layer, and etching the protective layer at the bottom of each level of groove to form a corresponding groove side wall protective layer.
Further, the method also comprises the following steps: and removing the surface etching mask or removing the surface etching mask and the groove side wall protection layer, and performing epitaxial backfilling and polishing processes to form a multi-stage super junction column region, wherein the multi-stage super junction column region comprises a plurality of single-stage column regions.
Furthermore, the tops of the adjacent single-pole column regions are connected with the bottom, the side walls of the multistage super junction column regions are vertical in a step shape, and the width of the single-pole column regions is gradually reduced from the tops to the bottoms of the multistage super junction column regions; or the side walls of the multistage super junction column regions are vertical, and the width of each single-stage column region is the same; alternatively, the sidewalls of each single stage column section exhibit an arcuate shape.
Further, the doping concentration of the single-level column region is gradually reduced from the top to the bottom of the multi-level super junction column region.
According to another embodiment of the present invention, a self-aligned preparation method of a multi-level super junction structure is provided, including: etching a first-stage groove by using a first-stage groove etching mask, wherein the first-stage groove etching mask is formed on the surface of the semiconductor; and forming a first-stage groove side wall protection layer, and performing first self-aligned etching by using a second-stage groove etching mask, wherein the second-stage groove etching mask comprises a first-stage groove etching mask and a first-stage groove side wall protection layer.
Further, the method also comprises performing a second self-aligned etching to an N-1 th self-aligned etching, wherein N is a natural number greater than or equal to 3, and the performing the second self-aligned etching comprises: forming a second-stage groove side wall protective layer, and performing second self-aligned etching by using a third-stage groove etching mask, wherein the third-stage groove etching mask comprises the second-stage groove side wall protective layer and a second-stage groove etching mask after the first self-aligned etching; the self-aligned etching for the (N-1) th time comprises the following steps: and forming an N-1 level groove side wall protection layer, and performing N-1 time self-alignment etching by using an N level groove etching mask to form a multi-level groove, wherein the N level groove etching mask comprises an N-1 level groove side wall protection layer and an N-1 level groove etching mask after N-2 times self-alignment etching, and the same process method is adopted from the second time self-alignment etching to the N-1 time self-alignment etching.
Further, the mth self-alignment etching is carried out until the mth groove side wall protection layer is consumed; or the mth-level groove side wall protection layer is reserved after the mth self-alignment etching, wherein m is a natural number from 1 to N.
Further, wherein forming the m-th level trench sidewall protection layer comprises: forming an m-1 level protective layer on the side wall and the bottom of the m-1 level groove; and non-selectively etching the m-1 level protective layer to form an m level groove side wall protective layer, wherein m is a natural number from 1 to N.
Further, the thickness of the (m-1) th protective layer on the first-level groove etching mask is larger than that of the (m-1) th protective layer on the bottom of the (m-1) th groove.
Further, the forming of the m-th-level trench sidewall protection layer by non-selective etching includes: and removing the m-1 level protective layer on the bottom of the m-1 level groove by using the characteristic of plasma dry etching anisotropy, wherein m is one natural number from 1 to N.
Further, the method also comprises the following steps: removing the first-level groove etching mask or removing the Nth-level groove etching mask; and carrying out epitaxial backfilling and polishing processes to form a multi-stage super junction column region, wherein the multi-stage super junction column region comprises N single-stage column regions.
Further, the side wall of the multistage super junction column region is vertically stepped, and the width of the N single-stage column regions is gradually reduced from the top to the bottom of the multistage super junction column region; or the side walls of the multistage super junction column regions are vertical, and the widths of the N single-stage column regions are the same; or the side walls of the N single-stage column regions are arc-shaped.
Further, the doping concentration of the N single-stage column regions is gradually reduced from the top to the bottom of the multi-stage super junction column regions.
Further, the width of the mth-level trench is equal to the width of the (m-1) -level trench minus twice the thickness of the (m-1) -level trench sidewall protection layer, wherein m is a natural number from 1 to N.
Further, the depth of the first-stage groove is determined by the depth of the multi-stage groove and the total stage number, wherein the total stage number is N. According to another embodiment of the present invention, a multi-level super junction structure is provided, including: epitaxial layer and multistage super junction post district, multistage super junction post district includes a plurality of single-stage posts district, a plurality of single-stage posts district corresponds a plurality of single-stage grooves, the single-stage groove is formed by many times self-align sculpture, the self-align sculpture includes: and performing multiple self-aligned etching by using the surface etching mask and the groove side wall protection layer.
The multistage super junction structure and the self-aligning preparation method thereof can realize regulation and control of the inclination angle of the side wall of the super junction groove, and can effectively reduce the influence caused by the side etching effect during deep groove etching by forming the groove side wall protective layer and then performing multistage etching, so that the super junction deep groove keeps relatively high verticality, and the performance of a super junction device is improved. The preparation of the multistage super junction groove is realized by depositing a protective layer, carrying out non-selective etching on the groove side wall protective layer to form an opening, and carrying out self-aligned etching and multistage etching. According to the method, an additional alignment process is not added, and the super junction groove with any side wall inclination angle can be realized by adjusting the thickness of the protective layer and the etching level. Aiming at the problem of low etching selection ratio of the silicon carbide material under the conventional nonmetal mask, the method adopts a mode of multiple mask growth, and uses the difference of the growth thickness of the mask inside and outside the groove, so that the effect of dynamic mask thickening can be realized, and the method is favorable for deep groove etching.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a flow chart of a method for self-aligned fabrication of a multi-level super junction structure according to an embodiment of the present invention;
fig. 2-7 are schematic cross-sectional views illustrating a process flow for fabricating the multi-level super junction structure 100 shown in fig. 7 according to an embodiment of the present invention, wherein the cross-sectional view of fig. 2 corresponds to step S1 in fig. 1, and the cross-sectional view of fig. 3 corresponds to step S2 in fig. 1; the cross-sectional view of fig. 4 corresponds to step S3 in fig. 1, the cross-sectional view of fig. 5 corresponds to step SN in fig. 1, the cross-sectional view of fig. 6 corresponds to step SN +1 in fig. 1, and the cross-sectional view of fig. 7 corresponds to step SN +2 in fig. 1;
fig. 8-12 are schematic cross-sectional views illustrating a process flow for fabricating the multi-level super junction structure 200 shown in fig. 11 according to an embodiment of the present invention, wherein the cross-sectional view of fig. 8 corresponds to step S1 in fig. 1, and the cross-sectional view of fig. 9 corresponds to step S2 in fig. 1; the cross-sectional view of fig. 10 corresponds to step S3 in fig. 1, the cross-sectional view of fig. 11 corresponds to step SN +1 in fig. 1, and the cross-sectional view of fig. 12 corresponds to step SN +2 in fig. 1, (when N =3, the cross-sectional view of fig. 11 corresponds to step S4 in fig. 1, and the cross-sectional view of fig. 12 corresponds to step S5 in fig. 1);
FIGS. 13-17 are schematic cross-sectional views illustrating a process flow for fabricating the multi-level super junction structure 300 shown in FIG. 17, wherein the cross-sectional view of FIG. 13 corresponds to step S1 in FIG. 1, and the cross-sectional view of FIG. 14 corresponds to step S2 in FIG. 1; the cross-sectional view of fig. 15 corresponds to step SN in fig. 1, the cross-sectional view of fig. 16 corresponds to step SN +1 in fig. 1, and the cross-sectional view of fig. 17 corresponds to step SN +2 in fig. 1.
Detailed Description
Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, and it should be noted that the embodiments described herein are only for illustration and are not intended to limit the present invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be understood by those of ordinary skill in the art that these specific details are not required in order to practice the present invention. Furthermore, in some embodiments, well-known circuits, materials, or methods have not been described in detail in order to avoid obscuring the present invention.
Throughout the specification, reference to "one embodiment," "an embodiment," "one example," or "an example" means: the particular features, structures, or characteristics described in connection with the embodiment or example are included in at least one embodiment of the invention. Thus, the appearances of the phrases "in one embodiment," "in an embodiment," "one example" or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combination and/or sub-combination in one or more embodiments or examples. Further, it will be understood by those of ordinary skill in the art that the drawings provided herein are for illustrative purposes, wherein like reference numerals refer to like elements, but not limited to the fact that the element structures must be identical. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The self-aligned preparation method of the multi-stage super junction structure in the embodiment of the invention comprises the steps of growing a surface etching mask (for example, the growing surface etching mask can be used for etching a first-stage trench corresponding to the step S1 in the figure 1) and forming a trench side wall protection layer for multiple times (for example, the forming of the trench side wall protection layer for multiple times can be used for forming the first-stage trench side wall protection layer to form the N-1-stage trench side wall protection layer in the steps S2 to SN in the figure 1, N is a natural number which is greater than or equal to 2), and performing self-aligned etching for multiple times by using the surface etching mask and the trench side wall protection layer (for example, performing self-aligned etching for multiple times can be used for performing self-aligned etching for the first time to perform self-aligned etching for the N-1 time in the steps S2 to SN in the figure 1) to form the multi-stage trench. The depth of the groove side wall protective layer corresponding to each self-aligned etching can be larger than the depth of the groove side wall protective layer corresponding to the previous self-aligned etching, the corresponding groove side wall protective layer can be reserved until the corresponding groove side wall protective layer is consumed or after each self-aligned etching, the depth of the first-stage groove can be determined by the depth of a plurality of stages of grooves and the total stages, for example, the depth of each stage of groove is uniform, the depth of each stage of groove is 25 micrometers, and the depth of the first-stage groove 3 can be 5 micrometers. Forming the trench sidewall protection layer may be accomplished by depositing a protection layer and etching away the protection layer at the bottom of the trench for each level. The self-aligned preparation method may further include: get rid of surface etching mask with slot lateral wall protective layer forms multistage super knot post district after carrying out epitaxial backfill and polishing process, multistage super knot post district includes a plurality of single-stage post districts, and wherein the top and the bottom in adjacent single-stage post district link to each other, and multistage super knot post district lateral wall can be perpendicularly and be the echelonment, by the top to the bottom in multistage super knot post district, and the width in single-stage post district can reduce gradually, or multistage super knot post district lateral wall can be perpendicular, and the width in every single-stage post district can be the same, or the lateral wall in every single-stage post district can present the arc, from the top to the bottom in multistage super knot post district, and the doping concentration in single-stage post district can reduce gradually.
Fig. 1 is a flow chart of a self-aligned preparation method of a multi-level super junction structure according to an embodiment of the invention. The flow of the self-aligned preparation method of the multi-level super junction structure may include steps S1 to SN +2, where N is a natural number greater than or equal to 2, or N is a natural number greater than or equal to 3.
And step S1, etching a first-stage groove by using the first-stage groove etching mask. The depth of the first-stage groove is determined by the depth of the multi-stage groove and the total stage number, wherein the total stage number is N.
And step S2, forming a first-stage groove side wall protection layer, and performing first self-aligned etching by using a second-stage groove etching mask, wherein the second-stage groove etching mask comprises the first-stage groove side wall protection layer and a first-stage groove etching mask.
And step S3, forming a second-stage groove side wall protection layer, and performing second self-aligned etching by using a third-stage groove etching mask, wherein the third-stage groove etching mask comprises the second-stage groove side wall protection layer and a second-stage groove etching mask after the first self-aligned etching.
… …, where the ellipses may include step 4 through step SN-1: and performing the self-aligned etching for the third time to the self-aligned etching for the N-1 st time according to the same process method for performing the self-aligned etching for the second time.
And SN, forming an N-1 level groove side wall protection layer, and performing N-1 self-aligned etching by using an N-level groove etching mask to form a multi-level groove, wherein the N-level groove etching mask comprises the N-1 level groove side wall protection layer and an N-1 level groove etching mask after N-2 self-aligned etching. Wherein the mth self-aligned etching can be performed until the mth trench sidewall protection layer is consumed; or the mth-level trench sidewall protection layer can be remained after the mth self-aligned etching, wherein m is a natural number from 1 to N. Wherein the depth of the m-1 th level trench sidewall protection layer corresponding to the m-th self-aligned etch may be greater than the depth of the m-2 th level trench sidewall protection layer corresponding to the m-1 st self-aligned etch. Wherein forming the mth level trench sidewall protection layer comprises: forming an m-1 level protective layer on the side wall and the bottom of the m-1 level groove; and non-selectively etching the m-1 level protective layer to form an m-level groove side wall protective layer, wherein m is a natural number from 1 to N, the thickness of the m-1 level protective layer on the first level groove etching mask can be larger than that of the m-1 level protective layer on the bottom of the m-1 level groove, and the non-selective etching to form the m-level groove side wall protective layer comprises the following steps: and removing the m-1 level protective layer on the bottom of the m-1 level groove by using the characteristic of plasma dry etching anisotropy. Wherein the width of the mth-level trench may be equal to the width of the m-1-level trench minus twice the thickness of the m-1-level trench sidewall protection layer, where m is a natural number from 1 to N. When N =2, step SN coincides with step S2, and step S3 may not be included in the manufacturing flow.
And SN +1, removing the first-stage groove etching mask or removing the Nth-stage groove etching mask. And when the mth self-aligned etching is performed until the mth level groove side wall protection layer is consumed, the step SN +1 comprises removing the first level groove etching mask, and when the mth level groove side wall protection layer is reserved after the mth self-aligned etching, the step SN +1 comprises removing the nth level groove etching mask.
And step SN +2, carrying out epitaxial backfill and polishing processes to form a multi-stage super junction column region. The multistage super junction column region comprises N single-stage column regions, the side wall of the multistage super junction column region can be vertically stepped, and the width of the N single-stage column regions is gradually reduced from the top to the bottom of the multistage super junction column region; or the side walls of the multistage super junction column regions can be vertical, and the widths of the N single-stage column regions can be the same; or the sidewalls of the N single stage column regions may exhibit arcs, and the maximum width of each arc may be the same. Wherein the doping concentration of the N single-level column regions can be gradually reduced from the top to the bottom of the multi-level super junction column region.
In the preparation method, the more etching stages are set, the thinner the thickness of the protective layer is, and the higher the smoothness of the side wall of the formed multistage super junction column region is. The super junction column region with any side wall angle can be formed by adjusting the thickness of the protective layer and the depth of each stage of etching according to requirements, and the performance optimization design of the super junction device is facilitated.
Fig. 2-7 are schematic cross-sectional views illustrating a process flow for fabricating the multi-level super junction structure 100 shown in fig. 7 according to an embodiment of the present invention. The multi-level super junction structure 100 shown in fig. 7 includes an epitaxial layer 1 and a multi-level super junction pillar region 26. The multi-level super junction pillar region 26 includes N single-level pillar regions 27 (N =5 in the embodiment shown in fig. 7), and the multi-level super junction pillar region 26 and the N single-level pillar regions 27 may be P-type doped. The width of each single-stage column region 27 can be different according to the different inclination angles of the side walls of the multi-stage super junction column region 26, and the width of the single-stage column region 27 can be gradually reduced from the top to the bottom of the multi-stage super junction column region 26. The width of each single-level pillar region 27 may be the same when the sidewalls of the multi-level super junction pillar region 26 are vertical. The depth of each single-stage column region 27 can be different, with the total depth of all single-stage column regions 27 being equal to the depth of the multi-stage super junction column region 26. The doping concentration of each single-level pillar region 27 may be set to be the same under a conventional one-time epitaxial backfill process. In order to further optimize the super junction electric field distribution, the preferable scheme may be that the doping concentration of the single-stage column region 27 is gradually reduced from the top to the bottom of the multi-stage super junction column region 26.
Wherein the cross-sectional view of fig. 2 corresponds to step S1 in fig. 1, a first level trench etching mask 2 is formed on the epitaxial layer 1, and a first level trench 3 is etched. Wherein the epitaxial layer 1 may be N-type doped, and the first-level trench etching mask 2 may be SiO2Or Si3N4Or a multi-layer mask. The depth of the first-stage trench 3 is related to the depth of the multi-stage trench 12 to be formed as shown in fig. 6 and the total number of stages, for example, the depth of the multi-stage trench 12 is 25 μm, the total number of stages is 5, and the depths of the trenches of the respective stages are uniform, so that the depth of the first-stage trench 3 may be 5 μm (equal to the depth of the multi-stage trench 12 divided by the total number of stages).
The cross-sectional view of fig. 3 corresponds to step S2 in fig. 1, and step S2 includes steps S2a, S2b, and S2 c.
Step S2a, growing a first-level protective layer 4 on the surfaces of the first-level trench etching mask 2 and the first-level trench 3, wherein the first-level protective layer 4 can be made of SiO2Or Si3N4. The thickness of the first-level protection layer 4 may be equal to the thickness of the first-level trench sidewall protection layer 5 to be formed, and when considering the undercut effect loss, the thickness of the first-level protection layer 4 should be greater than the thickness of the first-level trench sidewall protection layer 5 to be formed. For example, to form the first-level trench sidewall protection layer 5 with a thickness of 0.5 μm, the thickness of the first-level protection layer 4 is 0.6 μm under the process condition of 0.1 μm undercut loss. In addition, when a dynamic mask thickening effect is requiredThe difference in the growth rates inside and outside the groove during the formation of the first level protective layer 4 may be used so that the thickness of the first level protective layer 4 on the first level trench etch mask 2 is greater than the thickness of the first level protective layer 4 on the bottom of the first level trench 3.
Step S2b, performing non-selective etching on the first-stage protective layer 4 to obtain a first-stage trench sidewall protective layer 5, and removing the first-stage protective layer 4 on the bottom of the first-stage trench 3 by using the characteristic of plasma dry etching anisotropy, so that the first-stage trench sidewall protective layer 5 in the first-stage trench 3 can be better retained.
Step S2c, performing self-aligned etching using the first-level trench etching mask 2 and the first-level trench sidewall protection layer 5 as the second-level etching mask 25 to form a second-level trench 6, where the width of the second-level trench 6 is equal to the width of the first-level trench 3 minus the thickness of the first-level trench sidewall protection layer 5.
The cross-sectional view of fig. 4 corresponds to step S3 in fig. 1, and step S3 includes steps S3a, S3b, and S3 c.
Step S3a, growing a second-level protective layer 7 on the surfaces of the second-level trench etching mask 25 and the second-level trench 6, wherein the material of the second-level protective layer 7 can be SiO2Or Si3N4。
Step S3b, performing non-selective etching on the second-stage protective layer 7 to obtain a second-stage trench sidewall protective layer 8, and removing the second-stage protective layer 7 on the bottom of the second-stage trench 6 by using the characteristic of plasma dry etching anisotropy, so that the second-stage trench sidewall protective layer 8 in the second-stage trench 6 can be better retained.
And step S3c, self-alignment etching is carried out by using the second-stage groove etching mask 25 and the second-stage groove side wall protection layer 8 as a third-stage etching mask 35 to form a third-stage groove 9, wherein the width of the third-stage groove 9 is equal to the width of the second-stage groove 6 minus the thickness of the second-stage groove side wall protection layer 8.
The cross-sectional view of fig. 5 corresponds to step SN of fig. 1, and as shown in fig. 5, N =5, the fourth level trench sidewall protection layer 13 is formed, and a fourth self-aligned etching is performed using the fourth level trench etching mask 45 (the fourth level trench etching mask 45 includes the third level trench etching mask 35 and the third level trench sidewall protection layer 10) and the fourth level trench sidewall protection layer 13 as the fifth level trench etching mask 55, so as to form a multi-level trench, for example, the multi-level trench in the embodiment shown in fig. 5 is a five-level trench. Wherein corresponding trench sidewall protection layers are retained for each self-aligned etch, e.g., the first level trench sidewall protection layer 5, the second level trench sidewall protection layer 8, the third level trench sidewall protection layer 10, and the fourth level trench sidewall protection layer 13 are retained.
In other embodiments of the present invention, the forming manner of each trench is the same, and the same trench forming process can be continuously adopted: growing a new primary protective layer, forming a new primary groove side wall protective layer after non-selective etching, and obtaining a new primary groove by self-aligned etching; the process is cycled until the desired number of trench levels is achieved.
The cross-sectional view of fig. 6 corresponds to step SN +1 of fig. 1, where in the embodiment of fig. 5, N =5, and the fifth level trench etch mask 55 is removed.
The cross-sectional view of fig. 7 corresponds to SN +2 of fig. 1, and epitaxial backfill and polishing processes are performed to form the multi-level super junction pillar region 26, where N =5 in the embodiment shown in fig. 5, and the multi-level super junction pillar region 26 is formed as a five-level super junction pillar region. In the embodiment shown in fig. 7, the sidewall of the multi-stage super junction column region 26 is vertically stepped, the width of the single-stage column region 27 gradually decreases from the top to the bottom of the multi-stage super junction column region 26, and the doping concentration of the single-stage column region 27 may gradually decrease from the top to the bottom of the multi-stage super junction column region 26.
Fig. 8-12 are schematic cross-sectional views illustrating a process flow for fabricating the multi-level super junction structure 200 shown in fig. 11 according to an embodiment of the present invention, wherein the multi-level super junction structure 200 includes a multi-level super junction pillar region 26.
Wherein the cross-sectional view of fig. 8 corresponds to step S1 in fig. 1, a first level trench etch mask 2 is formed on the epitaxial layer 1, and a first level trench 3 is etched. Wherein the epitaxial layer 1 may be N-type doped, and the first-level trench etching mask 2 may be SiO2Or Si3N4Or a multi-layer mask.
The cross-sectional view of fig. 9 corresponds to step S2 in fig. 1, and step S2 includes steps S2a, S2b, and S2 c.
Step S2a, growing a first-level protective layer 4 on the surfaces of the first-level trench etching mask 2 and the first-level trench 3, wherein the first-level protective layer 4 can be made of SiO2Or Si3N4. The thickness of the first-level protection layer 4 may be equal to the thickness of the first-level trench sidewall protection layer 5 to be formed, and when considering the undercut effect loss, the thickness of the first-level protection layer 4 should be greater than the thickness of the first-level trench sidewall protection layer 5 to be formed. For example, to form the first-level trench sidewall protection layer 5 with a thickness of 0.5 μm, the first-level protection layer 4 has a thickness of 0.6 μm under the process condition of 0.1 μm undercut loss. In addition, when a dynamic mask thickening effect is required, the difference of the inner and outer growth rates of the time slots for forming the first-stage protective layer 4 can be used, so that the thickness of the first-stage protective layer 4 on the first-stage trench etching mask 2 is larger than that of the first-stage protective layer 4 on the bottom of the first-stage trench 3.
Step S2b, performing non-selective etching on the first-stage protective layer 4 to obtain a first-stage trench sidewall protective layer 5, and removing the first-stage protective layer 4 on the bottom of the first-stage trench 3 by using the characteristic of plasma dry etching anisotropy, so that the first-stage trench sidewall protective layer 5 in the first-stage trench 3 can be better retained. The first level trench sidewall protection layer 5 may be chosen to have a small thickness value, such as 50 nm.
Step S2c, performing self-aligned etching using the first-level trench etching mask 2 and the first-level trench sidewall protection layer 5 as the second-level etching mask 25 until the first-level trench sidewall protection layer 5 is consumed (i.e., the first-level trench sidewall protection layer 5 is completely removed by the side etching effect), and forming the second-level trench 6, as shown in the embodiment of fig. 9, the width of the second-level trench 6 is equal to the width of the first-level trench 3, and the second trench depth h2 after the second-level trench 6 is formed is greater than the first trench depth h1 after the first-level trench 3 is formed.
The cross-sectional view of fig. 10 corresponds to step S3 in fig. 1, and step S3 includes steps S3a, S3b, and S3 c.
Step S3a, growing a second layer on the surface of the first-stage trench etching mask 2The secondary protective layer 7, the material of the secondary protective layer 7 can be SiO2Or Si3N4。
Step S3b, performing non-selective etching on the second-stage protective layer 7 to obtain a second-stage trench sidewall protective layer 8, and removing the second-stage protective layer 7 on the bottom of the second-stage trench 6 by using the characteristic of plasma dry etching anisotropy, so that the second-stage trench sidewall protective layer 8 in the second-stage trench 6 can be better retained.
Step S3c, performing self-aligned etching using the second-level trench etching mask 25 (before step 3c begins, the first-level trench sidewall protection layer 5 in the second-level trench etching mask 25 is completely removed by the lateral etching effect, at this time, the second-level trench etching mask 25 is equal to the first-level trench etching mask 2) and the second-level trench sidewall protection layer 8 as the third-level etching mask 35, to form a third-level trench 9, wherein the width of the third-level trench 9 is equal to the width of the second-level trench 6, and the third-level trench depth h3 after the third-level trench 9 is formed is greater than the second-level trench depth h2 after the second-level trench 6 is formed.
The cross-sectional view of fig. 11 corresponds to step SN +1 of fig. 1, where N =3 in the embodiment shown in fig. 5, where the second-level trench sidewall protection layer 8 has been completely removed by the undercut effect, and step S4 includes removing the first-level trench etch mask 2.
The cross-sectional view of fig. 12 corresponds to SN +2 of fig. 1, and epitaxial backfill and polishing processes are performed to form the multi-level super junction pillar region 26, where N =3 in the embodiment shown in fig. 12, and the multi-level super junction pillar region 26 is formed as a three-level super junction pillar region. In the embodiment shown in fig. 12, the sidewalls of the multi-level super junction pillar region 26 are vertical.
Fig. 13-17 are schematic cross-sectional views illustrating a process flow for fabricating the multi-level super-junction structure 300 shown in fig. 17 according to another embodiment of the present invention, wherein the multi-level super-junction structure 300 shown in fig. 17 comprises a gourd-shaped multi-level super-junction structure under consideration of lateral etching of a semiconductor.
Wherein the cross-sectional view of fig. 13 corresponds to step S1 in fig. 1, a first level trench etch mask 2 is formed on the epitaxial layer 1, and a first level trench 3 is etched. Wherein the epitaxial layer 1 may beThe first level trench etch mask 2 may be SiO selective with N-type doping2Or Si3N4Or a multi-layer mask. In the embodiment shown in fig. 13, the sidewall of the first-level trench 3 is curved in consideration of the case of semiconductor lateral etching.
The cross-sectional view of fig. 14 corresponds to step S2 in fig. 1, and step S2 includes steps S2a, S2b, and S2 c.
Step S2a, growing a first-level protective layer 4 on the surfaces of the first-level trench etching mask 2 and the first-level trench 3, wherein the first-level protective layer 4 can be made of SiO2Or Si3N4. The thickness of the first-level protection layer 4 may be equal to the thickness of the first-level trench sidewall protection layer 5 to be formed, and when considering the undercut effect loss, the thickness of the first-level protection layer 4 should be greater than the thickness of the first-level trench sidewall protection layer 5 to be formed. For example, to form the first-level trench sidewall protection layer 5 with a thickness of 0.5 μm, the thickness of the first-level protection layer 4 is 0.6 μm under the process condition of 0.1 μm undercut loss. In addition, when a dynamic mask thickening effect is required, the difference of the inner and outer growth rates of the time slots for forming the first-stage protective layer 4 can be used, so that the thickness of the first-stage protective layer 4 on the first-stage trench etching mask 2 is larger than that of the first-stage protective layer 4 on the bottom of the first-stage trench 3.
Step S2b, performing non-selective etching on the first-stage protective layer 4 to obtain a first-stage trench sidewall protective layer 5, and removing the first-stage protective layer 4 on the bottom of the first-stage trench 3 by using the characteristic of plasma dry etching anisotropy, so that the first-stage trench sidewall protective layer 5 in the first-stage trench 3 can be better retained. The first-level trench sidewall protection layer 5 is curved and may be chosen to have a small thickness, e.g. 50 nm.
Step S2c, performing self-aligned etching using the first-level trench etching mask 2 and the first-level trench sidewall protection layer 5 as the second-level etching mask 25 until the first-level trench sidewall protection layer 5 is consumed (i.e. the first-level trench sidewall protection layer 5 is completely removed by the lateral etching effect), so as to form the second-level trench 6, where in the embodiment shown in fig. 14, the maximum width of the second-level trench 6 is equal to the maximum width of the first-level trench 3.
The cross-sectional view of fig. 15 corresponds to step SN of fig. 1, and in the embodiment shown in fig. 15, N =5, and the multilevel trench 24 formed after four times of self-aligned etching is a five-level trench. And each self-alignment etching is carried out until the corresponding groove side wall protection layer is consumed, and a first-stage groove etching mask 2 is left, for example, the mth self-alignment etching is carried out until the mth groove side wall protection layer is consumed, wherein m is one natural number from 1 to N.
The cross-sectional view of fig. 16 corresponds to step SN +1 in fig. 1, removing the first level trench etch mask 2.
The cross-sectional view of fig. 17 corresponds to SN +2 of fig. 1, and epitaxial backfill and polishing processes are performed to form the multi-level super junction pillar region 26, where N =5 in the embodiment shown in fig. 17, and the multi-level super junction pillar region 26 is formed as a five-level super junction pillar region. In the embodiment shown in fig. 17, the multi-stage super junction region 26 has a gourd shape with curved sidewalls.
While the present invention has been described with reference to several exemplary embodiments, it is understood that the terminology used is intended to be in the nature of words of description and illustration, rather than of limitation. As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiments are not limited by any of the details of the foregoing description, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the meets and bounds of the claims, or equivalences of such meets and bounds are therefore intended to be embraced by the appended claims.
Claims (20)
1. The self-alignment preparation method of the multilevel super junction structure is characterized by comprising the steps of growing a surface etching mask, forming a groove side wall protection layer for multiple times, and performing self-alignment etching for multiple times by using the surface etching mask and the groove side wall protection layer to form a multilevel groove.
2. The method of claim 1, wherein the depth of the trench sidewall protection layer corresponding to each self-aligned etch is greater than the depth of the trench sidewall protection layer corresponding to the previous self-aligned etch.
3. The self-aligned preparation method of the multi-level super junction structure according to claim 1, wherein each self-aligned etching is performed until the corresponding trench sidewall protection layer is consumed; or, the corresponding groove side wall protection layer is reserved after each self-aligned etching.
4. The method of self-aligned fabrication of a multi-level super junction structure of claim 1, wherein a depth of a first level trench of said multi-level trenches is determined by a depth of said multi-level trench and a total number of levels.
5. The self-aligned method of fabricating a multi-level super junction structure according to claim 1, wherein forming a trench sidewall protection layer comprises: and depositing a protective layer, and etching the protective layer at the bottom of each level of groove to form a corresponding groove side wall protective layer.
6. The self-aligned fabrication method of a multi-level super junction structure according to claim 1, further comprising: and removing the surface etching mask or removing the surface etching mask and the groove side wall protection layer, and performing epitaxial backfilling and polishing processes to form a multi-stage super junction column region, wherein the multi-stage super junction column region comprises a plurality of single-stage column regions.
7. The self-aligned preparation method of the multi-level super junction structure according to claim 6, wherein the top of the adjacent single-pole column region is connected with the bottom, the sidewall of the multi-level super junction column region is vertically stepped, and the width of the single-level column region is gradually reduced from the top to the bottom of the multi-level super junction column region; or the side walls of the multistage super junction column regions are vertical, and the width of each single-stage column region is the same; alternatively, the sidewalls of each single stage column section exhibit an arcuate shape.
8. The self-aligned preparation method of the multi-level super junction structure according to claim 6, wherein the doping concentration of the single-level column region is gradually decreased from the top to the bottom of the multi-level super junction column region.
9. The self-aligned preparation method of the multilevel super junction structure is characterized by comprising the following steps:
etching a first-stage groove by using a first-stage groove etching mask, wherein the first-stage groove etching mask is formed on the surface of the semiconductor;
and forming a first-stage groove side wall protection layer, and performing first self-aligned etching by using a second-stage groove etching mask, wherein the second-stage groove etching mask comprises a first-stage groove etching mask and a first-stage groove side wall protection layer.
10. The self-aligned preparation method of the multi-level super junction structure according to claim 9, further comprising performing a second self-aligned etching to an N-1 self-aligned etching, wherein N is a natural number greater than or equal to 3, wherein
Performing a second self-aligned etch comprises: forming a second-stage groove side wall protective layer, and performing second self-aligned etching by using a third-stage groove etching mask, wherein the third-stage groove etching mask comprises the second-stage groove side wall protective layer and a second-stage groove etching mask after the first self-aligned etching;
the self-aligned etching for the (N-1) th time comprises the following steps: and forming an N-1 level groove side wall protection layer, and performing N-1 time self-alignment etching by using an N level groove etching mask to form a multi-level groove, wherein the N level groove etching mask comprises an N-1 level groove side wall protection layer and an N-1 level groove etching mask after N-2 times self-alignment etching, and the same process method is adopted from the second time self-alignment etching to the N-1 time self-alignment etching.
11. The method for self-aligned fabricating a multi-level super junction structure according to claim 9, wherein the mth self-aligned etching is performed until the mth trench sidewall protection layer is consumed; or the mth-level groove side wall protection layer is reserved after the mth self-alignment etching, wherein m is a natural number from 1 to N.
12. The method of self-aligned fabricating a multi-level super junction structure according to claim 9, wherein forming the m-th level trench sidewall protection layer comprises:
forming an m-1 level protective layer on the side wall and the bottom of the m-1 level groove;
and non-selectively etching the m-1 level protective layer to form an m level groove side wall protective layer, wherein m is a natural number from 1 to N.
13. The self-aligned preparation method of the multi-level super junction structure according to claim 12, wherein the thickness of the m-1 level protection layer on the first level trench etching mask is greater than the thickness of the m-1 level protection layer on the bottom of the m-1 level trench.
14. The self-aligned preparation method of the multi-level super junction structure according to claim 12, wherein the forming of the m-th level trench sidewall protection layer by the non-selective etching comprises: and removing the m-1 level protective layer on the bottom of the m-1 level groove by using the characteristic of plasma dry etching anisotropy, wherein m is one natural number from 1 to N.
15. The self-aligned preparation method of the multi-level super junction structure of claim 9, wherein the width of the mth level trench is equal to the width of the m-1 level trench minus two times the thickness of the m-1 level trench sidewall protection layer, wherein m is a natural number from 1 to N.
16. The self-aligned fabrication method of a multi-level super junction structure according to claim 9, further comprising:
removing the first-level groove etching mask or removing the Nth-level groove etching mask; and
and carrying out epitaxial backfilling and polishing processes to form a multi-stage super junction column region, wherein the multi-stage super junction column region comprises N single-stage column regions.
17. The self-aligned preparation method of the multi-level super junction structure according to claim 16, wherein the sidewall of the multi-level super junction pillar region is vertically stepped, and the width of the N single-level pillar regions gradually decreases from the top to the bottom of the multi-level super junction pillar region; or the side walls of the multistage super junction column regions are vertical, and the widths of the N single-stage column regions are the same; or the side walls of the N single-stage column regions are arc-shaped.
18. The self-aligned preparation method of the multi-level super junction structure according to claim 16, wherein the doping concentration of the N single-level column regions is gradually decreased from the top to the bottom of the multi-level super junction column region.
19. The method of self-aligned fabricating a multi-level super junction structure according to claim 10, wherein a depth of the first-level trench is determined by a depth of the multi-level trench and a total number of levels, wherein the total number of levels is N.
20. A multi-level super junction structure, comprising: epitaxial layer and multistage super junction post district, multistage super junction post district includes a plurality of single-stage posts district, a plurality of single-stage posts district corresponds a plurality of single-stage grooves, the single-stage groove is formed by many times self-align sculpture, the self-align sculpture includes: and performing multiple self-aligned etching by using the surface etching mask and the groove side wall protection layer.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115377220A (en) * | 2022-09-14 | 2022-11-22 | 江苏美微科半导体有限公司 | Stepped gradient epitaxial deep trench super junction and preparation method thereof |
| CN117293023A (en) * | 2023-11-21 | 2023-12-26 | 深圳基本半导体有限公司 | Method for plasma etching of silicon carbide |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004072068A (en) * | 2002-06-14 | 2004-03-04 | Fuji Electric Holdings Co Ltd | Semiconductor device |
| JP2009141307A (en) * | 2007-11-15 | 2009-06-25 | Fuji Electric Device Technology Co Ltd | Method of manufacturing semiconductor device |
| JP2009188025A (en) * | 2008-02-04 | 2009-08-20 | Sanken Electric Co Ltd | Method of manufacturing semiconductor apparatus |
| US20130105947A1 (en) * | 2011-10-26 | 2013-05-02 | Zeon Corporation | High aspect ratio and reduced undercut trench etch process for a semiconductor substrate |
| CN103560086A (en) * | 2013-10-18 | 2014-02-05 | 西安龙腾新能源科技发展有限公司 | Super junction semiconductor device manufacturing method capable of improving avalanche capacity |
| CN109461767A (en) * | 2018-10-25 | 2019-03-12 | 深圳市金鑫城纸品有限公司 | A kind of super-junction structure and preparation method thereof |
| CN111785625A (en) * | 2020-06-30 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | Technological method of super junction device |
-
2022
- 2022-05-18 CN CN202210537454.7A patent/CN114649406A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004072068A (en) * | 2002-06-14 | 2004-03-04 | Fuji Electric Holdings Co Ltd | Semiconductor device |
| JP2009141307A (en) * | 2007-11-15 | 2009-06-25 | Fuji Electric Device Technology Co Ltd | Method of manufacturing semiconductor device |
| JP2009188025A (en) * | 2008-02-04 | 2009-08-20 | Sanken Electric Co Ltd | Method of manufacturing semiconductor apparatus |
| US20130105947A1 (en) * | 2011-10-26 | 2013-05-02 | Zeon Corporation | High aspect ratio and reduced undercut trench etch process for a semiconductor substrate |
| CN103560086A (en) * | 2013-10-18 | 2014-02-05 | 西安龙腾新能源科技发展有限公司 | Super junction semiconductor device manufacturing method capable of improving avalanche capacity |
| CN109461767A (en) * | 2018-10-25 | 2019-03-12 | 深圳市金鑫城纸品有限公司 | A kind of super-junction structure and preparation method thereof |
| CN111785625A (en) * | 2020-06-30 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | Technological method of super junction device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115377220A (en) * | 2022-09-14 | 2022-11-22 | 江苏美微科半导体有限公司 | Stepped gradient epitaxial deep trench super junction and preparation method thereof |
| CN117293023A (en) * | 2023-11-21 | 2023-12-26 | 深圳基本半导体有限公司 | Method for plasma etching of silicon carbide |
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