CN216624280U - Semiconductor memory device with a plurality of memory cells - Google Patents
Semiconductor memory device with a plurality of memory cells Download PDFInfo
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- CN216624280U CN216624280U CN202123011922.7U CN202123011922U CN216624280U CN 216624280 U CN216624280 U CN 216624280U CN 202123011922 U CN202123011922 U CN 202123011922U CN 216624280 U CN216624280 U CN 216624280U
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Abstract
The application discloses a semiconductor storage device, which can overcome the problems in the prior art and optimize the yield of semiconductor products. The semiconductor storage device comprises a substrate, a contact window is formed on the surface of the substrate, and the contact window exposes the inside of the substrate; the plurality of stacked structures are formed on the surface of the substrate, and the contact window is positioned between two adjacent stacked structures; the first material layer is distributed between two adjacent stacked structures and is positioned in the contact window, doped ions are contained in the first material layer, and at most one hollow hole is formed in the first material layer; the first material layer comprises a plurality of material sublayers, and the doped ion concentration of each material sublayer is different and is sequentially reduced upwards along the direction vertical to the upper surface of the substrate.
Description
Technical Field
The present application relates to the field of semiconductor devices, and more particularly, to semiconductor memory devices.
Background
In the prior art, when a semiconductor memory is prepared, the problems of high manufacturing difficulty and complex preparation process exist. For example, when the node contact is fabricated, in order to ensure that the node contact can be electrically connected to the memory transistor well, the requirement on the fabrication process of the node contact is high, for example, the deposition process used in the process of fabricating the node contact is high, and the deposition material is required to have a good filling property, which results in strict requirements on the fabrication of the node contact and a slow fabrication process, which may not only affect the production efficiency of the memory, but also lower the utilization rate of the semiconductor processing equipment. Moreover, if the quality of the semiconductor product is not up to standard, the electrical property of the finally prepared semiconductor product is easily damaged.
It is desirable to provide a technique for reducing the difficulty of manufacturing a memory, simplifying the process, and improving the yield of semiconductor products.
SUMMERY OF THE UTILITY MODEL
In view of this, the present application provides a semiconductor memory device, which can reduce the difficulty of manufacturing a memory, simplify the process, and optimize the yield of semiconductor products.
The application provides a semiconductor storage device, including:
the surface of the substrate is provided with a contact window, and the contact window exposes the inside of the substrate;
the plurality of stacked structures are formed on the surface of the substrate, and the contact window is positioned between two adjacent stacked structures;
the first material layer is distributed between two adjacent stacked structures and is positioned in the contact window, doped ions are contained in the first material layer, and at most one hollow hole is formed in the first material layer;
the first material layer comprises a plurality of material sublayers, and the doped ion concentration of each material sublayer is different and is sequentially reduced upwards along the direction vertical to the upper surface of the substrate.
Optionally, the first material layer includes a material sub-layer with a dopant ion concentration of 0, and a lowermost surface of the material sub-layer is located below an upper surface of the stack structure.
Optionally, the stacked structure comprises a bit line structure.
Optionally, when the void exists, the void passes through at least two regions in the first material layer, and the two regions have different dopant ion concentrations.
Optionally, when the void is present, a top of the void is lower than an upper surface of the stacked structure.
In this embodiment, the first material layer formed in the contact window includes dopant ions, and the concentration of the dopant ions gradually decreases in a direction perpendicular to the substrate surface, such gradually decreasing concentration of the dopant ions helps prevent the formation of voids, and at most one void is formed inside the first material layer, so that the electrical yield of the semiconductor memory device based on the few voids is higher.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a flowchart illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.
Fig. 2 is a flowchart illustrating a step of forming a first material layer in the contact window according to an embodiment of the present disclosure.
Fig. 3 is a schematic cross-sectional view of a substrate and a surface structure thereof according to an embodiment of the present application.
Fig. 4 is a schematic cross-sectional view of a semiconductor memory device according to an embodiment of the present application.
Fig. 5 is a schematic cross-sectional view illustrating a semiconductor memory device according to an embodiment of the present application.
Fig. 6 is a schematic cross-sectional view illustrating a semiconductor memory device according to an embodiment of the present application.
Fig. 7 is a schematic top view of a semiconductor memory device according to an embodiment of the present application.
Detailed Description
Researches find that the important reason of low yield of the semiconductor device in the prior art is low; when the material layer is filled in the contact window, more than two cavities are easy to appear in the material layer filled in the contact window. These voids are likely to cause electrical damage to the semiconductor device, resulting in poor yield of the semiconductor device.
Research also finds that reducing or removing the cavity 180 of the material layer filled in the contact window 170 can effectively reduce the probability of electrical damage of the semiconductor device, thereby optimizing the yield of the semiconductor device.
The semiconductor memory device will be further described with reference to the drawings and the embodiments.
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.
In this embodiment, the method for manufacturing a semiconductor memory device includes the steps of:
step S101: providing a substrate 101, forming a plurality of stacked structures (132a and 132b) on the surface of the substrate 101, forming a contact window 170 on the surface of the substrate 101, wherein the contact window 170 exposes the inside of the substrate 101 and is located between two adjacent stacked structures (132a and 132 b). The substrate 101 in the step S101 can refer to fig. 3.
Step S102: forming a first material layer 120 in the contact window 170, wherein at most one void 180 is formed inside the first material layer 120, and the first material layer 120 contains dopant ions, and the concentration of the dopant ions gradually decreases in an upward direction perpendicular to the surface of the substrate 101, as shown in fig. 4 or 5.
In this embodiment, the first material layer 120 formed in the contact window 170 contains dopant ions, and the concentration of the dopant ions gradually decreases in a direction perpendicular to the surface of the substrate 101, such gradually decreasing concentration of the dopant ions helps to prevent the formation of the voids 180, and at most one void 180 is formed in the first material layer 120, so that the electrical yield of the semiconductor memory device based on the few voids 180 is higher.
In the embodiment shown in fig. 3, the substrate 101 comprises a semiconductor base. The material of the semiconductor substrate may include silicon (Si), such as crystalline Si, polycrystalline silicon, or amorphous Si. In some embodiments, the semiconductor substrate may comprise a semiconductor material, such as germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP).
In some embodiments, the substrate 101 may have conductive regions formed therein, such as impurity-doped wells, or other structures doped with impurities.
An isolation structure 102 is formed in the substrate 101, and the substrate 101 is divided into a plurality of active regions 1021, and the active regions 1021 may be arranged at equal intervals. The isolation structure 102 may be a Shallow Trench Isolation (STI) structure, and the isolation structure 102 is formed by etching the substrate 101 to form a trench and then filling the trench with an insulating material. The insulating material used for the isolation structure 102 may be at least one of insulating dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride.
The active regions 1021 may have regular shapes, such as long stripes, and be arranged regularly. A gate structure is formed in the active region 1021.
The first material layer 120 includes a silicon layer, and the specific material of the first material layer 120 may be set according to the requirement. In some embodiments, the dopant ions include at least phosphorous ions.
FIG. 7 is a schematic top view of a semiconductor memory device according to an embodiment of the present application
In the embodiment shown in fig. 7, a pad is formed in the contact 110, and a word line WL is also formed in the substrate 101 to intersect the active region 1021. Bit lines 180 are distributed perpendicular to the word lines WL and intersect the active regions 1021, and bit line gates 190 are located at the intersections and connected to the bit lines 180. The bit line 180 is partially located on the bit line gate 190 and partially located on the surface of the other region of the substrate 101.
In one embodiment, the stacked structures (132a and 132b) include bit line structures. In the embodiment shown in fig. 2, the bit line structure at least includes a metal layer 151, and the metal layer 151 includes a single conductive metal material layer or multiple conductive metal material layers. In the embodiment shown in fig. 3, the metal layer 151 only includes a tungsten layer, and actually, in other embodiments, the metal layer 151 may further include a titanium nitride layer. In some embodiments, the metal layer 151 includes a titanium nitride layer and a tungsten layer sequentially stacked in a direction perpendicular to an upper surface of the substrate 101.
In the embodiment shown in fig. 3, the bitline structure further includes a liner 130 disposed under the metal layer 151. The liner 130 is located in the contact portion 110 shown in fig. 7 and includes at least one of an amorphous silicon layer and a phosphorus-doped silicon layer. In fact, in other embodiments, the specific material of the liner 130 may be set as desired.
In the embodiment shown in fig. 3, the stacked structure (132a and 132b) further includes a first insulating layer 103, a second insulating layer 104, a third insulating layer 105, and a first conductive layer 106 disposed below the metal layer 151 and sequentially disposed upward along a direction perpendicular to the surface of the substrate 101.
The material of the first insulating layer 103 and the third insulating layer 105 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxycarbide, silicon oxynitride, and other insulating materials. The first insulating layer 103 and the third insulating layer 105 may have a single-layer structure or a multilayer structure.
The material of the second insulating layer 104 may also include, but is not limited to, insulating materials such as silicon oxide, silicon nitride, silicon oxycarbide, and silicon oxynitride; moreover, the material of the second insulating layer 104 is different from the materials of the first insulating layer 103 and the third insulating layer 105, and the second insulating layer is subsequently used as an etching stop layer, and has different etching selectivity from the first insulating layer 103 and the third insulating layer 105.
In one embodiment, the first conductive layer 106 is an amorphous silicon layer formed on the surface of the third insulating layer 105. In practice, the first conductive layer 106 can also be prepared by using a semiconductor material doped with N-type or P-type dopant ions, such as doped polysilicon, doped amorphous silicon, and the like.
Each of the film layers in the stacked structure (132a and 132b) may be formed on the surface of the substrate 101 by using at least one of chemical vapor deposition, physical vapor deposition, and atomic layer deposition.
In the embodiment shown in fig. 3, the stack structures (132a and 132b) further include isolation structures (including 161, 162, and 163) disposed at sides of the metal layer 151. When the stacked structure (132a and 132b) includes the metal layer 151 and the underlying pad 130 (as shown by 132a in fig. 3), the isolation structure is also provided to the side surface of the pad 130. When the stacked structure (132a and 132b) includes the metal layer 151 and the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, and the first conductive layer 106 disposed below the metal layer 151 in this order upward from the surface of the substrate 101 (as shown in 132b in fig. 3), the isolation structure is also disposed to the side surfaces of the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, and the first conductive layer 106.
The insulation structure includes a first insulation layer 161, a second insulation layer 162, and a third insulation layer 163. In some embodiments, the first isolation layer 161 may be SiN, the second isolation layer 162 may be silicon oxide, and the third isolation layer 163 may be SiN.
In the embodiment shown in fig. 4 and 5, the first material layer 120 fills the contact window 170 and is formed on the upper surface of the stacked structure (132a and 132b) to ensure that the contact window 170 is fully filled.
Referring to fig. 2, a flow chart of an embodiment of a step of forming the first material layer 120 in the contact window 170 is shown.
In this embodiment, forming the first material layer 120 in the contact window 170 at least includes the following steps: step S201: preparing to form the first material layer 120 by using a first precursor and a second precursor, wherein the first precursor contains main material ions, and the second precursor contains the doping ions; step S202: during the process of preparing the first material layer 120, the relative concentration of the second precursor with respect to the first precursor is gradually decreased until the relative concentration of the second precursor with respect to the first precursor is less than or equal to a preset threshold.
In this embodiment, the dopant ions include at least phosphorus ions and the host material ions include at least silicon ions.
In some embodiments, the first material layer 120 may be prepared by taking the first precursor and the second precursor as described above and using an epitaxial growth scheme. The epitaxial (epixy, Epi for short) process is to grow a layer of single crystal material with the same lattice arrangement as the substrate on the substrate, wherein the epitaxial layer can be a homogeneous epitaxial layer (Si/Si) or a heterogeneous epitaxial layer (SiGe/Si or SiC/Si, etc.); there are also many ways to achieve epitaxial growth including Molecular Beam Epitaxy (MBE), ultra-high vacuum chemical vapor deposition (UHV/CVD), atmospheric and reduced pressure epitaxy (ATM & RP Epi), and so on. Only silicon (Si) and silicon germanium (SiGe) epitaxial processes that are widely used in semiconductor integrated circuit production where the substrate 101 is a silicon material will be described herein.
In some embodiments, a silicon-containing gas source, such as Silane (SiH), is often employed4) Dichlorosilane (SiH)2Cl2DCS for short) and trichlorosilane (SiHCl)3TCS) as the first precursor, and Si ions in the industrial gas are the above-mentioned main material ions. The second precursor may be Phosphine (PH)3) And the like.
In this embodiment, since the relative concentration of the second precursor with respect to the first precursor is changed, the user can choose to increase the concentration of the first precursor or decrease the concentration of the second precursor to change the relative concentration according to actual operation.
Specifically, the gradually decreasing the relative concentration of the second precursor with respect to the first precursor includes: 1. and reducing the concentration of the first precursor, and keeping the concentration of the first precursor unchanged until the relative concentration of the second precursor relative to the first precursor is the preset threshold. 2. Gradually increasing the concentration of the second precursor, and keeping the concentration of the second precursor unchanged until the relative concentration of the second precursor relative to the first precursor is the preset threshold.
In an embodiment, the preset threshold is 0. In fact, the size of the preset threshold value can be set according to needs. When the relative concentration of the second precursor with respect to the first precursor is equal to 0, the concentration of the dopant ions of the subsequently formed first material layer 120 is gradually reduced to 0 on the basis of the concentration of the dopant ions of the currently formed first material layer 120.
In some embodiments, the portion of the first material layer 120 higher than the stacked structure (132a and 132b) is not required to contain doping ions, so when the relative concentration of the second precursor with respect to the first precursor is adjusted to be 0, the first material layer 120 is formed below the upper surface of the stacked structure (132a and 132b), and thus the concentration of the doping ions may be equal to 0 when the first material layer 120 is flush with the top of the stacked structure (132a and 132 b).
In some other embodiments, when the relative concentration of the second precursor with respect to the first precursor is 0, the first material layer 120 may also be formed above the upper surface of the stacked structure (132a and 132 b).
In some embodiments, said gradually decreasing the concentration of the second precursor comprises: the concentration of the second precursor decreases in a gradient manner with the reaction time. In this case, the structural diagram of the first material layer 120 obtained can refer to fig. 5, and in the embodiment shown in fig. 5, the first material layer 120 includes three sub-layers, where the first sub-layer 120a has the highest doping ion concentration, the second sub-layer 120b has the second lowest doping ion concentration, and the third sub-layer 120c has the lowest doping ion concentration.
Fig. 5 is merely an example of the first material layer 120 when the concentration of the second precursor is decreased in a gradient manner with the reaction time, and in fact, other numbers of sub-layers may be included in the first material layer 120, and each sub-layer has a gradually decreasing concentration of the dopant ions in an upward direction perpendicular to the substrate 101.
In some other embodiments, the gradually decreasing the concentration of the second precursor comprises: the concentration of the second precursor decreases linearly with reaction time. In this case, a schematic structural diagram of the first material layer 120 may be obtained with reference to fig. 4, in the embodiment shown in fig. 4, the concentration of the dopant ions of the first material layer 120 gradually decreases with the increase of the height.
In these embodiments, the concentration of the dopant ions in the first material layer 120 gradually decreases with the increase of the height, so that the probability of the problem of lattice mismatch caused by the large stress existing between the sub-layers due to the abrupt change of the dopant ion concentration can be reduced.
In fact, other ways may be used to prepare the first material layer 120 as desired. In some embodiments, the forming of the first material layer 120 in the contact window 170 includes at least the following steps: a plurality of material sub-layers are sequentially prepared, and the doping ion concentration of each material sub-layer is different and decreases upwards sequentially along a direction perpendicular to the upper surface of the substrate 101. Regardless of whether the first precursor and the second precursor are used to prepare the first material layer 120, the material layers may be formed in a plurality of material sub-layers that have different dopant ion concentrations and sequentially decrease upward in a direction perpendicular to the upper surface of the substrate 101.
In one embodiment, when the void 180 is present, the void 180 passes through at least two regions of the first material layer 120, and the two regions have different dopant ion concentrations. The void 180 is created in the first region, and in the second region, even the third and fourth regions, the void 180 is closed due to the variation of the concentration of the dopant ions.
When the void 180 is present, the top of the void 180 is lower than the upper surface of the stacked structure (132a and 132 b).
The embodiment of the application also provides a semiconductor storage device.
Referring to fig. 4, the semiconductor memory device includes: a substrate 101, a contact window 170 is formed on the surface, and the contact window 170 exposes the inside of the substrate 101; a plurality of stacked structures (132a and 132b) formed on the surface of the substrate 101, wherein the contact window 170 is located between two adjacent stacked structures (132a and 132 b); the first material layer 120 is disposed between two adjacent stacked structures (132a and 132b) and located in the contact window 170, the first material layer 120 includes doped ions, at most one cavity 180 is formed inside the first material layer 120, and the concentration of the doped ions gradually decreases in an upward direction perpendicular to the surface of the substrate 101.
Referring to fig. 5, the first material layer 120 includes a plurality of material sub-layers, and the doping ion concentration of each material sub-layer is different and decreases in sequence upward along a direction perpendicular to the upper surface of the substrate 101.
In an embodiment, the first material layer 120 is formed in the contact window 170 by using the method of epitaxial growth described in the previous embodiment, and the concentration of the dopant ions is changed following the change of the relative concentration of the second precursor with respect to the first precursor.
If it is required that the portion of the first material layer 120 higher than the stacked structure (132a and 132b) does not contain dopant ions, when the relative concentration of the second precursor with respect to the first precursor is equal to 0, the concentration of dopant ions of the subsequently formed first material layer 120 is gradually reduced to 0 based on the concentration of dopant ions of the currently formed first material layer 120.
In one embodiment, the first material layer 120 includes a material sub-layer with a dopant ion concentration of 0, and a lowermost surface of the material sub-layer is located below an upper surface of the stacked structure (132a and 132 b). The material sub-layer is obtained based on epitaxial growth of the previous layer, and therefore, in the case where the doping ion of the previous layer is not 0, the doping ion of the material sub-layer is gradually reduced to 0 on the basis of the concentration of the doping ion of the previous layer.
In one embodiment, the stacked structures (132a and 132b) include bit line structures. The bit line structure is as described in the previous embodiments.
When the void 180 is present, the void 180 passes through at least two regions of the first material layer 120, and the two regions have different dopant ion concentrations.
When the void 180 is present, the top of the void 180 is lower than the upper surface of the stacked structure (132a and 132 b).
Fig. 6 is a schematic cross-sectional view of a semiconductor memory device according to an embodiment of the present application.
In an embodiment, after the first material layer 120 is prepared, the first material layer 120 is further etched back to make the top surface of the first material layer 120 lower than the top surface of the stacked structures (132a and 132b) for performing a subsequent process of preparing a semiconductor memory device.
The above-mentioned embodiments are only examples of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent flow transformations made by the contents of the specification and the drawings, such as the combination of technical features between the embodiments and the direct or indirect application to other related technical fields, are also included in the scope of the present application.
Claims (5)
1. A semiconductor memory device, comprising:
the surface of the substrate is provided with a contact window, and the contact window exposes the inside of the substrate;
the plurality of stacked structures are formed on the surface of the substrate, and the contact window is positioned between two adjacent stacked structures;
the first material layer is distributed between two adjacent stacked structures and is positioned in the contact window, doped ions are contained in the first material layer, and at most one hollow hole is formed in the first material layer;
the first material layer comprises a plurality of material sublayers, and the doped ion concentration of each material sublayer is different and is sequentially reduced upwards along the direction vertical to the upper surface of the substrate.
2. The semiconductor memory device according to claim 1, wherein the first material layer comprises a material sub-layer having a dopant ion concentration of 0, and a lowermost surface of the material sub-layer is located below an upper surface of the stacked structure.
3. The semiconductor memory device according to claim 1, wherein the stacked structure comprises a bit line structure.
4. The semiconductor memory device according to claim 1, wherein when the void exists, the void passes through at least two regions in the first material layer, and the two regions have different dopant ion concentrations.
5. The semiconductor memory device according to claim 1, wherein when the void exists, a top of the void is lower than an upper surface of the stacked structure.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202123011922.7U CN216624280U (en) | 2021-12-01 | 2021-12-01 | Semiconductor memory device with a plurality of memory cells |
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| CN202123011922.7U CN216624280U (en) | 2021-12-01 | 2021-12-01 | Semiconductor memory device with a plurality of memory cells |
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