CN113097287A - IGBT chip terminal structure and manufacturing method thereof - Google Patents
IGBT chip terminal structure and manufacturing method thereof Download PDFInfo
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- CN113097287A CN113097287A CN201911333532.6A CN201911333532A CN113097287A CN 113097287 A CN113097287 A CN 113097287A CN 201911333532 A CN201911333532 A CN 201911333532A CN 113097287 A CN113097287 A CN 113097287A
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- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
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Abstract
The invention provides an IGBT chip terminal structure and a manufacturing method thereof.A P-type field limiting ring (2) and a ballast resistor area (3) are formed inside the front surface of an N-type substrate (1); forming an oxide layer on the front surfaces of the P-type field limiting ring (2) and the ballast resistor area (3); a front metal layer (9) is formed on the front surface of the oxide layer, a back structure is formed on the back surface of the N-type substrate (1), and the ballast resistor area (3) can avoid the occurrence of hole current concentration and dynamic latch-up, so that the burning failure of the IGBT chip in the turn-off process is avoided, meanwhile, the doping concentration of a P-type collector area (11) on the back surface corresponding to the terminal structure is reduced, the hole current density in the turn-off process of the IGBT chip is reduced, and the dynamic latch-up resistance and the overcurrent turn-off capability of the IGBT chip are further improved. The invention also reduces the electric field intensity by reducing the etching angle of the field plate step, and improves the reliability of the IGBT chip in a blocking state.
Description
Technical Field
The invention relates to the technical field of power electronic devices, in particular to an IGBT chip terminal structure and a manufacturing method of the IGBT chip terminal structure.
Background
Insulated Gate Bipolar Transistors (IGBTs) integrate the excellent characteristics of Bipolar Junction Transistors (BJTs) and Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), have the characteristics of high input impedance, voltage drive control, low drive power, low on-state voltage drop, low switching loss, and adaptability to high-frequency applications, and are currently the most ideal power Semiconductor devices, especially having a broad application prospect in the field of high-voltage and high-power applications.
In the manufacturing process of the IGBT chip, the pn junction is formed by processing through ion implantation and diffusion processes, the pn junction is approximate to a parallel plane junction in the middle area of the IGBT chip, and cylindrical or spherical pn junctions can be formed in the corner areas of the IGBT chip. The breakdown voltage of the cylindrical surface or spherical surface pn junction is only 10 to 25 percent of that of the parallel plane junction according to the calculation of the Poisson equation of the electric field. For this reason, the IGBT chip must have a termination structure (i.e., a junction termination region), which reduces the electric field strength at the cylindrical junction or the spherical junction at the edge of the IGBT chip and increases the withstand voltage level of the pn junction. The terminal structure adopted by the IGBT chip at present mainly adopts a field plate technology, an electric field concentration effect exists at the step of the field plate, hot electron injection is brought under a high-voltage state, and the reliability of the IGBT chip is low. On the other hand, when the IGBT chip is in an on state, a large number of holes are injected from the collector side, and in the turn-off process of the IGBT chip, the holes need to be extracted through the cells in the active region on the front side.
Disclosure of Invention
In order to overcome the defects that the IGBT chip in the prior art is low in reliability and easy to burn out and lose efficacy in the turn-off process, the invention provides an IGBT chip terminal structure and an IGBT chip terminal structure manufacturing method, wherein a P-type field limiting ring (2) and a ballast resistor area (3) are formed inside the front surface of an N-type substrate (1); forming an oxide layer on the front surfaces of the P-type field limiting ring (2) and the ballast resistor area (3); a front metal layer (9) is formed on the front surface of the oxide layer, a back structure is formed on the back surface of the N-type substrate (1), and the ballast resistor area (3) can avoid the occurrence of hole current concentration and dynamic latch-up, so that the burning-out failure of the IGBT chip in the turn-off process is avoided.
In order to achieve the purpose of the invention, the invention adopts the following technical scheme:
in one aspect, the invention provides a method for manufacturing an IGBT chip terminal structure, including:
forming a P-type field limiting ring (2) and a ballast resistor region (3) in the front of an N-type substrate (1);
forming an oxide layer on the front surfaces of the P-type field limiting ring (2) and the ballast resistor area (3);
and forming a front metal layer (9) on the front surface of the oxide layer, and forming a back structure on the back surface of the N-type substrate (1).
The P-type field limiting ring (2) and the ballast resistor region (3) are formed on the front surface of the N-type substrate (1), and the method comprises the following steps:
a photoresist mask process is adopted in the front side of the N-type substrate (1), and a P-type field limiting ring (2) and a ballast resistor region (3) are formed in an ion implantation and high-temperature junction pushing mode;
and stripping and cleaning the photoresist on the front surface of the N-type substrate (1).
The P-type doping concentrations of the P-type field limiting ring (2) and the ballast resistor region (3) are both 5e17cm-3～5e18cm-3；
The dosage of the ion implantation is 1e14cm-2～1e15cm-2；
The width of the ballast resistor area (3) is 100-300 um.
The oxide layer is formed on the front surfaces of the P-type field limiting ring (2) and the ballast resistor area (3), and the oxide layer comprises:
sequentially adopting thermal oxidation, Ar ion implantation, photoetching, etching and glue stripping processes to form a primary field oxide layer (4) on the front surface of the N-type substrate (1);
forming a grid oxide layer (5) on the front surfaces of the N-type substrate (1) and the P-type field limiting ring (2) by adopting a thermal oxidation process;
sequentially adopting deposition, photoetching, etching and glue stripping processes to form a polysilicon layer (6) on the front surfaces of the primary field oxide layer (4) and the grid oxide layer (5);
sequentially adopting deposition, photoetching, etching and glue stripping processes to form an isolation oxide layer (7) on the front surfaces of the P-type field limiting ring (2), the ballast resistor region (3), the primary field oxide layer (4) and the polycrystalline silicon layer (6);
and sequentially forming a secondary field oxide layer (8) on the front surface of the isolation oxide layer (7) by adopting deposition, Ar ion implantation, photoetching, etching and stripping processes.
The boundary of the field oxide layer (4) is in a slope shape, the slope angle is 15-25 degrees, and the thickness of the field oxide layer is 1.0-1.5 um.
The thickness of the grid oxide layer (5) is 0.09 um-0.15 um;
the thickness of the polycrystalline silicon layer (6) is 0.5 um-1.0 um;
the thickness of the isolation oxide layer (7) is 1.0-2.0 um;
the boundary of the secondary field oxide layer (8) is in a slope shape, the slope angle is 15-45 degrees, and the thickness of the secondary field oxide layer is 2.5-5.0 um;
the thickness of the front metal layer (9) is 2.0 um-4.5 um.
The method for forming the back structure on the back of the N-type substrate (1) comprises the following steps:
forming an N-type buffer layer (12), a P-type collector region (11) and a back metal layer (10) on the back of the N-type substrate (1) in sequence;
the P-type doping concentration of the P-type collector region (11) is 1e17cm-3～3e17cm-3。
In another aspect, the present invention provides an IGBT chip termination structure, including:
the P-type field limiting ring (2) and the ballast resistor region (3) are arranged on the front surface of the N-type substrate (1); and the oxide layer is arranged on the front surfaces of the P-type field limiting ring (2) and the ballast resistor area (3); a front metal layer (9) arranged on the front surface of the oxide layer; and the back structure is arranged on the back surface of the N-type substrate (1).
The oxide layer comprises a primary field oxide layer (4), a grid oxide layer (5), an isolation oxide layer (7) and a secondary field oxide layer (8) which are sequentially positioned on the front surface of the N-type substrate (1);
and a polycrystalline silicon layer (6) is arranged between the grid oxide layer (5) and the isolation oxide layer (7).
The P-type doping concentrations of the P-type field limiting ring (2) and the ballast resistor region (3) are both 5e17cm-3～5e18cm-3；
The dosage of the ion implantation is 1e14cm-2～1e15cm-2；
The width of the ballast resistor area (3) is 100-300 um;
the boundary of the primary field oxide layer (4) and the secondary field oxide layer (8) is in a slope shape;
the slope angle of the field oxide layer (4) is 15-25 degrees, and the thickness of the field oxide layer is 1.0-1.5 um;
the slope angle of the secondary field oxide layer (8) is 15-45 degrees, and the thickness of the secondary field oxide layer is 2.5-5.0 um;
the thickness of the grid oxide layer (5) is 0.09 um-0.15 um;
the thickness of the polycrystalline silicon layer (6) is 0.5 um-1.0 um;
the thickness of the isolation oxide layer (7) is 1.0-2.0 um;
the thickness of the front metal layer (9) is 2.0 um-4.5 um.
Compared with the closest prior art, the technical scheme provided by the invention has the following beneficial effects:
in the manufacturing method of the IGBT chip terminal structure, a P-type field limiting ring (2) and a ballast resistor area (3) are formed inside the front surface of an N-type substrate (1); forming an oxide layer on the front surfaces of the P-type field limiting ring (2) and the ballast resistor area (3); a front metal layer (9) is formed on the front surface of the oxide layer, a back structure is formed on the back surface of the N-type substrate (1), and the ballast resistor area (3) can avoid the occurrence of hole current concentration and dynamic latch-up, so that the burning failure of an IGBT chip in the turn-off process is avoided;
the boundary of the primary field oxide layer (4) is in a slope shape, the slope angle is 15-25 degrees, the electric field intensity of the oxide layer at the corresponding position of the step is reduced by reducing the thickness of the primary field oxide layer (4), so that the electric field peak of the IGBT chip in the blocking state is reduced, the peak electric field can be reduced by about 15 percent in the blocking state, and the reliability of the IGBT chip in the blocking state is improved;
the width of the ballast resistor region is 100-300 mu m, and the doping concentration of the P-type collector region (11) corresponding to the terminal structure is 1e17cm-3～3e17cm-3Compared with the doping concentration of a back P-type collector region corresponding to the active region, the doping concentration of the back P-type collector region is reduced by more than 90%, minority carriers gathered in a drift region below a terminal structure in the turn-on process of the IGBT chip are further reduced, the number of carriers required to be extracted in the turn-off process is reduced, the hole current density of edge cells of the active region in the turn-off process is reduced, and the dynamic latch-up resistance and overcurrent turn-off capability of the IGBT chip are improved.
Drawings
FIG. 1 is a flow chart of a method for fabricating an IGBT chip termination structure according to an embodiment of the present invention;
FIG. 2 is a terminal structure diagram of an IGBT chip in the embodiment of the invention;
FIG. 3 is a diagram illustrating electric field strength at different angles of a field oxide layer according to an embodiment of the present invention;
in the figure, 1, an N-type substrate, 2, a P-type field limiting ring, 3, a ballast resistor region, 4, a primary field oxide layer, 5, a grid oxide layer, 6, a polycrystalline silicon layer, 7, an isolation oxide layer, 8, a secondary field oxide layer, 9, a front metal layer, 10, a back metal layer, 11, a P-type collector region corresponding to a terminal structure, 12, an N-type buffer layer, 13 and a P-type collector region corresponding to an active region.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
Example 1
s101: forming a P-type field limiting ring 2 and a ballast resistor region 3 in the front of an N-type substrate 1;
s102: forming an oxide layer on the front surfaces of the P-type field limiting ring 2 and the ballast resistor area 3;
s103: a front metal layer 9 is formed on the front surface of the oxide layer, and a back structure is formed on the back surface of the N-type substrate 1.
In S101, a P-type field limiting ring 2 and a ballast resistor region 3 are formed on a front surface of an N-type substrate 1, including:
forming a P-type field limiting ring 2 and a ballast resistor region 3 in the front of an N-type substrate 1 by adopting a photoresist mask process and adopting an ion implantation and high-temperature push-knot mode;
and stripping and cleaning the photoresist on the front surface of the N-type substrate 1.
The P-type doping concentrations of the P-type field limiting ring 2 and the ballast resistor region 3 are both 5e17cm-3～5e18cm-3；
The dose of the ion implantation is 1e14cm-2～1e15cm-2；
The width of the ballast resistor area 3 is 100-300 um.
The N-type substrate 1 is an N-type silicon wafer, and the resistivity and the thickness of the N-type silicon wafer can be determined according to the voltage grade of the IGBT chip.
In S102, forming an oxide layer on the front surfaces of the P-type field limiting ring 2 and the ballast resistor region 3, including:
sequentially adopting thermal oxidation, Ar ion implantation, photoetching, etching and glue stripping processes to form a primary field oxide layer 4 on the front surface of the N-type substrate 1, wherein the primary field oxide layer 4 is a second step;
forming a gate oxide layer 5 on the front surfaces of the N-type substrate 1 and the P-type field limiting ring 2 by adopting a thermal oxidation process, wherein the gate oxide layer 5 is a first step;
forming a polysilicon layer 6 on the front surfaces of the primary field oxide layer 4 and the grid oxide layer 5 by adopting deposition, photoetching, etching and glue stripping processes in sequence;
sequentially adopting deposition, photoetching, etching and glue stripping processes to form an isolation oxide layer 7 on the front surfaces of the P-type field limiting ring 2, the ballast resistor region 3, the primary field oxide layer 4 and the polycrystalline silicon layer 6, wherein the isolation oxide layer 7 is a third step;
sequentially adopting deposition, Ar ion implantation, photoetching, etching and glue stripping processes to form a secondary field oxide layer 8 on the front surface of the isolation oxide layer 7, wherein the secondary field oxide layer 8 is a fourth step;
the boundary of the field oxide layer 4 is in a slope shape, and a specific slope angle is realized through Ar ion implantation, wherein the slope angle is 15-25 degrees, and the thickness of the slope angle is 1.0-1.5 um. The schematic diagram of the electric field strength of the primary field oxide layer at different angles is shown in fig. 3, and it can be seen that the electric field corresponding to 15 ° is the weakest, the electric field corresponding to 45 ° is the strongest, and the electric field is proportional to the slope angle.
The thickness of the grid oxide layer 5 is 0.09 um-0.15 um;
the thickness of the polysilicon layer 6 is 0.5um to 1.0 um;
the thickness of the isolation oxide layer 7 is 1.0 um-2.0 um;
the boundary of the secondary field oxide layer 8 is in a slope shape, and a specific slope angle is realized through Ar ion implantation, wherein the slope angle is 15-45 degrees, and the thickness of the slope angle is 2.5-5.0 um;
the thickness of the front metal layer 9 is 2.0 um-4.5 um.
In S103, forming a back structure on the back surface of the N-type substrate 1, including:
forming an N-type buffer layer 12, a P-type collector region 11 and a back metal layer 10 on the back of an N-type substrate 1 in sequence;
the P-type doping concentration of the P-type collector region 11 is 1e17cm-3～3e17cm-3。
The terminal structure finally obtained by the method for manufacturing the terminal structure of the IGBT chip provided in embodiment 1 of the present invention is shown in fig. 2.
Example 2
a P-type field limiting ring 2 and a ballast resistor region 3 which are arranged on the front surface of the N-type substrate 1;
the oxide layer is arranged on the front surfaces of the P-type field limiting ring 2 and the ballast resistor area 3;
a front metal layer 9 disposed on the front surface of the oxide layer;
and the back structure is arranged on the back surface of the N-type substrate 1.
The oxide layer comprises a primary field oxide layer 4, a grid oxide layer 5, an isolation oxide layer 7 and a secondary field oxide layer 8 which are sequentially positioned on the front surface of the N-type substrate 1;
a polysilicon layer 6 is provided between the gate oxide layer 5 and the isolation oxide layer 7.
The P-type doping concentrations of the P-type field limiting ring 2 and the ballast resistor region 3 are both 5e17cm-3～5e18cm-3；
The dose of the ion implantation is 1e14cm-2～1e15cm-2；
The width of the ballast resistor area 3 is 100-300 um;
the boundaries of the primary field oxide layer 4 and the secondary field oxide layer 8 are both in a slope shape;
the slope angle of the field oxide layer 4 is 15-25 degrees, and the thickness is 1.0-1.5 um;
the slope angle of the secondary field oxide layer 8 is 15-45 degrees, and the thickness thereof is 2.5-5.0 um;
the thickness of the grid oxide layer 5 is 0.09 um-0.15 um;
the thickness of the polysilicon layer 6 is 0.5um to 1.0 um;
the thickness of the isolation oxide layer 7 is 1.0 um-2.0 um;
the thickness of the front metal layer 9 is 2.0 um-4.5 um.
According to the requirement of blocking voltage, the terminal structure can be a combination of one or more terminal structures, and when a plurality of terminal structures are adopted, the terminal structure is arranged in a mode that the distance between the P-type field limiting rings 2 is gradually increased.
As shown in fig. 3, in addition to the N-type substrate 1 and the terminal structures on the front surface of the N-type substrate 1, embodiment 2 of the present invention further includes an active region located on the front surface of the N-type substrate 1, where the active region includes a P-type doped well region of the active region, the back surface structure of the IGBT chip includes a back surface structure corresponding to the active region in addition to the back surface structure corresponding to the terminal structure, and the back surface structure corresponding to the active region includes an N-type buffer layer 12, a P-type collector region 13 corresponding to the active region, and a back surface metal layer 10.
For convenience of description, each part of the above-described apparatus is separately described as being functionally divided into various modules or units. Of course, the functionality of the various modules or units may be implemented in the same one or more pieces of software or hardware when implementing the present application.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Finally, it should be noted that: the above embodiments are only intended to illustrate the technical solution of the present invention and not to limit the same, and a person of ordinary skill in the art can make modifications or equivalents to the specific embodiments of the present invention with reference to the above embodiments, and such modifications or equivalents without departing from the spirit and scope of the present invention are within the scope of the claims of the present invention as set forth in the claims.
Claims (10)
1. A manufacturing method of an IGBT chip terminal structure is characterized by comprising the following steps:
forming a P-type field limiting ring (2) and a ballast resistor region (3) in the front of an N-type substrate (1);
forming an oxide layer on the front surfaces of the P-type field limiting ring (2) and the ballast resistor area (3);
and forming a front metal layer (9) on the front surface of the oxide layer, and forming a back structure on the back surface of the N-type substrate (1).
2. The manufacturing method of the IGBT chip termination structure of claim 1, wherein the forming of the P-type field limiting ring (2) and the ballast resistor region (3) on the front surface of the N-type substrate (1) comprises:
a photoresist mask process is adopted in the front side of the N-type substrate (1), and a P-type field limiting ring (2) and a ballast resistor region (3) are formed in an ion implantation and high-temperature junction pushing mode;
and stripping and cleaning the photoresist on the front surface of the N-type substrate (1).
3. The manufacturing method of the IGBT chip terminal structure of claim 2, wherein the P-type doping concentrations of the P-type field limiting ring (2) and the ballast resistor region (3) are both 5e17cm-3～5e18cm-3；
The dosage of the ion implantation is 1e14cm-2～1e15cm-2；
The width of the ballast resistor area (3) is 100-300 um.
4. The method for manufacturing the terminal structure of the IGBT chip according to claim 1, wherein the forming of the oxide layer on the front surfaces of the P-type field limiting ring (2) and the ballast resistor region (3) comprises:
sequentially adopting thermal oxidation, Ar ion implantation, photoetching, etching and glue stripping processes to form a primary field oxide layer (4) on the front surface of the N-type substrate (1);
forming a grid oxide layer (5) on the front surfaces of the N-type substrate (1) and the P-type field limiting ring (2) by adopting a thermal oxidation process;
sequentially adopting deposition, photoetching, etching and glue stripping processes to form a polysilicon layer (6) on the front surfaces of the primary field oxide layer (4) and the grid oxide layer (5);
sequentially adopting deposition, photoetching, etching and glue stripping processes to form an isolation oxide layer (7) on the front surfaces of the P-type field limiting ring (2), the ballast resistor region (3), the primary field oxide layer (4) and the polycrystalline silicon layer (6);
and sequentially forming a secondary field oxide layer (8) on the front surface of the isolation oxide layer (7) by adopting deposition, Ar ion implantation, photoetching, etching and stripping processes.
5. The manufacturing method of the IGBT chip terminal structure according to claim 4, characterized in that the boundary of the primary field oxide layer (4) is in a slope shape, the slope angle is 15-25 degrees, and the thickness is 1.0-1.5 um.
6. The manufacturing method of the IGBT chip terminal structure according to claim 3, wherein the thickness of the gate oxide layer (5) is 0.09 um-0.15 um;
the thickness of the polycrystalline silicon layer (6) is 0.5 um-1.0 um;
the thickness of the isolation oxide layer (7) is 1.0-2.0 um;
the boundary of the secondary field oxide layer (8) is in a slope shape, the slope angle is 15-45 degrees, and the thickness of the secondary field oxide layer is 2.5-5.0 um;
the thickness of the front metal layer (9) is 2.0 um-4.5 um.
7. The method for manufacturing the terminal structure of the IGBT chip according to claim 1, wherein the forming of the back structure on the back surface of the N-type substrate (1) comprises:
forming an N-type buffer layer (12), a P-type collector region (11) and a back metal layer (10) on the back of the N-type substrate (1) in sequence;
the P-type doping concentration of the P-type collector region (11) is 1e17cm-3～3e17cm-3。
8. An IGBT chip termination structure, comprising:
the P-type field limiting ring (2) and the ballast resistor region (3) are arranged on the front surface of the N-type substrate (1); and the oxide layer is arranged on the front surfaces of the P-type field limiting ring (2) and the ballast resistor area (3); a front metal layer (9) arranged on the front surface of the oxide layer; and the back structure is arranged on the back surface of the N-type substrate (1).
9. The IGBT chip termination structure according to claim 8, wherein the oxide layer comprises a primary field oxide layer (4), a gate oxide layer (5), an isolation oxide layer (7) and a secondary field oxide layer (8) in this order on the front side of the N-type substrate (1);
and a polycrystalline silicon layer (6) is arranged between the grid oxide layer (5) and the isolation oxide layer (7).
10. The IGBT chip termination structure of claim 9, wherein the P-type doping concentrations of the P-type field limiting ring (2) and the ballast resistor region (3) are both 5e17cm-3～5e18cm-3；
The dosage of the ion implantation is 1e14cm-2～1e15cm-2；
The width of the ballast resistor area (3) is 100-300 um;
the boundary of the primary field oxide layer (4) and the secondary field oxide layer (8) is in a slope shape;
the slope angle of the field oxide layer (4) is 15-25 degrees, and the thickness of the field oxide layer is 1.0-1.5 um;
the slope angle of the secondary field oxide layer (8) is 15-45 degrees, and the thickness of the secondary field oxide layer is 2.5-5.0 um;
the thickness of the grid oxide layer (5) is 0.09 um-0.15 um;
the thickness of the polycrystalline silicon layer (6) is 0.5 um-1.0 um;
the thickness of the isolation oxide layer (7) is 1.0-2.0 um;
the thickness of the front metal layer (9) is 2.0 um-4.5 um.
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Cited By (2)
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| CN114883185A (en) * | 2022-07-01 | 2022-08-09 | 深圳芯能半导体技术有限公司 | Manufacturing method of IGBT chip with high current density |
| WO2023071237A1 (en) * | 2021-10-30 | 2023-05-04 | 华为数字能源技术有限公司 | Insulated gate bipolar transistor and manufacturing method therefor, and electronic device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2023071237A1 (en) * | 2021-10-30 | 2023-05-04 | 华为数字能源技术有限公司 | Insulated gate bipolar transistor and manufacturing method therefor, and electronic device |
| CN114883185A (en) * | 2022-07-01 | 2022-08-09 | 深圳芯能半导体技术有限公司 | Manufacturing method of IGBT chip with high current density |
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