CN114883185A - Manufacturing method of IGBT chip with high current density - Google Patents
Manufacturing method of IGBT chip with high current density Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 88
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 claims abstract description 55
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 51
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000001312 dry etching Methods 0.000 claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 10
- 238000002513 implantation Methods 0.000 claims description 48
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 43
- 150000002500 ions Chemical class 0.000 claims description 38
- 238000005530 etching Methods 0.000 claims description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 25
- 229920005591 polysilicon Polymers 0.000 claims description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 19
- 238000000151 deposition Methods 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 239000013078 crystal Substances 0.000 claims description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 15
- 239000012535 impurity Substances 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- 230000007797 corrosion Effects 0.000 claims description 12
- 238000005260 corrosion Methods 0.000 claims description 12
- 239000000377 silicon dioxide Substances 0.000 claims description 11
- 235000012239 silicon dioxide Nutrition 0.000 claims description 11
- 238000002161 passivation Methods 0.000 claims description 10
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 9
- 230000001413 cellular effect Effects 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 238000011049 filling Methods 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 6
- 238000003466 welding Methods 0.000 claims description 6
- -1 BF2 ions Chemical class 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 238000000227 grinding Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 abstract description 9
- 230000007547 defect Effects 0.000 abstract description 6
- 238000010849 ion bombardment Methods 0.000 abstract description 6
- 230000000694 effects Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 238000002360 preparation method Methods 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052950 sphalerite Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
Abstract
The invention provides a method for manufacturing an IGBT chip with high current density, which takes a monocrystalline silicon wafer as a substrate, adopts photoresist to carry out pattern definition and photoresist removal, utilizes potassium hydroxide or tetramethylammonium hydroxide solution to corrode an N-type monocrystalline silicon substrate to a preset depth to form a grid groove, avoids the surface damage of the channel caused by ion bombardment in the traditional dry etching process, forms a smoother channel surface, ensures that the channel of the IGBT chip has fewer surface defects and higher carrier mobility, and improves the current density of the IGBT chip. Meanwhile, the gate trench is formed by adopting a KOH or TMAH wet etching process, so that the step of sacrificing an oxide layer before the subsequent gate oxide process can be omitted, and the manufacturing period and the process cost of the chip are reduced.
Description
Technical Field
The invention relates to the technical field of IGBT chip preparation, in particular to a manufacturing method of an IGBT chip with high current density.
Background
The IGBT is a high-power semiconductor discrete device, combines the advantages of high switching frequency of an MOS chip, easy control, high-current processing capacity of a BJT chip and the like, and has wide application in the fields of industrial frequency conversion, consumer electronics, rail transit, new energy, aerospace and the like. In a traditional planar gate IGBT cellular region structure, MOS channel current flows in the horizontal direction, a PN junction depletion layer between Pwell and an N-drift region expands, a JFET effect is formed at a corner where the current turns from the horizontal direction to the vertical direction, and the resistance on a conduction path is increased. On the other hand, the channel is in the horizontal direction, so that the surface area of the chip is occupied, and the further reduction of the size of the cellular region is limited.
With the mature application of the gate trench etching technology in the IGBT chip, the channel current is successfully changed from the horizontal direction to the vertical direction, the JFET effect of a planar gate cellular area is effectively eliminated, the size of the cellular area is reduced, the channel density is not limited by the surface area of the chip any more, the density of the cellular area is improved, and the current density of the chip is greatly improved.
However, in the process of forming the IGBT gate trench by dry etching, the surface of the channel is damaged by the ion bombardment effect in the etching process, and even if a sacrificial oxide layer process is subsequently used and the damaged layer on the surface is etched away, the surface defect of the channel cannot be completely repaired, which may result in an enhanced surface scattering effect of carriers in the channel and a reduced channel mobility.
Disclosure of Invention
In view of the above, the invention provides a method for manufacturing an IGBT chip with high current density, which replaces the conventional dry etching process, avoids the damage effect of ion bombardment in the dry etching process on the surface of a channel, effectively reduces the surface defect density of the channel, and improves the channel mobility of carriers, thereby improving the current density of the chip.
In order to achieve the above object, the present invention provides a method for manufacturing an IGBT chip with high current density, including:
s1, selecting an N-type monocrystalline silicon wafer as a substrate, growing a field oxide layer by adopting a wet oxygen process, selectively corroding the field oxide layer on a field limiting ring region of the terminal region, and carrying out P-type impurity propulsion after ion implantation to obtain a P-type silicon region of the terminal region;
s2, selectively corroding the field oxide layer in a cell area, depositing and growing a silicon dioxide stress buffer layer and a silicon nitride mask layer based on a low-pressure chemical vapor deposition method, photoetching and dry etching the silicon dioxide stress buffer layer and the silicon nitride hard mask layer, corroding the N-type monocrystalline silicon substrate to a preset depth by using potassium hydroxide or tetramethylammonium hydroxide solution to form a gate trench, removing the silicon nitride mask layer, and growing a gate oxide layer;
s3, filling polycrystalline silicon in the grid groove in the cell area based on a low-pressure chemical vapor deposition method, etching the polycrystalline silicon in a dry method to form a grid electrode, forming a terminal area polycrystalline silicon area above the oxide layer in the terminal area based on the low-pressure chemical vapor deposition method, etching the polycrystalline silicon in the dry method to form a bus bar wiring, turning the N-type monocrystalline silicon wafer to the back side, and removing the polycrystalline silicon on the back side;
s4, turning the N-type monocrystalline silicon wafer back to the front side, injecting P-type ions into the cell region, removing the photoresist, pushing impurities to form a P-well region, oxidizing the polycrystalline silicon region of the cell region and the polycrystalline silicon region of the terminal region simultaneously, and etching the oxide layer of the cell region to reduce the preset thickness;
s5, sequentially injecting P + ions and As + ions into the cellular region to form an N-type silicon region;
s6, depositing insulating dielectric layers in the cell area and the terminal area, etching contact holes, and sequentially injecting BF2 ions and B + ions into the contact holes;
s7, performing front metallization and passivation layer deposition in the cell area and the terminal area;
and S8, overturning the N-type monocrystalline silicon wafer to the back, and thinning and metalizing the back in the cell area and the terminal area.
Preferably, in step S1, the N-type monocrystalline silicon surface is a (100) crystal plane or a (110) crystal plane, and the resistivity of the N-type monocrystalline silicon wafer is 30 to 90 Ω · m; the process temperature of the wet oxygen process is 800-1050 ℃, and the thickness of the prepared field oxide layer is 1-3 mu m; the implanted ions are B + ions, the implantation dosage is 8E13-5E14, and the implantation energy is 80-140 keV; the temperature of the P-type impurity propulsion is 1000-1200 ℃, and the time is 300-600 min.
Preferably, in the step S2, the thicknesses of the silicon dioxide stress buffer layer and the silicon nitride mask layer are 3000-; the concentration of the potassium hydroxide or tetramethyl ammonium hydroxide solution is 20-50 wt%, the process temperature is 70-90 ℃, the corrosion rate is 0.5-3 mu m/min, the preset depth of corrosion is 4-7 mu m, and the uniformity in a chip of the corrosion process is controlled within 5%.
Preferably, in the step S3, the filling thickness of the cell region polysilicon region is 8000-.
Preferably, in step S4, the P-type ions implanted in the cell region are B + ions, the implantation dose is 1E13-1E14, and the implantation energy is 80-140 keV; the temperature is 1000-1150 ℃ when the impurity propulsion is carried out, and the time is 90-150 min.
Preferably, in step S5, the implantation dose of the implanted P + ions is 1E15-8E15, the implantation energy is 40-80keV, and the implantation dose of the implanted As + ions is 1E15-8E15, the implantation energy is 40-100 keV.
Preferably, in step S6, the total thickness of the insulating dielectric layer is 9000-12000A, the implantation dose of BF2 ions is 5E14-8E15, the implantation energy is 20-80keV, the implantation dose of B + ions is 1E14-5E15, and the implantation energy is 40-100 keV.
Preferably, the step S7 specifically includes:
depositing a metal layer on the front surface, wherein the thickness of the metal layer is 4-8 mu m, and performing dry etching patterning to form a grid electrode pressure welding point and a source electrode pressure welding point;
and depositing a silicon nitride layer based on a PECVD process, wherein the thickness is 9000-15000A, and etching and patterning to form a terminal region passivation layer.
Preferably, the step S8 specifically includes:
grinding the back of the wafer, removing silicon oxide, and reducing the thickness to 60-150 um;
implanting P + ions into the buffer layer on the back surface, wherein the implantation dosage is 2E11-1E13, and the implantation energy is 200-900 keV;
b + ions are implanted into the back surface, wherein the implantation dosage is 1E12-8E13, and the implantation energy is 20-50 keV;
the furnace tube annealing activates impurities at the temperature of 300 ℃ and 500 ℃ for 20-80 min;
and depositing a metal layer on the back surface, wherein the thickness of the metal layer is 1-2 um.
Preferably, the shape of the gate trench in the cell region is any one of a triangle, a trapezoid, a combined figure formed by a rectangle and a triangle, and a combined figure formed by a rectangle and a trapezoid.
The beneficial effects of adopting the above embodiment are:
according to the invention, the monocrystalline silicon wafer is used as the substrate, the photoresist is adopted for pattern definition and photoresist removal, the N-type monocrystalline silicon substrate is corroded to the preset depth by using the potassium hydroxide or tetramethylammonium hydroxide solution to form the grid groove, the surface damage of the channel caused by ion bombardment in the traditional dry etching process is avoided, the surface of the formed channel is smooth, the channel of the IGBT chip has fewer surface defects and higher carrier mobility, and the current density of the IGBT chip is improved. Meanwhile, the gate trench is formed by adopting a KOH or TMAH wet etching process, so that the conventional step of sacrificing an oxide layer before the subsequent gate oxide process can be omitted, and the manufacturing period and the process cost of the chip are reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 to 8 are schematic structural changes of an IGBT chip when the method for manufacturing an IGBT chip with high current density according to the present invention is performed;
FIG. 9 is a schematic diagram illustrating an embodiment of forming a gate trench by wet etching in the method for manufacturing a high current density IGBT chip according to the present invention;
fig. 10 is a schematic structural diagram of an embodiment of a method for manufacturing an IGBT chip with high current density according to the present invention;
fig. 11 is a schematic structural diagram of another embodiment of the method for manufacturing the high-current-density IGBT chip according to the present invention;
fig. 12 is a schematic structural diagram of yet another embodiment of the method for manufacturing the high-current-density IGBT chip according to the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In an embodiment of the present invention, the present invention provides a method for manufacturing an IGBT chip with high current density, including the following steps:
s1, selecting an N-type monocrystalline silicon wafer as a substrate 101/201, growing a field oxide layer 102 by adopting a wet oxygen process, selectively corroding the field oxide layer 202 on a field limiting ring region of the terminal region, and carrying out P-type impurity propulsion after ion implantation to obtain a P-type silicon region 203 of the terminal region;
in a specific embodiment, referring to fig. 1, fig. 1 shows a cell region and a termination region after being prepared in step S1, the cell region includes a cell region single-crystal silicon substrate 101 and a cell region oxide layer 102 (typically silicon dioxide), and the termination region includes a termination region single-crystal silicon substrate 201, a cell region oxide layer 202 and a termination region P-type silicon region 203.
In a specific embodiment, the surface of the N-type monocrystalline silicon wafer is a (100) crystal plane or a (110) crystal plane, and the resistivity of the N-type monocrystalline silicon wafer is 30-90 Ω · m; the process temperature of the wet oxygen process is 800-1050 ℃, and the thickness of the prepared field oxide layer is 1-3 mu m; the implanted ions are B + ions, the implantation dosage is 8E13-5E14, and the implantation energy is 80-140 keV; the temperature of the P-type impurity propulsion is 1000-1200 ℃, and the time is 300-600 min.
S2, selectively corroding the field oxide layer 102 in the cell area, depositing and growing a silicon dioxide stress buffer layer and a silicon nitride mask layer based on a low-pressure chemical vapor deposition method, photoetching and dry etching the silicon dioxide stress buffer layer and the silicon nitride hard mask layer, corroding the N-type monocrystalline silicon substrate to a preset depth by using potassium hydroxide or tetramethylammonium hydroxide solution to form a gate trench, removing the silicon nitride mask layer, and growing a gate oxide layer;
in a specific embodiment, referring to fig. 2, fig. 2 shows a cell region and a termination region after being prepared in step S2, the cell region includes a cell region single-crystal silicon substrate 101 and a cell region oxide layer 102 (typically silicon dioxide), the termination region includes a termination region single-crystal silicon substrate 201, a cell region oxide layer 202 and a termination region P-type silicon region 203, and the cell region single-crystal silicon substrate 101 and the cell region oxide layer 102 include gate trenches (i.e., two "V" type trenches in fig. 2).
In a specific embodiment, the thicknesses of the silicon dioxide stress buffer layer and the silicon nitride mask layer are 3000-5000A and 1000-3000A respectively; the concentration of the potassium hydroxide or tetramethyl ammonium hydroxide solution is 20-50 wt%, the process temperature is 70-90 ℃, the corrosion rate is 0.5-3 mu m/min, the preset depth of corrosion is 4-7 mu m, and the uniformity in a chip of the corrosion process is controlled within 5%.
It should be noted that the surface of the N-type single crystal silicon wafer correspondingly adopted by the gate trench formed in fig. 2 is in the (100) crystal plane direction, the formation of the gate trench is realized by a potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH) wet etching process, channel surface damage caused by ion bombardment in the conventional dry etching process is avoided, the formed channel surface is relatively smooth, the channel of the IGBT chip has fewer surface defects and higher carrier mobility, and the current density of the IGBT chip is improved. Meanwhile, the gate trench is formed by adopting a KOH or TMAH wet etching process, so that the step of sacrificing an oxide layer before the subsequent gate oxide process can be omitted, and the manufacturing period and the process cost of the chip are reduced.
To illustrate that different gate trenches are formed when different crystal plane directions of the surface of the N-type single crystal silicon wafer are selected, please specifically refer to fig. 9, where fig. 9 is a schematic diagram of an embodiment of forming a gate trench by wet etching in the method for manufacturing an IGBT chip with high current density according to the present invention.
It should be noted that fig. 9 is a principle of forming a gate trench with a (100) crystal plane direction on the surface of an N-type single crystal silicon wafer, when wet etching (KOH or TMAH) is performed, the trench depth will gradually become deeper along with continuous etching, when the bottoms of the two sides of the gate trench are connected (i.e., a preset depth, which is the maximum depth) to form a triangular gate trench (with an included angle of a fixed angle α) (i.e., as shown in fig. 2), when the bottoms of the two sides of the gate trench are not connected (i.e., the preset depth, which may be determined according to process requirements), the etching is stopped, and a trapezoidal gate trench will be formed (as shown in fig. 10); when the surface of the N-type single crystal silicon wafer is in the (110) crystal plane direction, and the wet etching is performed by using KOH or TMAH, a combined pattern composed of a rectangle and a triangle is formed after the bottoms of the two sides of the gate trench are connected (i.e., a preset depth is a maximum depth), so as to obtain the gate trench (i.e., as shown in fig. 11), and the etching is stopped when the bottoms of the two sides of the gate trench are not connected (i.e., the preset depth is determined according to the process requirements), so as to form a combined pattern composed of a rectangle and a trapezoid, so as to obtain the gate trench (as shown in fig. 10).
Further, taking the monocrystalline silicon with the (100) crystal face as an example, KOH or TMAH has anisotropic characteristics for etching of a silicon substrate, and KOH or TMAH solution with the same concentration and under the same process conditions is used for monocrystalline silicon with a sphalerite lattice structure in the following (111): (100): (110) the etching rate ratio on the crystal plane is 1:400:600, and it can be considered that the etching does not basically etch on the (111) crystal plane, so that the etching plane stops on the (111) crystal plane and forms an included angle of 54.74 degrees (i.e. an angle α) with the surface of the wafer. When the corrosion window is narrow, the bevel edges of the two (111) crystal faces are downward converged at one point to form a V shape, and the corrosion is stopped at the moment, so that the corrosion of KOH or TMAH has a self-stopping effect in the depth direction, and the uniformity in the wafer and between batches of the process and the CPK processing capability of the process can be greatly improved. Similarly, when the window of the etching process is wide, the etching process needs to be controlled in time, and the process is stopped at an appropriate time, so as to finally form the inverted trapezoidal groove cross section.
Furthermore, when the window of the etching process is narrow, for example, the monocrystalline silicon with (110) crystal plane, a tapered trench cross section is finally formed, the trench depth is determined by the width of the window, and the self-stop effect is achieved in the depth direction, so that the in-wafer and batch-to-batch uniformity of the etching process can be greatly improved, and the CPK level of the process is improved. Furthermore, when the window of the etching process is wide, the etching process needs to be controlled in time, and the process is stopped at a proper time, so as to finally form the cross section of the trench combining the rectangular shape and the inverted trapezoid shape.
It is understood that the shape of the gate trench in the cell region is any one of a triangle, a trapezoid, a combination of a rectangle and a triangle, and a combination of a rectangle and a trapezoid.
S3, filling polycrystalline silicon in the grid groove in the cell area based on a low-pressure chemical vapor deposition method to form a grid electrode (namely the cell area polycrystalline silicon area 104), performing dry etching on the polycrystalline silicon to form a terminal area polycrystalline silicon area 204 above the oxide layer in the terminal area based on the low-pressure chemical vapor deposition method, performing dry etching on the polycrystalline silicon to form a bus bar routing, turning the N-type monocrystalline silicon wafer to the back side, and removing the back side polycrystalline silicon;
in a specific embodiment, referring to fig. 3, fig. 3 is a cell region and a terminal region after being prepared in step S3, the cell region includes a cell region single-crystal silicon substrate 101, a cell region oxide layer 102 and a cell region polysilicon region 104, the terminal region includes a terminal region single-crystal silicon substrate 201, a cell region oxide layer 202, a terminal region P-type silicon region 203 and a terminal region polysilicon region 204, and the cell region polysilicon region 104 fills the gate trench.
In a specific embodiment, the filling thickness of the polysilicon region in the cell region is 8000-.
S4, turning the N-type monocrystalline silicon wafer back to the front side, injecting P-type ions into the cell region, removing the photoresist, pushing impurities to form a P well region 103, oxidizing the polycrystalline silicon region of the cell region and the polycrystalline silicon region of the terminal region simultaneously, and etching the oxide layer of the cell region to reduce the preset thickness;
in a specific embodiment, referring to fig. 4, fig. 4 shows the cell region and the termination region after the preparation in step S4, the cell region includes the cell region single-crystal silicon substrate 101, the cell region oxide layer 102, the cell region P-well region 103 and the cell region polysilicon region 104, and the termination region includes the termination region single-crystal silicon substrate 201, the cell region oxide layer 202, the termination region P-type silicon region 203, the termination region polysilicon region 204 and the termination region polysilicon oxide region 302.
In a specific embodiment, the P-type ions implanted in the cell region are B + ions, the implantation dose is 1E13-1E14, and the implantation energy is 80-140 keV; the temperature is 1000-1150 ℃ when the impurity propulsion is carried out, and the time is 90-150 min.
S5, injecting P + ions and As + ions in sequence into the cellular region to form an N-type silicon region 105, and annealing in a furnace tube after removing the photoresist at the temperature of 800-;
in a specific embodiment, referring to fig. 5, fig. 5 shows the cell region and the termination region after the preparation in step S5, the cell region includes the cell region single-crystal silicon substrate 101, the cell region oxide layer 102, the cell region P-well region 103, the cell region polysilicon region 104 and the N-type silicon region 105, and the termination region includes the termination region single-crystal silicon substrate 201, the cell region oxide layer 202, the termination region P-type silicon region 203, the termination region polysilicon region 204 and the termination region polysilicon oxide region 302.
In a specific embodiment, the implantation dose of the implanted P + ions is 1E15-8E15, the implantation energy is 40-80keV, and the implantation dose of the implanted As + ions is 1E15-8E15, and the implantation energy is 40-100 keV.
S6, performing insulating dielectric layer deposition in both the cell area and the terminal area to form a USG + BPSG double-layer structure (namely the cell area insulating dielectric layer 106), wherein the total thickness is 9000-;
in a specific embodiment, referring to fig. 6, fig. 6 shows the cell region and the terminal region after being prepared in step S6, the cell region includes a cell region single-crystal silicon substrate 101, a cell region oxide layer 102, a cell region P-well region 103, a cell region polysilicon region 104, an N-type silicon region 105, a cell region insulating dielectric layer 106 and a cell region contact hole 107, and the terminal region includes a terminal region single-crystal silicon substrate 201, a cell region oxide layer 202, a terminal region P-type silicon region 203, a terminal region polysilicon region 204, a terminal region polysilicon oxide region 302, a terminal region insulating dielectric layer 206 and a terminal region contact hole 207.
In a specific embodiment, the implantation dose of the BF2 ions is 5E14-8E15, the implantation energy is 20-80keV, the implantation dose of the B + ions is 1E14-5E15, and the implantation energy is 40-100 keV.
S7, performing front metallization and passivation layer deposition in the cell area and the terminal area;
in a specific embodiment, referring to fig. 7, fig. 7 is a cell region and a terminal region after being prepared in step S7, the cell region includes a cell region single-crystal silicon substrate 101, a cell region oxide layer 102, a cell region P-well region 103, a cell region polysilicon region 104, an N-type silicon region 105, a cell region insulating dielectric layer 106, a cell region contact hole 107, a cell region metal layer 108, and a cell region passivation layer 109, and the terminal region includes a terminal region single-crystal silicon substrate 201, a cell region oxide layer 202, a terminal region P-type silicon region 203, a terminal region polysilicon region 204, a terminal region polysilicon oxide region 302, a terminal region insulating dielectric layer 206, a terminal region contact hole 207, a terminal region metal layer 208, and a terminal region passivation layer 209.
In a specific embodiment, step S7 specifically includes:
depositing a metal layer on the front surface, wherein the thickness of the metal layer is 4-8 mu m, and performing dry etching patterning to form a grid electrode pressure welding point and a source electrode pressure welding point;
and depositing a silicon nitride layer based on a PECVD process, wherein the thickness is 9000-15000A, and etching and patterning to form a terminal region passivation layer.
And S8, overturning the N-type monocrystalline silicon wafer to the back, and thinning and metalizing the back in the cell area and the terminal area.
In a specific embodiment, referring to fig. 8, fig. 8 is a cell region and a terminal region after being prepared in step S8, the cell region includes a cell region single-crystal silicon substrate 101, a cell region oxide layer 102, a cell region P-well region 103, a cell region polysilicon region 104, an N-type silicon region 105, a cell region insulating dielectric layer 106, a cell region contact hole 107, a cell region metal layer 108, and a cell region passivation layer 109, and the terminal region includes a terminal region single-crystal silicon substrate 201, a cell region oxide layer 202, a terminal region P-type silicon region 203, a terminal region polysilicon region 204, a terminal region polysilicon oxide region 302, a terminal region insulating dielectric layer 206, a terminal region contact hole 207, a terminal region metal layer 208, and a terminal region passivation layer 209.
In a specific embodiment, the step S8 specifically includes:
grinding the back of the wafer, removing silicon oxide, and reducing the thickness to 60-150 um;
implanting P + ions into the buffer layer on the back surface, wherein the implantation dosage is 2E11-1E13, and the implantation energy is 200-900 keV;
b + ions are implanted into the back surface, wherein the implantation dosage is 1E12-8E13, and the implantation energy is 20-50 keV;
the furnace tube annealing activates impurities at the temperature of 300 ℃ and 500 ℃ for 20-80 min;
and depositing a metal layer on the back surface, wherein the thickness of the metal layer is 1-2 um.
It should be noted that fig. 7 and fig. 8 are a front side structure and a back side structure of a wafer, respectively, and the difference is that the bottom of the front side structure of the wafer is an oxide layer, and the bottom of the back side structure of the wafer is a metal layer.
In summary, the invention uses the monocrystalline silicon wafer as the substrate, uses the photoresist to perform pattern definition and remove the photoresist, and uses the potassium hydroxide or tetramethylammonium hydroxide solution to corrode the N-type monocrystalline silicon substrate to the preset depth to form the gate trench, thereby avoiding the surface damage of the trench caused by ion bombardment in the traditional dry etching process, and the formed trench surface is smoother, so that the trench of the IGBT chip has fewer surface defects and higher carrier mobility, and the current density of the IGBT chip is improved. Meanwhile, the gate trench is formed by adopting a KOH or TMAH wet etching process, so that the conventional step of sacrificing an oxide layer before the subsequent gate oxide process can be omitted, and the manufacturing period and the process cost of the chip are reduced.
The method for manufacturing the high-current-density IGBT chip provided by the present invention is described in detail above, and the principle and the implementation of the present invention are explained in the present document by applying specific examples, and the description of the above examples is only used to help understanding the method and the core idea of the present invention; meanwhile, for those skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A manufacturing method of an IGBT chip with high current density is characterized by comprising the following steps:
s1, selecting an N-type monocrystalline silicon wafer as a substrate, growing a field oxide layer by adopting a wet oxygen process, selectively corroding the field oxide layer on a field limiting ring region of the terminal region, and carrying out P-type impurity propulsion after ion implantation to obtain a P-type silicon region of the terminal region;
s2, selectively corroding the field oxide layer in a cell area, depositing and growing a silicon dioxide stress buffer layer and a silicon nitride mask layer based on a low-pressure chemical vapor deposition method, photoetching and dry etching the silicon dioxide stress buffer layer and the silicon nitride hard mask layer, corroding the N-type monocrystalline silicon substrate to a preset depth by using potassium hydroxide or tetramethylammonium hydroxide solution to form a gate trench, removing the silicon nitride mask layer, and growing a gate oxide layer;
s3, filling polycrystalline silicon in the grid groove in the cell area based on a low-pressure chemical vapor deposition method, etching the polycrystalline silicon in a dry method to form a grid electrode, forming a terminal area polycrystalline silicon area above the oxide layer in the terminal area based on the low-pressure chemical vapor deposition method, etching the polycrystalline silicon in the dry method to form a bus bar wiring, turning the N-type monocrystalline silicon wafer to the back side, and removing the polycrystalline silicon on the back side;
s4, turning the N-type monocrystalline silicon wafer back to the front side, injecting P-type ions into the cell region, removing the photoresist, pushing impurities to form a P-well region, oxidizing the polycrystalline silicon region of the cell region and the polycrystalline silicon region of the terminal region simultaneously, and etching the oxide layer of the cell region to reduce the preset thickness;
s5, sequentially injecting P + ions and As + ions into the cellular region to form an N-type silicon region;
s6, depositing insulating dielectric layers in the cell area and the terminal area, etching contact holes, and sequentially injecting BF2 ions and B + ions into the contact holes;
s7, performing front metallization and passivation layer deposition in the cell area and the terminal area;
and S8, overturning the N-type monocrystalline silicon wafer to the back, and thinning and metalizing the back in the cell area and the terminal area.
2. The method according to claim 1, wherein in step S1, the N-type single crystal silicon surface is a (100) crystal plane or a (110) crystal plane, and the resistivity of the N-type single crystal silicon wafer is 30-90 Ω -m; the process temperature of the wet oxygen process is 800-1050 ℃, and the thickness of the prepared field oxide layer is 1-3 mu m; the implanted ions are B + ions, the implantation dosage is 8E13-5E14, and the implantation energy is 80-140 keV; the temperature of the P-type impurity propulsion is 1000-1200 ℃, and the time is 300-600 min.
3. The method as claimed in claim 1, wherein in step S2, the thicknesses of the silicon dioxide stress buffer layer and the silicon nitride mask layer are 3000-5000A and 1000-3000A, respectively; the concentration of the potassium hydroxide or tetramethyl ammonium hydroxide solution is 20-50 wt%, the process temperature is 70-90 ℃, the corrosion rate is 0.5-3 mu m/min, the preset depth of corrosion is 4-7 mu m, and the uniformity in a chip of the corrosion process is controlled within 5%.
4. The method as claimed in claim 1, wherein in step S3, the filling thickness of the polysilicon region in the cell region is 8000-10000A.
5. The method of claim 1, wherein in step S4, the P-type ions implanted into the cell region are B + ions, the implantation dose is 1E13-1E14, and the implantation energy is 80-140 keV; the temperature is 1000-1150 ℃ when the impurity propulsion is carried out, and the time is 90-150 min.
6. The method of claim 1, wherein in step S5, the implantation dose of the implanted P + ions is 1E15-8E15, the implantation energy is 40-80keV, and the implantation dose of the implanted As + ions is 1E15-8E15, the implantation energy is 40-100 keV.
7. The method as claimed in claim 1, wherein in step S6, the total thickness of the insulating dielectric layer is 9000-12000A, the implantation dose of BF2 ions is 5E14-8E15, the implantation energy is 20-80keV, the implantation dose of B + ions is 1E14-5E15, and the implantation energy is 40-100 keV.
8. The method for manufacturing the high-current-density IGBT chip according to claim 1, wherein the step S7 specifically includes:
depositing a metal layer on the front surface, wherein the thickness of the metal layer is 4-8 mu m, and performing dry etching patterning to form a grid electrode pressure welding point and a source electrode pressure welding point;
and depositing a silicon nitride layer based on a PECVD process, wherein the thickness is 9000-15000A, and etching and patterning to form a terminal region passivation layer.
9. The method for manufacturing the high-current-density IGBT chip according to claim 1, wherein the step S8 specifically includes:
grinding the back of the wafer, removing silicon oxide, and reducing the thickness to 60-150 um;
implanting P + ions into the buffer layer on the back surface, wherein the implantation dosage is 2E11-1E13, and the implantation energy is 200-900 keV;
b + ions are implanted into the back surface, wherein the implantation dosage is 1E12-8E13, and the implantation energy is 20-50 keV;
the furnace tube annealing activates impurities at the temperature of 300 ℃ and 500 ℃ for 20-80 min;
and depositing a metal layer on the back surface, wherein the thickness of the metal layer is 1-2 um.
10. The method of claim 1, wherein the shape of the gate trench in the cell region is any one of a triangle, a trapezoid, a combination of a rectangle and a triangle, and a combination of a rectangle and a trapezoid.
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