CN109860302A - A kind of power metal-oxide-semiconductor field effect transistor and its manufacture of new model - Google Patents
A kind of power metal-oxide-semiconductor field effect transistor and its manufacture of new model Download PDFInfo
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Abstract
The present invention provides a kind of power metal-oxide-semiconductor field effect transistor of new model and its manufactures, it include: one substrate+extension, one oxide layer, one polysilicon (Poly-Si) layer, one silicon nitride layer, one first doped region, one second doped region, one injects the first P+ doped region for the first time, one injects the 2nd P+ doped region for the first time, one dielectric substance layer (ILD), one second of the first P+ doped region of injection, one second of the 2nd P+ doped region of injection, one the first metal layer, one second metal layer, the present invention uses three-layer light cover, effectively reduce technique manufacturing process, but device property is not had an impact, the reactive ion etch (RIE) that part utilizes semiconductor equipment need to only be filled, its selection ratio adjusted for different etching materials, derivative clearance wall Spacer structure Just it can complete that the light shield number of plies is allowed to reduce, its device is made to keep original superperformance.
Description
Technical field
The present invention relates to electronic component, semiconductor, integrated circuit more particularly to a kind of power metal-oxides of new model
The manufacture of object semiconductcor field effect transistor.
Background technique
Power metal-oxide-semiconductor field effect transistor Power MOSFET (Metal-Oxide-Semiconductor
It Field-Effect-Transistor) is a kind of field-effect transistor for being widely used in various circuit and Switching Power Supply, it is main excellent
The problem of gesture is that its device is majority carrier characteristic, and there is no minority carrier storage charges, therefore have higher work frequency
Rate；The operating rate of another MOSEFT is fast, even if with the presence of high voltage and high current in switching circuit, the loss of conducting is still non-
It is often low.
MOSFET can easily divide into groove (trench) structure and plane (planar) structure, this research at present
For planar structure.Using silicon as the MOSFET of background, competitor is many in the market at present, so cost control is often leading
It is crucial.The processing procedure of planar structure need to use five layers of light shield or more at present, and respectively AA (isolates active region and termination environment), Poly
(position of Si-Poly before fixed), Source (defines the region to be adulterated N+), and (Al metal to be connected Contact after definition
Position), Metal (opens its Al metal separation), causes production cost that can not decline, this is also current production power metal oxygen
One of the predicament that the company of compound semiconductcor field effect transistor is faced.
Summary of the invention
The technical problem to be solved by the present invention is for the cost of plant produced flow and time (cycle time),
Five light shield techniques are all selected, and the present invention uses the manufacturing process of new three light shield, cost reduces many, while
The output time is saved, this will improve plant produced efficiency in turn and bring more gross profits, and the present invention provides a kind of new
The power metal-oxide-semiconductor field effect transistor of form and its manufacture solve the above problems.
The technical solution adopted by the present invention to solve the technical problems is: a kind of power metal-oxide of new model is partly led
Body field-effect transistor, comprising:
One substrate+extension has a drain metal layer in the lower surface of the substrate；
One oxide layer is growth in the extension, which is characterized in that the oxide layer has more a gate pole oxidation layer and one
Oxide layer, the gate pole oxidation layer are thinner than field oxide；
One polysilicon (Poly-Si) layer is growth in the oxide layer；
One silicon nitride layer is growth on the polysilicon layer, and the silicon nitride layer is formed by deposition twice, respectively first
Road silicon nitride layer and second silicon nitride layer；
One first doped region is located at below the outer Yanzhong and the gate pole oxidation layer, and first doped region is with ion cloth
Value and heating diffusion way form the first P- doped region and the first N+ doped region；
One second doped region also is located at below the outer Yanzhong and the gate pole oxidation layer, and second doped region is with ion
Implantation and heating diffusion way form the 2nd P- doped region and the 2nd N+ doped region；
One injects the first P+ doped region for the first time, is located among the first P- doped region and the first N+ doped region, the first P
+ doped region is formed with the ion implantation using high-energy, high dose；
One injects the 2nd P+ doped region for the first time, is located among the 2nd P- doped region and the 2nd N+ doped region, the 2nd P
+ doped region is formed with the ion implantation using high-energy, high dose；
One dielectric substance layer (ILD) is located at the silicon nitride layer side；
One second of the first P+ doped region of injection is located among the first P- doped region and the first N+ doped region；
One second of the 2nd P+ doped region of injection is located among the 2nd P- doped region and the 2nd N+ doped region；
One the first metal layer is growth the gate pole oxidation layer on one side, in second of the first P+ doped region of injection and the
On the 2nd P+ doped region of secondary injection, which is characterized in that the first metal layer connection second of injection the first P+ doping
Area and second of the 2nd P+ doped region of injection, to form source metal；
One second metal layer is growth on described field oxide one side, in the polysilicon (Poly-Si) layer and the field oxidation
Layer top, to form gate metal layer.
Further, after the dielectric substance layer (ILD) has deposited, its surface is carried out using chemical grinding equipment (CMP)
Planarization process.
Further, which need to be spaced one from the first doped region and the N+ of the second doped region mixes
Miscellaneous area, and contacted simultaneously with the P+ doped region of its N+ doped region and lower section, the source metal contact zone is mixed with described first
The contact surface that miscellaneous area and second doped region are formed is in same level.
Further, the interface of gate metal layer contact zone is higher than source metal contact zone interface.
The present invention also provides a kind of manufacture of the power metal-oxide-semiconductor field effect transistor of new model, packets
Include following steps:
1) oxide layer is grown in the extension；
2) field oxide and the gate pole oxidation layer are etched with first of light shield (AA), that is, has separated out the active of device
Area and termination environment；
3) polysilicon (Poly-Si) layer and first of silicon nitride layer are deposited；
4) polysilicon (Poly-Si) the floor block that will be stayed and first of silicon nitride layer area are etched with second light shield (Poly)
Block, wherein the purpose of reserved silicon nitride layer block is in order to which overetch of the second silicon nitride layer later when etching is pre-
It stays, avoids polysilicon (Poly-Si) layer in the active region exposed；
5) first doped region and second doped region are formed with ion implantation and heating diffusion way；
6) second nitride deposition；
7) use the ion implantation of high-energy, high dose in first doped region and second doped region while difference shape
The first P+ doped region and the first time are injected at the first time and injects the 2nd P+ doped region, wherein first time injection the
The formation that one P+ doped region and the first time inject the 2nd P+ doped region can effectively improve the avalanche capacity of its device；
8) deposition of the dielectric layer (ILD)；
9) its surface is planarized to the dielectric layer (ILD) using chemical grinding equipment (CMP)；
10) it is used to etch the dielectric layer (ILD) using reactive ion etch equipment (RIE), to form the dielectric layer
(ILD) residual (Spacer), while also etching away a little silicon nitride on the termination environment polysilicon (Poly-Si)；
11) etching of silicon nitride until termination environment polysilicon (Poly-Si) expose, and it is etched after in the active region polysilicon
(Poly-Si) still there is extra silicon nitride on；
12) epitaxial silicon in active region is etched, it is separated with the first N+ doped region in first doped region, and
It is separated with the 2nd N+ doped region in second doped region；
13) the 2nd P+ doped region of second of the first P+ doped region of injection and second of injection is formed, this described second
The first P+ doped region of secondary injection and the 2nd P+ doped region of second injection generate so as to the first metal layer later
There is preferable nurse contact difficult to understand；
14) deposition of metal (Al) layer；
15) third road light shield (Metal) forms the source level metal layer and the lock grade metal layer.
Further, wherein step 7 can be omitted suddenly.
Further, when progress step 13 is rapid, the polysilicon (Poly-Si) of the termination environment is not possible to determine when the sample has been completely etched.
The invention has the advantages that with general power metal-oxide-semiconductor field effect transistor making technology mode
Technique manufacturing process is effectively reduced using three-layer light cover compared to photograph, but device property is not had an impact, more fills part utilization
The reactive ion etch (RIE) of semiconductor equipment, for the different selection ratios that are adjusted of etching materials and derivative
Clearance wall Spacer structure also all allows the light shield number of plies to reduce, its device is made to keep original superperformance.
Detailed description of the invention
Above content of the invention will be described in detail with other purposes, characteristic and advantage in conjunction with following attached drawing,
Middle same components are indicated with the same symbol.
Fig. 1 grows oxide layer in extension, etches field oxide and gate pole oxidation layer step with first of light shield (AA).
Fig. 2 deposit polycrystalline silicon (Poly-Si) layer and first of silicon nitride layer, and with second light shield (Poly) etch by
The polysilicon to be stayed (Poly-Si) layer block and first of silicon nitride layer block step.
Fig. 3 forms the first doped region and the second doped region step with ion implantation and heating diffusion way.
Fig. 4 second nitride deposition, and form the first P+ doped region of injection and the 2nd P+ of injection for the first time for the first time and mix
Miscellaneous area's step.
The deposition step of Fig. 5 dielectric layer (ILD).
Fig. 6 is used to etch dielectric layer (ILD) using reactive ion etch equipment (RIE), to form dielectric layer (ILD)
Residual (Spacer), while also etching away a little silicon nitride step on termination environment polysilicon (Poly-Si).
Fig. 7 etching of silicon nitride exposes until termination environment polysilicon (Poly-Si).
Injection forms second of the oneth P+ doped region and second of the 2nd P+ doped region step after Fig. 8 etches epitaxial silicon.
The deposition of Fig. 9 metal (Al) layer, third road light shield (Metal) form source level metal layer and lock grade metal layer step.
Specific embodiment
The embodiment of the present invention is described below in detail, the example of embodiment is shown in the accompanying drawings, wherein identical from beginning to end
Or similar label indicates same or similar component or component with the same or similar functions.It is retouched below with reference to attached drawing
The embodiment stated is exemplary, and for explaining only the invention, and is not considered as limiting the invention.
In the description of the present invention, it is to be understood that, term " above ", " lower surface, " side ", " instruction such as horizontal plane
Orientation or positional relationship be based on the orientation or positional relationship shown in the drawings, be merely for convenience of description the present invention and simplification retouch
It states, rather than the device of indication or suggestion meaning must have a particular orientation, be constructed and operated in a specific orientation, therefore not
It can be interpreted as limitation of the present invention.
In addition, term " first ", " second " etc. are used for description purposes only, it is not understood to indicate or imply relatively important
Property.In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, term " first ", " second " answer
It is interpreted broadly, for example, it may be third, is also possible to the 4th or the 5th；It can be the 6th, be also possible to 7th etc., it is right
For those skilled in the art, the concrete meaning of above-mentioned term in the present invention can be understood with concrete condition.
As shown in figure 9, being the power metal-oxide-semiconductor field effect transistor of new model of the present invention, comprising:
One substrate+extension has a drain metal layer in the lower surface of the substrate；
Preferably, the substrate+extension is all N-type；
One oxide layer is growth in the extension, which is characterized in that the oxide layer has more a gate pole oxidation layer and one
Oxide layer, the gate pole oxidation layer are thinner than field oxide；
One polysilicon (Poly-Si) layer is growth in the oxide layer；
One silicon nitride layer is growth on the polysilicon layer, and the silicon nitride layer is formed by deposition twice, respectively first
Road silicon nitride layer and second silicon nitride layer；
One first doped region is located at below the outer Yanzhong and the gate pole oxidation layer, and first doped region is with ion cloth
Value and heating diffusion way form the first P- doped region and the first N+ doped region；
One second doped region also is located at below the outer Yanzhong and the gate pole oxidation layer, and second doped region is with ion
Implantation and heating diffusion way form the 2nd P- doped region and the 2nd N+ doped region；
One injects the first P+ doped region for the first time, is located among the first P- doped region and the first N+ doped region, the first P
+ doped region is formed with the ion implantation using high-energy, high dose；
One injects the 2nd P+ doped region for the first time, is located among the 2nd P- doped region and the 2nd N+ doped region, the 2nd P
+ doped region is formed with the ion implantation using high-energy, high dose；
One dielectric substance layer (ILD) is located at the silicon nitride layer side；
One second of the first P+ doped region of injection is located among the first P- doped region and the first N+ doped region；
One second of the 2nd P+ doped region of injection is located among the 2nd P- doped region and the 2nd N+ doped region；
One the first metal layer is growth the gate pole oxidation layer on one side, in second of the first P+ doped region of injection and the
On the 2nd P+ doped region of secondary injection, which is characterized in that the first metal layer connection second of injection the first P+ doping
Area and second of the 2nd P+ doped region of injection, to form source metal；
One second metal layer is growth on described field oxide one side, in the polysilicon (Poly-Si) layer and the field oxidation
Layer top, to form gate metal layer.
Further, after the dielectric substance layer (ILD) has deposited, its surface is carried out using chemical grinding equipment (CMP)
Planarization process.
Further, which need to be spaced one from the first doped region and the N+ of the second doped region mixes
Miscellaneous area, and contacted simultaneously with the P+ doped region of its N+ doped region and lower section, the source metal contact zone is mixed with described first
The contact surface that miscellaneous area and second doped region are formed is in same level.
Further, the interface of gate metal layer contact zone is higher than source metal contact zone interface.
To fully understand the purpose of the present invention, feature and effect, now by following specific embodiments, and cooperate attached drawing,
The present invention is described in detail, is illustrated as after.
Fig. 1 to Fig. 9 shows a kind of manufacture of the power metal-oxide-semiconductor field effect transistor of new model of the present invention
Schematic diagram, wherein will be explained using N channel-type as example.
Firstly, providing one substrate+extension, oxide layer is grown in extension, in the present embodiment, the substrate can be highly concentrated
The N+ type silicon substrate of doping is spent, and the oxide layer can be silicon dioxide layer (SiO2) and can be using a thermal oxidation process come shape
At structure is as shown in Figure 1.Wherein, surface can plate a conductive metal layer (to ask as drain contacts to the substrate below
See the drain metal layer of Fig. 9)；The substrate also can be the substrate that an other semiconductor materials are made into；The oxide layer be as
Mask layer is used；And the resistance value of the N+ type silicon substrate is preferably the resistance value with 0.002~0.004 Ω-cm, the N+ type
The resistance value of extension is preferably the resistance value with 1~50 Ω-cm.Then mask lithography processing procedure is penetrated in the oxide layer
The mode of (Mask photolithograph) forms patterned first of light shield (AA), and with first of light shield (AA)
The oxide layer is etched for etching mask, so that the field oxide and gate pole oxidation layer of different-thickness are etched, in this implementation
Gate pole oxidation layer thickness described in example is about 0.05~0.12 μm, and the field oxide thickness is about 1~2 μm.
Then as shown in Fig. 2, deposit polycrystalline silicon (Poly-Si) layer and first of silicon nitride layer, and with second light shield
(Poly) polysilicon (Poly-Si) the layer block and first of silicon nitride layer block that will be stayed are etched, as preferably described more
Crystal silicon (Poly-Si) layer with a thickness of 0.7~1.4 μm, the thickness of the silicon nitride layer is about 0.1~0.5 μm.
Then as shown in figure 3, in the present embodiment, the first time and second of ion implanting can be used to ion implantation and
Heating diffusion way forms the first doped region and for the first time to save the number and cost of mask lithography processing procedure with ion implanting
Two doped regions, the concentration of first time ion implantation process can be 3 × 1013~6 × 1015ions/cm2, energy can for 20KeV ~
300KeV makes the first P- doped region and the first N+ doped region in the injection thickness of the N+ type silicon epitaxy be respectively 2.5~5
μm and 0.2~0.6 μm, make the 2nd P- doped region and the 2nd N+ doped region the N+ type silicon epitaxy injection thickness distinguish
For 2.5~5 μm and 0.2~0.6 μm.
Wherein Fig. 4 second nitride deposition, and form the first P+ doped region of injection for the first time and for the first time the 2nd P of injection
+ doped region in deposition second silicon nitride, while being used the ion implantation shape of high-energy, high dose in the present embodiment
At the 2nd P+ doped region of first time the first P+ doped region of injection and first time injection, P+ doped region therein can effectively improve its device
The avalanche capacity of part, it is preferable that ion implantation method described in the present embodiment is 10-7Under the vacuum of Torr, using high current with
Middle current ion implanter carries out, and the ion implantation method average ion beam current is 5 ~ 10mA, and ion source life is 40 ~
50hrs, as another preparation flow of the present invention, the first time injects the first P+ doped region and for the first time the 2nd P+ of injection doping
The preparation step in area can be omitted, and such case nor affects on power metal-oxide-semiconductor field effect transistor of the present invention
Basic function, so also in protection scope of the present invention.
The wherein deposition of Fig. 5 dielectric layer (ILD), the dielectric layer (ILD) using APCVD, LPCVD or electric plating method into
Row, the preferred electrochemical deposition method of the present embodiment carry out plated film, and in 3%, deposition is warm at the thickness uniformity bottom of the dielectric layer (ILD)
Degree is 250 ~ 400 DEG C, and the electrochemical deposition rate is 20 ~ 30nm/min, and dielectric layer described in the present embodiment (ILD) is using electricity
The uniformity of film that chemical deposition method obtains is good, particle is few, Step Coverage is good, depositing temperature is low, deposition rate is high and cost pole
It is low.
Wherein Fig. 6 is used to etch dielectric layer (ILD) using reactive ion etch equipment (RIE), to form dielectric layer
(ILD) residual (Spacer), while a little silicon nitride step on termination environment polysilicon (Poly-Si) is also etched away, preferably
Ground, its technology preparation of the dielectric layer are as follows: 7 P a(low pressure of pressure removes polymer)；Power 100W；CF4 flow 50sccm；
Etch rate 150nm/min.However, technology preparation and etch rate solidify two more than oxygen with different types difference
Silicon oxide etch rate is fast, and carbon containing more silica is then slow, equation be SiO2 (Gu)+CF4 (gas)+e- → SiF4 (gas)+
CO (gas)；Preferably described polysilicon (Poly-Si) technique requires polysilicon that can carry out incorgruous etching in chlorine gas environment,
Technology preparation are as follows: pressure 13Pa(low pressure=high selectivity ratio=low-voltage)；30 W of power；S F6 flow 50sccm.But it is this
Incorgruous etching is not necessarily to, it needs more chlorine, and cost is very big, therefore is not used.Under low pressure SF6 plasma, choosing
Selecting can obtain than good isotropic etching, its selection ratio is 100: 1, equation be Si (Gu)+SF6 (gas)+O2+ e-
→ SiF4 (gas)+SO2 (gas), in plasma etching, process control parameters are in addition to radio-frequency power, air-flow, cavity pressure, also
Including temperature and electrode gap.
Wherein Fig. 7 etching of silicon nitride, the chemical characteristic of silicon nitride require it that can only carry out incorgruous etching, therefore its advantages
That removal surrounds the nitride of upper layer metal, equation be Si3N4 (Gu)+SF6 (gas)+e- → SiF4 (gas)+SF6 (gas)+
N2 (gas), it is preferable that when carrying out this step, the polysilicon (Poly-Si) of the termination environment is not possible to determine when the sample has been completely etched.
Wherein Fig. 8 forms second of the first P+ doped region of injection and second of injection the 2nd P+ doping after etching epitaxial silicon
Area's step, preferably described second of the first P+ doped region of injection and second of the 2nd P+ doped region concentration of injection can be 1 × 1014
~1 × 1016ions/cm2, energy can be 10KeV ~ 200KeV.
The wherein deposition of Fig. 9 metal (Al) layer, third road light shield (Metal) form source level metal layer and lock grade metal layer step
Suddenly, it is preferable that the deposition of metal (Al) layer uses ion beam sputtering method, and wherein Al uses 99.99% high pure metal
Target, plasma sputter line 100mA, acceleration voltage 3000V, it is preferable that metal (Al) layer with a thickness of 3~5 μm, wherein Al
Limiting current density be 1.21 × 105A/cm2。
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example
Point is included at least one embodiment or example of the invention.In the present specification, not necessarily to the schematic representation of term
Refer to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be any one
It can be combined in any suitable manner in a or multiple embodiment or examples.
Although above description is retouched with plane formula N channel power metal oxide semiconductcor field effect transistor device
It states, but the present invention may also apply to plane formula P channel power metal oxide semiconductcor field effect transistor devices, wherein only needing
P is changed to N and N is changed to P.In addition, the present disclosure applies equally to aqueduct type power metal oxide semiconductcor field effects
Transistor unit or IGBT (insulated gate bipolar tran sistor).The present invention is not limited to above description, but allows kind
Kind modification and variation, wherein different manufacturing method and ion implantation technique and cause identical as the method for apparatus of the present invention structure
, through the above description, relevant staff completely can without departing from the scope of the technological thought of the present invention', into
Row various changes and amendments.The technical scope of the present invention is not limited to the contents of the specification, it is necessary to according to
Scope of the claims determines its technical scope.
Claims (7)
1. a kind of power metal-oxide-semiconductor field effect transistor of new model characterized by comprising
One substrate+extension has a drain metal layer in the lower surface of the substrate；
One oxide layer is growth on the epitaxial wafer, which is characterized in that the oxide layer has more a gate pole oxidation layer and one
Field oxide, the gate pole oxidation layer are thinner than field oxide；
One polysilicon (Poly-Si) layer is growth in the oxide layer；
One silicon nitride layer is growth on the polysilicon layer, and the silicon nitride layer is formed by deposition twice, respectively first
Road silicon nitride layer and second silicon nitride layer；
One first doped region is located at below the outer Yanzhong and the gate pole oxidation layer, and first doped region is with ion cloth
Value and heating diffusion way form the first P- doped region and the first N+ doped region；
One second doped region also is located at below the outer Yanzhong and the gate pole oxidation layer, and second doped region is with ion
Implantation and heating diffusion way form the 2nd P- doped region and the 2nd N+ doped region；
One injects the first P+ doped region for the first time, is located among the first P- doped region and the first N+ doped region, the first P
+ doped region is formed with the ion implantation using high-energy, high dose；
One injects the 2nd P+ doped region for the first time, is located among the 2nd P- doped region and the 2nd N+ doped region, the 2nd P
+ doped region is formed with the ion implantation using high-energy, high dose；
One dielectric substance layer (ILD) is located at the silicon nitride layer side；
One second of the first P+ doped region of injection is located among the first P- doped region and the first N+ doped region；
One second of the 2nd P+ doped region of injection is located among the 2nd P- doped region and the 2nd N+ doped region；
One the first metal layer is growth the gate pole oxidation layer on one side, in second of the first P+ doped region of injection and the
On the 2nd P+ doped region of secondary injection, which is characterized in that the first metal layer connection second of injection the first P+ doping
Area and second of the 2nd P+ doped region of injection, to form source metal；
One second metal layer is growth on described field oxide one side, in the polysilicon (Poly-Si) layer and the field oxidation
Layer top, to form gate metal layer.
2. a kind of power metal-oxide-semiconductor field effect transistor of new model according to claim 1, feature exist
In after the dielectric substance layer (ILD) has deposited, using chemical grinding equipment (CMP) to its surface progress planarization process.
3. a kind of power metal-oxide-semiconductor field effect transistor of new model according to claim 1, feature exist
In, which need to be spaced one from the N+ doped region of the first doped region and the second doped region, and simultaneously with
Its N+ doped region and the contact of the P+ doped region of lower section, the source metal contact zone and first doped region and described second
The contact surface that doped region is formed is in same level.
4. a kind of power metal-oxide-semiconductor field effect transistor of new model according to claim 1, feature exist
In the interface of gate metal layer contact zone is higher than source metal contact zone interface.
5. a kind of manufacture of the power metal-oxide-semiconductor field effect transistor of new model, which is characterized in that including such as
Lower step:
1) oxide layer is grown in the substrate+extension；
2) field oxide and the gate pole oxidation layer are etched with first of light shield (AA), that is, has separated out the active of device
Area and termination environment；
3) polysilicon (Poly-Si) layer and first of silicon nitride layer are deposited；
4) polysilicon (Poly-Si) the floor block that will be stayed and first of silicon nitride layer area are etched with second light shield (Poly)
Block, wherein the purpose of reserved silicon nitride layer block is in order to which overetch of the second silicon nitride layer later when etching is pre-
It stays, avoids polysilicon (Poly-Si) layer in the active region exposed；
5) first doped region and second doped region are formed with ion implantation and heating diffusion way；
6) second nitride deposition；
7) it is respectively formed simultaneously using the ion implantation of high-energy, high dose in first doped region and second doped region
The first time injects the first P+ doped region and the first time injects the 2nd P+ doped region, wherein first time injection first
The formation that P+ doped region and the first time inject the 2nd P+ doped region can effectively improve the avalanche capacity of its device；
8) deposition of the dielectric layer (ILD)；
9) its surface is planarized to the dielectric layer (ILD) using chemical grinding equipment (CMP)；
10) it is used to etch the dielectric layer (ILD) using reactive ion etch equipment (RIE), to form the dielectric layer
(ILD) residual (Spacer), while also etching away a little silicon nitride on the termination environment polysilicon (Poly-Si)；
11) etching of silicon nitride until termination environment polysilicon (Poly-Si) expose, and it is etched after in the active region polysilicon
(Poly-Si) still there is extra silicon nitride on；
12) epitaxial silicon in active region is etched, it is separated with the first N+ doped region in first doped region, and
It is separated with the 2nd N+ doped region in second doped region；
13) the 2nd P+ doped region of second of the first P+ doped region of injection and second of injection is formed, this described second
The first P+ doped region of secondary injection and the 2nd P+ doped region of second injection generate so as to the first metal layer later
There is preferable nurse contact difficult to understand；
14) deposition of metal (Al) layer；
15) third road light shield (Metal) forms the source level metal layer and the lock grade metal layer.
6. a kind of manufacturer of the power metal-oxide-semiconductor field effect transistor of new model according to claim 5
Formula, which is characterized in that wherein step 7 can be omitted suddenly.
7. a kind of manufacturer of the power metal-oxide-semiconductor field effect transistor of new model according to claim 5
Formula, which is characterized in that when progress step 13 is rapid, the polysilicon (Poly-Si) of the termination environment is not possible to determine when the sample has been completely etched.
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| CN111933700A (en) * | 2020-09-29 | 2020-11-13 | 中芯集成电路制造(绍兴)有限公司 | Power semiconductor device and method for manufacturing the same |
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| US5960275A (en) * | 1996-10-28 | 1999-09-28 | Magemos Corporation | Power MOSFET fabrication process to achieve enhanced ruggedness, cost savings, and product reliability |
| US20040251516A1 (en) * | 2003-06-11 | 2004-12-16 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
| CN210040206U (en) * | 2019-02-27 | 2020-02-07 | 江苏应能微电子有限公司 | Novel form of power metal oxide semiconductor field effect transistor |
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2019
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|---|---|---|---|---|
| US5960275A (en) * | 1996-10-28 | 1999-09-28 | Magemos Corporation | Power MOSFET fabrication process to achieve enhanced ruggedness, cost savings, and product reliability |
| US20040251516A1 (en) * | 2003-06-11 | 2004-12-16 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
| CN210040206U (en) * | 2019-02-27 | 2020-02-07 | 江苏应能微电子有限公司 | Novel form of power metal oxide semiconductor field effect transistor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111933700A (en) * | 2020-09-29 | 2020-11-13 | 中芯集成电路制造(绍兴)有限公司 | Power semiconductor device and method for manufacturing the same |
| CN111933700B (en) * | 2020-09-29 | 2021-06-11 | 中芯集成电路制造(绍兴)有限公司 | Power semiconductor device and method for manufacturing the same |
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