CN210897288U

CN210897288U - Novel structure of trench type power metal oxide semiconductor field effect transistor

Info

Publication number: CN210897288U
Application number: CN201922440525.8U
Authority: CN
Inventors: 李振道
Original assignee: Nanjing Rongxin Microelectronic Co ltd
Current assignee: Nanjing Rongxin Microelectronic Co ltd
Priority date: 2019-12-30
Filing date: 2019-12-30
Publication date: 2020-06-30
Anticipated expiration: 2029-12-30

Abstract

The utility model provides a new structure of a trench type power metal oxide semiconductor field effect transistor, which at least comprises an N doped region or a P well region; the N doping regions and the P doping regions are arranged alternately, namely one N doping region is next to one P doping region and then next to one N doping region, and the like; n doping area or P well district are in silicon substrate epitaxial wafer the inside, the utility model provides a new structure compares with other structures, can reach the purpose of saving process flow and cost, on the other hand the utility model discloses make the product of device electric current and route resistance be difficult for being greater than the Vbe voltage of the parasitic transistor of built-in and let the triode switch on, therefore maintain the ability of original avalanche breakdown (UIS) and reduce the probability that snapback takes place easily, the utility model discloses so can accomplish the product of medium-high voltage, but not lose the ability of protection again, promote the range of application of product greatly.

Description

Novel structure of trench type power metal oxide semiconductor field effect transistor

Technical Field

The present invention relates to electronic devices, semiconductors, and integrated circuits, and more particularly to a new structure of trench power mosfet.

Background

The Power MOSFET (Metal-Oxide-semiconductor field-Effect-Transistor) can be divided into a trench structure and a planar structure, wherein the trench structure can obtain a better resistance value due to a smaller Cell size (Cell Pitch), and thus the trench MOSFET is widely applied to a voltage below 200V, and more than 200V is completed by a multi-purpose planar structure due to a lower correlation between the resistance value and the Cell size.

In recent years, due to the rapid development of technology, the over-protection function of a power mosfet (Metal-Oxide-Semiconductor Field-Effect-Transistor) is relatively important.

SUMMERY OF THE UTILITY MODEL

The present invention provides a new over-protection structure for drain and source terminals, the circuit diagram of which is shown in fig. 1, and the structure of which can also increase the avalanche breakdown (UIS) capability of the components.

The utility model provides a technical scheme that its technical problem adopted is: a new structure of trench power MOSFET comprises: a silicon substrate epitaxial wafer; a gate oxide layer grown on the etched silicon substrate epitaxial wafer; a polysilicon (Poly-Si) layer deposited within the etched trench;

comprises an N-doped region, a P-doped region or a P-well region; the P doped region is formed by ion implantation and heating diffusion; the N-doped region is formed by adopting high-energy and high-dose ion implantation value; the N-doped regions and the P-doped regions are arranged in the polysilicon (Poly-Si) layer in the trench alternately, that is, one N-doped region is next to one P-doped region and then to one N-doped region, and so on; the N-doped region or the P well region is arranged in the silicon substrate epitaxial wafer; a dielectric layer (ILD) over the silicon substrate epitaxial wafer; a source metal layer connected with the N doped region at one side of the inner periphery of the polysilicon; a gate metal layer connected to the N-doped region on the other side of the polysilicon inner periphery.

Further, the respective lengths, depths, numbers and concentrations of the N-doped region and the P-doped region are different according to the required characteristic requirements.

Furthermore, the same design manner of the GD-side clamping structure of the trench-type power mosfet can be used for both gate (gate) and source (source), the GD-side clamping structure of the trench-type power mosfet is different from other structures in which polysilicon (Poly-Si) is formed on the surface, and the GD-side clamping structure of the trench-type power mosfet is manufactured in a required polysilicon (Poly-Si) trench only by using a general trench manufacturing process, and is called a multiple-base diode.

Further, the new structure of the trench type power metal oxide semiconductor field effect transistor is prepared by the following steps:

1) completing a basic etching process on the silicon substrate epitaxial wafer and growing the gate oxide layer;

2) depositing the layer of polycrystalline silicon (Poly-Si);

3) using a first photomask (AA) and carrying out etching corresponding to the first shape;

4) performing bottom smoothing treatment on the first shape etched in the step 2, and simultaneously preparing a P doped region and a P well region in the etched polycrystalline silicon (Poly-Si);

5) etching the gate oxide block to be remained by using a second photomask (Poly), and then completing the preparation of the N doped region of the polysilicon (Poly-Si);

6) performing dielectric layer (ILD) deposition;

7) planarizing the surface of the dielectric layer (ILD) by using a chemical polishing apparatus (CMP);

8) performing a third photomask (Contact;

9) etching at the third shape location to form a void connect metal connection;

10) deposition of a metal (Al) layer;

11) performing a fourth photo-mask (Metal) to form the source Metal layer and the gate Metal layer.

Furthermore, at least one of the P doped region, the P well region and the N doped region is provided.

The beneficial effects of the utility model are that, the utility model provides a new structure compares with other structures, because of its processing procedure is as good as with general slot processing procedure, can reach the purpose of saving process flow and cost, on the other hand the utility model discloses a technique of Deep ion implantation (Deep transplantation) has been used for the product of device electric current and path resistance is difficult for being greater than the Vbe voltage of the parasitic transistor of built-in and lets the triode switch on, therefore maintains the ability of original avalanche breakdown (UIS) and reduces the probability that snapback takes place easily, the utility model discloses so can accomplish the product of well high voltage, but not miss the ability of protection again, promote the range of application of product greatly.

Drawings

The above and other objects, features and advantages of the present invention will be described in detail in conjunction with the following drawings, wherein like reference numerals denote like elements:

fig. 1 is a circuit diagram of a trench power mosfet of the present invention.

Fig. 2 is a plan view of the trench power mosfet of the present invention.

Fig. 3 is a partial cross-sectional view of the trench power mosfet of the present invention.

FIG. 4 is a circuit diagram of the present invention, which is applied to two terminals of the gate (gate) and the source (source).

FIG. 5 is a plan view of the gate and source electrodes of the present invention.

FIG. 6 is a partial cross-sectional view of the gate and source electrodes in accordance with the present invention.

FIG. 7 illustrates a basic etching process performed on a silicon substrate and a gate oxide layer grown thereon.

FIG. 8 is a schematic diagram of the polysilicon (Poly-Si) etching process after depositing the polysilicon (Poly-Si) according to the present invention.

FIG. 9 is a schematic diagram of the present invention using a photomask to complete the preparation of P-doped regions in polysilicon (Poly-Si) and P-well regions on an epitaxial wafer.

FIG. 10 is a schematic diagram of the present invention using a photomask to complete the preparation of N doped region in polysilicon (Poly-Si).

Figure 11 illustrates a schematic diagram of a deposition process for a dielectric layer ILD.

Figure 12 illustrates a schematic diagram of the formation of a void connect metal connection by etching a dielectric layer ILD according to the present invention.

Wherein: 1 is a silicon substrate epitaxial wafer; 2 is a source metal layer; 3 is a gate metal layer; 4 is a dielectric layer (ILD); 5 is a P doped region; 6 is an N doped region; 7 is a P well region; and 8 is a polysilicon (Poly-Si) layer.

Detailed Description

Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar parts or parts having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present invention, and should not be construed as limiting the present invention.

In the description of the present invention, it should be understood that the terms "upper surface", "lower surface", "side surface", "one side", "horizontal plane", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for convenience of description of the present invention and simplification of description, but do not indicate or imply that the device referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.

Furthermore, the terms "first," "second," "more than" and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "first" and "second" are to be interpreted broadly, and may be, for example, third, fourth, or fifth; the term "about" can be used to mean about six, or about seven, etc., and the specific meaning of the term in the present invention can be understood by those skilled in the art.

As shown in fig. 1-6, the new structure of the trench power mosfet of the present invention comprises: a silicon substrate epitaxial wafer; a gate oxide layer grown on the etched silicon substrate epitaxial wafer; a polysilicon (Poly-Si) layer deposited within the etched trench; comprises an N-doped region, a P-doped region or a P-well region; the P doped region is formed by ion implantation and heating diffusion; the N-doped region is formed by adopting high-energy and high-dose ion implantation value; the N-doped regions and the P-doped regions are arranged alternately in the polysilicon (Poly-Si) layer, i.e., one N-doped region is next to one P-doped region and then to one N-doped region, and so on; the N-doped region or the P well region is arranged in the silicon substrate epitaxial wafer; a dielectric layer (ILD) over the silicon substrate epitaxial wafer; a source metal layer connected with the N doped region at one side of the inner periphery of the polysilicon; a gate metal layer connected to the N-doped region at the other side of the polysilicon inner periphery; the respective lengths, depths, quantities and concentrations of the N-doped region and the P-doped region are different according to the required characteristic requirements; the GD end clamping structure of the trench type power metal oxide semiconductor field effect transistor can be used for two ends of a gate (gate) or a source (source) in the same design mode, the GD end clamping structure of the trench type power metal oxide semiconductor field effect transistor is different from that of polycrystalline silicon (Poly-Si) manufactured on the surface, and the GD end clamping structure of the trench type power metal oxide semiconductor field effect transistor is manufactured in a required polycrystalline silicon (Poly-Si) trench only by utilizing a common trench manufacturing process and is called a multiple-base diode.

The utility model relates to a structure groove formula power metal oxide semiconductor field effect transistor new construction is made through following step:

2) depositing the layer of polycrystalline silicon (Poly-Si);

6) performing dielectric layer (ILD) deposition;

8) performing a third photomask (Contact;

9) etching at the third shape location to form a void connect metal connection;

10) deposition of a metal (Al) layer;

The detailed process flow is as follows, firstly, a silicon substrate epitaxial wafer is provided, and a gate oxide layer is deposited on the silicon substrate epitaxial wafer, as shown in fig. 7. Wherein, the lower surface of the silicon substrate epitaxial wafer can be plated with a conductive metal layer to be used as a drain contact; the silicon substrate epitaxial wafer can also be a substrate made of other semiconductor materials; the gate oxide layer is used as a mask layer; the resistance of the silicon substrate epitaxial wafer is preferably 0.001-0.005 omega-cm. And then forming the first photomask (AA) on the silicon substrate epitaxial wafer in a Mask photolithography process (Mask photolithography), and etching the gate oxide layer by using the first photomask (AA) as an etching Mask, wherein the first shape is a plurality of groove-shaped shapes, the lengths, depths, numbers and concentrations of the groove-shaped shapes are different according to the required characteristic requirements, the bottoms of the groove-shaped shapes are rounded to form circular arcs through bottom rounding, the radian of the circular arcs is 60-150 degrees, the heights of the groove-shaped shapes are all 1.0-1.5 μm, and the widths of the groove-shaped shapes are about 0.18-0.25 μm.

Next, as shown in fig. 8 and 9, the polysilicon (Poly-Si) layer is deposited and etched at the same time, and the etched P-doped region in the polysilicon (Poly-Si) and the P-well region doped on the silicon substrate epitaxial wafer are etched at the same time, preferably, the polysilicon (Poly-Si) layer has a thickness that covers the plurality of trench-like shapes.

Next, as shown in FIG. 10, the gate oxide block to be left is etched using a second mask (Poly), and then the N-doped region deposition of polysilicon (Poly-Si) is completed.

In this embodiment, the ion implantation of the P-doped region, the P-well region or the N-doped region can be performed by ion implantation with a concentration of 3 × 10 to save the times and cost of the mask photolithography process, and the formation of the P-doped region, the P-well region or the N-doped region by ion implantation can be performed by ion implantation with a concentration of 3 ×¹³～6×10¹⁵iions/cm²The energy can be 20KeV to 300KeV, and the implantation thickness of the P doped region, the P well region or the N doped region on the silicon substrate epitaxial wafer can be 0.2 to 2 μm.

Next, fig. 11 illustrates the deposition of the dielectric layer (ILD), wherein HDPCVD is performed in a coating apparatus using silicon hydride and oxygen (O2) or silicon hydride, oxygen and phosphorus hydride (PH3) or silicon hydride, oxygen, phosphorus hydride and boron-containing compound to form Undoped Silicate Glass (USG) or Phosphosilicate Glass (PSG) or Borophosphosilicate Glass (BPSG ) as a material to obtain the dielectric layer (ILD), in this embodiment, the deposited dielectric layer (ILD) is USG material, and the P-doped region, P-well region or N-doped region formed by high-energy and high-dose ion implantation can effectively improve the avalanche capability of the device; preferably, the ion implantation method in this embodiment is 10^-7In Torr vacuum, high current and medium current ion implanters are used, the average ion beam current by the ion value distribution method is 5-20 mA, and the ion source life is 10-50 hrs.

Next to fig. 12, a third photo mask (Contact) is performed to etch the dielectric layer (ILD) by using a reactive ion etching equipment (RIE) to form a residue (Spacer) of the dielectric layer (ILD), preferably, the process recipe of the dielectric layer (ILD) is: pressure 7P a (low pressure to remove polymer); the power is 100W; CF4 flow 50 sccm; the etching rate was 150 nm/min. However, the process recipe and the etching rate are different from one another, the etching rate of silicon dioxide containing more solidified oxygen is fast, and the etching rate of silicon dioxide containing more carbon is slow, and the equation is SiO2 (solid) + CF4 (gas) + e- → SiF4 (gas) + CO (gas); preferably the other process recipe is: pressure 13Pa (low pressure = high selection ratio = low voltage); the power is 30W; s F6 flow rate 50 sccm. Or may be under a low pressure SF6 plasma; preferably, another process recipe is that its selection ratio is 100: 1, the equation is Si (solid) + SF6 (gas) + O2+ e- → SiF4 (gas) + SO2 (gas), and in plasma etching, the process control parameters include the rf power, gas flow, chamber pressure, temperature and electrode gap.

Wherein FIG. 6 is a deposition of a metal (Al) layer to form the source metal layer and the gate metal layer, preferably, the deposition of the metal (Al) layer is performed by an ion beam sputtering method, wherein Al is performed by using a 99.99% high-purity metal target, a sputtering ion beam current is 200mA, an acceleration voltage is 5000V, preferably, the thickness of the metal (Al) layer is 10-1000 μm, and the limiting current density of Al is 1.38 × 10⁶A/cm²Preferably, the thickness of the source metal layer is about 1 to 6 μm, and the thickness of the gate metal layer is 2 to 5 μm.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, a schematic representation of terms does not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

The present invention is not limited to the above description, but can allow various modifications and changes, wherein different manufacturing methods and ion implantation techniques lead to the same method as the device structure of the present invention, and various changes and modifications can be made by workers without departing from the technical idea of the present invention. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the scope of the claims.

Claims

1. A new structure of trench power MOSFET is disclosed, which comprises:

a silicon substrate epitaxial wafer;

a gate oxide layer grown on the etched silicon substrate epitaxial wafer;

a layer of polysilicon (Poly-Si) deposited within said etched trench;

comprises an N-doped region, a P-doped region or a P-well region;

the N-doped regions and the P-doped regions are arranged in the polysilicon (Poly-Si) layer in the trench alternately, that is, one N-doped region is next to one P-doped region and then to one N-doped region, and so on;

a dielectric layer (ILD) over the silicon substrate epitaxial wafer;

a source metal layer connected with the N doped region at one side of the inner periphery of the polysilicon;

a gate metal layer connected to the N-doped region on the other side of the polysilicon inner periphery.

2. The new trench power mosfet structure of claim 1 wherein the respective lengths, depths, quantities and concentrations of the N-doped regions and the P-doped regions are different depending on the desired characteristics.

3. The structure of claim 1, wherein the trench power MOSFET is designed for use at both gate and source ends in the same manner.