JPH0556657B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to overvoltage protection technology and technology that is particularly effective when applied to active type overvoltage protection elements, such as electrostatic discharge damage in bipolar semiconductor integrated circuit devices. This article relates to effective techniques that can be used for prevention.

[Background technology]

Generally, in a C-MOS type semiconductor integrated circuit device, in order to prevent the gate insulation of the MOS field effect transistor that constitutes the internal circuit from being destroyed by static electricity, etc. An overvoltage protection element is inserted between the circuit and the circuit.

On the other hand, in bipolar semiconductor integrated circuit devices, the active elements that make up the internal circuit are current-driven elements, so they are generally resistant to high-voltage surges such as static electricity, and therefore the need for overvoltage protection elements is low. It was.

However, as the degree of integration of bipolar semiconductor integrated circuit devices has increased recently and the minimum dimensions of the devices have become smaller, it has become necessary to protect the internal circuitry of bipolar semiconductor integrated circuit devices with overvoltage protection elements. It has become clear from the inventor's study that this is large.

In order to increase the degree of integration of bipolar semiconductor integrated circuit devices, as the dimensions of bipolar transistors formed on the semiconductor substrate are reduced, the junctions of the bipolar transistors become shallower. In other words, the diffusion layers that form the base region and emitter region of bipolar transistors become thinner, and their junctions become shallower. In a bipolar transistor having such a shallow junction, the shallow junction portion is likely to be destroyed by high voltage surges caused by, for example, static electricity. Therefore, it has been found that if the degree of integration of a semiconductor integrated circuit device is to be increased, even if it is a bipolar type device, some kind of overvoltage protection measure is required.

As an overvoltage protection element used in bipolar semiconductor integrated circuit devices, for example, the
There is one described in Publication No. 21838. As shown in FIG. 1, the overvoltage protection element described in the publication includes an n ^- type epitaxial layer 3 as a first conductivity type region, and a second conductivity type region formed within this epitaxial layer 3. p-type base diffusion layer 60 as
and an n ⁺ -type emitter diffusion layer 70 as a first conductivity type region formed within the p-type base diffusion layer 60 . On both sides of these three conductivity type regions 3, 60, 70, there are two
NPN type bipolar transistors Q1 and Q2 are formed equivalently. Furthermore, one emitter of the bipolar transistors Q1 and Q2 is connected to the external input terminal pad Pi side, and the other emitter is connected to the protected circuit 10 side, and a resistor Ri is connected between both emitters. There is.

The above two bipolar transistors Q1, Q2
maintains a non-conducting state under normal conditions, but when a high voltage surge due to static electricity is applied from the terminal pad Pi, one of the bipolar transistors Q1
Alternatively, Q2 becomes an inverse transistor and becomes conductive, whereby the applied high voltage surge is bypassed to the potential of the power supply Vcc, and the internal circuit 1
0 is protected.

However, in the conventional overvoltage protection element described above, the innermost first conductivity type region of the bipolar transistors Q1 and Q2, that is, the n ⁺ type emitter diffusion layer 70, is connected to the external input terminal pad Pi side. . Therefore, a high voltage surge applied from the outside is concentrated on the innermost n ⁺ type emitter diffusion layer 70. Therefore, as the magnitude of the applied high voltage surge increases, there is a risk that the semiconductor junction between the emitter diffusion layer 70 and the base diffusion layer 60 will be destroyed by the high voltage surge.

As described above, conventional overvoltage protection elements still have room for improvement in terms of their durability.

[Purpose of the invention]

An object of the present invention is to provide a technique that improves the durability of an overvoltage protection element and makes it possible to reliably protect a protected circuit even from large-scale high voltage surges.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, by guiding the high voltage surge to the largest conductive area among the three conductive areas forming the bipolar transistor, the energy of the applied high voltage surge is dispersed, thereby improving the durability of the protection element. The purpose of this is to improve the protection and provide reliable protection.

〔Example〕

Hereinafter, typical embodiments of the present invention will be described with reference to the drawings.

In the drawings, the same reference numerals indicate the same or corresponding parts.

FIG. 2 shows the structure of the overvoltage protection element according to the present invention using a sectional view and a plan layout diagram. In the figure, a indicates its cross-sectional state, and b indicates its planar layout state.

The overvoltage protection device shown in FIGS. 2a and 2b is an active type overvoltage protection device constructed using bipolar transistors, and is connected between the internal circuit 10 of the bipolar semiconductor integrated circuit device and the external input terminal pad Pi. be mediated by

The semiconductor integrated circuit device uses a semiconductor substrate formed by forming an n ^- type epitaxial layer 3 on a p ^-U silicon semiconductor substrate 1, and has an internal circuit 10 made of bipolar elements formed by the iso-planar method. An island-shaped n ⁺ type buried layer 2 is formed under the epitaxial layer 3 for each element formation region. Further, each element forming region is electrically isolated by the thick partial oxide film 5 and the p ⁺ type isolation diffusion layer 4.

In this embodiment, the overvoltage protection element uses two types of bipolar transistors, and is configured to operate against high voltage surges of either positive or negative polarity.

First, an npn bipolar transistor Q2 is used as one of the bipolar transistors. This npn type bipolar transistor Q2 is formed in a vertical structure. That is, a p-type base diffusion layer 63 as a second conductivity type region is formed in the n ^- type epitaxial layer 3 as a first conductivity type region, and a first conductivity type region is further formed in this p-type base diffusion layer 63. An n ⁺ type emitter diffusion layer 7 is formed. The outermost first conductivity type region of this bipolar transistor Q2, that is, the collector region here, is connected to the external input terminal pad Pi side. This allows high pressure surges to be introduced from this collector region.

Furthermore, the above npn type bipolar transistor Q
2, an n ⁺ type collector diffusion layer (CN ⁺ ) 82 with a high conductive impurity concentration is formed in the n ^- type epitaxial layer 3 forming the collector region, and an aluminum wiring 9 is formed from this n ⁺ type collector diffusion layer 82. The collector electrode taken out is connected to the external input terminal pad Pi. This collector electrode is
It is also connected to the input side of the internal circuit 10 via a resistor Ri in series. bipolar transistor Q2
The base and emitter of are both connected to the negative side of the power supply, here to ground potential.

As the other bipolar transistor Q1, a pnp type bipolar transistor Q1 is used. This pnp type bipolar transistor Q
2 is formed in a lateral type structure. That is, two second conductivity type regions are disposed laterally with the n ^- type epitaxial layer 3 as the first conductivity type region sandwiched therebetween. The two second conductivity type regions are p ⁺ type diffusion layers 61 and 62, one of which functions as a collector region and the other as an emitter region. Then, one of the second conductivity type regions, that is, the p ⁺ type diffusion layer 62 serving as the collector region is connected to the external input terminal pad Pi side. At this time,
The size of the p ⁺ -type diffusion layer 62 which becomes the collector region is the same as or larger than that of the p ⁺ -type diffusion layer 61 which becomes the emitter region. In this embodiment, both are formed to have approximately the same size. The diffusion layers 61 and 62 are arranged to face each other, thereby reducing the layout area.
This also makes it possible to reduce parasitic capacitance.

Furthermore, the above pnp type bipolar transistor Q
Regarding No. 1, an n ⁺ type collector diffusion layer (CN ⁺ ) 81 with a high conductive impurity concentration is formed in the n ^- type epitaxial layer 3 forming the base region, and from this n ⁺ type collector diffusion layer 81 an aluminum wiring 9 is formed. The base electrode is taken out. This base electrode is connected to the positive power supply Vcc together with the emitter electrode taken out by the aluminum wiring 9 as well. In addition, the collector electrode taken out from the p ⁺ type diffusion layer 62 by the aluminum wiring 9 is
It is also connected to the input side of the internal circuit 10 via a resistor Ri in series.

FIG. 3 shows an equivalent circuit of the overvoltage protection element shown in FIG. 2.

The circuit of the overvoltage protection element shown in FIG.
As shown in FIG. 1A, the collectors 62 and 3 of the pnp bipolar transistor Q1 and the npn bipolar transistor Q2 are respectively connected to the external input terminal pad Pi. Along with this, pnp
The base and emitter of the type bipolar transistor Q1 are connected to a positive power supply Vcc, and the base and emitter of the npn type bipolar transistor Q2 are connected to the ground potential. At this time, the input terminal pad
When neither positive nor negative high voltage surge is applied to Pin, each transistor Q1, Q2 is
Since the voltage between the base and emitter becomes almost 0 (zero), both maintain an OFF (non-conducting) state. As a result, the signal given to the input terminal pad Pi is transmitted to the two transistors Q1 and Q.
2, it is normally guided to the input side of the internal circuit 10.

Here, as shown in FIG. 5B, when a positive high voltage surge power supply +Vp is connected to the input terminal pad Pi, the pnp type bipolar transistor Q1 starts to operate as an inverse transistor.
Then, this pnp type bipolar transistor Q1
receives base current from the input terminal pad Pi side and becomes ON (conducting) state. As a result, the positive high voltage surge applied to the input terminal pad Pin is bypassed to the power supply Vcc side through the collector-emitter of the pnp type bipolar transistor Q1. As a result, the input side potential of the internal circuit 10 is clamped to near the voltage of the power supply Vcc, so that the internal circuit 10 is reliably protected from the high voltage surge power supply +Vp.

Also, as shown in Figure c, when the negative high voltage surge power supply -Vp is connected to the input terminal pad Pi,
This time, the npn type bipolar transistor Q2 begins to operate as an inverse transistor. This npn type bipolar transistor Q2 is
The input terminal pad receives base current from the Pi side and becomes ON (conducting). As a result, the negative high voltage surge applied to the input terminal pad Pin is bypassed to the negative side of the power supply Vcc, that is, to the ground potential side here, through the collector-emitter of the npn bipolar transistor Q2. As a result, the input side potential of the internal circuit 10 is clamped to near the ground potential, so that the internal circuit 10 is reliably protected from the high voltage surge power supply -Vp.

In the manner described above, the internal circuit 10 can be protected from positive polarity high voltage surges or negative polarity high voltage surges.What should be noted here is that the high voltage surges cover a relatively large conductive area. This means that it is bypassed by being guided to the collector region. By guiding the high voltage surge to a relatively large conductive area in this way, the energy of the high voltage surge is dispersed, which makes it difficult to destroy the junction between the emitter and base of the bipolar transistor that constitutes the protection element, and as a result, It becomes possible to reliably perform protective operation without being destroyed even in the face of large-scale high-pressure surges.

〔effect〕

(1) Connect the collector sides of the pnp bipolar transistor and npn bipolar transistor to the external terminal side, and connect the base and emitter of the pnp bipolar transistor to the positive side of the power supply, and connect the base and emitter of the npn bipolar transistor to the positive side of the power supply. Connect each to the negative side of the power supply,
By making the pnp bipolar transistor conductive when a positive overvoltage is applied, and the npn bipolar transistor conducting as an inverse transistor when a negative overvoltage is applied, high voltage surges of either positive or negative polarity can be prevented. The effect is that it can also operate as a protection element against.

(2) At the same time, the energy of the high voltage surge can be dispersed by guiding the high voltage surge to the collector region consisting of a relatively large conductive area, thereby increasing the durability of the overvoltage protection element itself. The effect is that the protected circuit can be reliably protected even from large-scale high-voltage surges.

[Application field]

The above explanation has mainly been about the application of the invention made by the present inventor to an overvoltage protection element for a bipolar semiconductor integrated circuit device, which is the background field of application, but the invention is not limited thereto. For example, it can also be applied to overvoltage protection elements of C-MOS type or bipolar/MOS mixed type semiconductor integrated circuit devices.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a conventional overvoltage protection element, FIGS. FIG. 3 is a diagram showing an equivalent circuit of the overvoltage protection element shown in the figure. DESCRIPTION OF SYMBOLS 1... p ^- type silicon semiconductor substrate, 2... n ⁺ type buried layer, 3... first conductivity type region (n ^- type epitaxial layer), 4... p ⁺ type isolation diffusion layer, 5... Partial oxide film, 61, 62... Second conductivity type region (p ⁺ type diffusion layer), 63... Second conductivity type region (p type base diffusion layer), 7... First conductivity type region (n ⁺ type Emitter diffusion layer), 81, 82...n ⁺ type collector diffusion layer (CN ⁺ ), 9... Aluminum wiring, 10... Protected circuit (internal circuit), Ri... Resistor, Vcc... Power supply (positive) , Q1...PNP bipolar transistor with lateral structure, Q2...NPN with vertical structure
type bipolar transistor, Pi...Input terminal pad, +Vp...Positive high voltage surge power supply, -Vp...Negative high voltage surge power supply.

Claims (1)

[Claims] 1. An active type constructed using a bipolar transistor that conducts only when an overvoltage is applied to perform a voltage clamping operation, and an input terminal for protecting the input base of the bipolar transistor that constitutes the circuit to be protected. An overvoltage protection element to be connected,
The bipolar transistor for the protection element has a P-type semiconductor substrate, an N-type epitaxial layer on the main surface of the substrate, and a separation layer that reaches the substrate from the main surface of the N-type epitaxial layer. thus forming separated first and second island regions,
In the first and second island regions, there are first and second N-type buried layers of high concentration in contact with the substrate, respectively, and on the main surface thereof with the first island region as a base region. are a P-type region for emitter and a P-type region for collector as a lateral PNP configuration separated from each other,
It has a first N-type region of high concentration in contact with the first N-type buried layer, and has a P-type base for a vertical NPN configuration on its main surface with the second island region as a collector. an emitter N-type region in the base P-type region and a highly doped second N-type region in contact with the second N-type buried layer, and the highly doped first N-type region and the P-type emitter region are electrically connected to one positive power supply, the N-type emitter region and the P-type base region are electrically grounded, and the high concentration second N-type region and a collector P-type region are electrically connected and connected to the input terminal, so that when a positive overvoltage is applied, the PNP type bipolar transistor is activated, and when a negative overvoltage is applied, the PNP type bipolar transistor is activated. Sometimes NPN
An overvoltage protection element characterized in that bipolar transistors are made conductive as inverse transistors. 2. An overvoltage protection element that is an active type constructed using a bipolar transistor that conducts only when an overvoltage is applied to perform a voltage clamping operation, and is connected to the input terminal to protect the input base of the bipolar transistor that constitutes the protected circuit. And,
The bipolar transistor for the protection element has a P-type semiconductor substrate, an N-type epitaxial layer on the main surface of the substrate, and a separation layer that reaches the substrate from the main surface of the N-type epitaxial layer. thus forming separated first and second island regions,
In the first and second island regions, there are first and second N-type buried layers of high concentration in contact with the substrate, respectively, and on the main surface thereof with the first island region as a base region. are a P-type region for emitter and a P-type region for collector as a lateral PNP configuration separated from each other,
It has a first N-type region of high concentration in contact with the first N-type buried layer, and has a P-type base for a vertical NPN configuration on its main surface with the second island region as a collector. In the first island region, there is an N-type emitter region in the P-type region for the base and a second N-type region with a high concentration in contact with the second N-type buried layer. A thick partial oxide film is located between the emitter P-type region and the high concentration first N-type region and does not reach the first N-type buried layer; has a thick partial oxide film that is located between the base P-type region and the high concentration second N-type region and does not reach the second N-type buried layer; The first N-type region and the emitter P-type region are electrically connected to one positive power supply, the emitter N-type region and the base P-type region are electrically grounded, and the high concentration The second N-type region and the collector P-type region are electrically connected and connected to the input terminal, and when a positive overvoltage is applied, the PNP
An overvoltage protection element characterized in that the NPN type bipolar transistors are made to conduct as inverse transistors when a negative overvoltage is applied.