JPH0511667B2 - - Google Patents
Info
- Publication number
- JPH0511667B2 JPH0511667B2 JP61170215A JP17021586A JPH0511667B2 JP H0511667 B2 JPH0511667 B2 JP H0511667B2 JP 61170215 A JP61170215 A JP 61170215A JP 17021586 A JP17021586 A JP 17021586A JP H0511667 B2 JPH0511667 B2 JP H0511667B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- resistor
- polycrystalline silicon
- layer
- input protection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 25
- 239000010410 layer Substances 0.000 description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 18
- 239000011229 interlayer Substances 0.000 description 11
- 230000005684 electric field Effects 0.000 description 5
- 230000005611 electricity Effects 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に内部回路を外
部からの静電気による破壊から守る為の入力保護
回路、なかんずく多結晶シリコン層配線を入力保
護抵抗として用いられ、かつ半導体装置が形成さ
れている基板が電源電位もしくは接地電位に置か
れている場合の入力保護回路を備えた半導体装置
に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, and particularly to an input protection circuit for protecting an internal circuit from damage caused by external static electricity, and in particular, an input protection circuit using a polycrystalline silicon layer wiring as an input protection resistor. The present invention relates to a semiconductor device equipped with an input protection circuit used when a substrate on which the semiconductor device is formed is placed at a power supply potential or a ground potential.
従来この種の半導体装置はボンデイングパツド
が、層間絶縁膜に開孔された接続窓を通じて多結
晶シリコン層からなる抵抗に接続され、これが入
力信号回路の初段トランジスタへ至る配線の一部
として構成されていた。さらに抵抗の前後または
これと並列にPN接合やトランジスタの降状電圧
を利用した保護回路が設けられることが多い。い
ずれにしろ、多結晶シリコン層による抵抗は層間
絶縁膜を介して基板上に配され、下には基板と反
対導電型の不純物拡散領域や、金属、多結晶シリ
コン配線等は何も置かれない場合が多い。
Conventionally, in this type of semiconductor device, a bonding pad is connected to a resistor made of a polycrystalline silicon layer through a connection window made in an interlayer insulating film, and this is configured as part of the wiring leading to the first stage transistor of the input signal circuit. was. Furthermore, a protection circuit that utilizes a PN junction or a transistor's drop voltage is often provided before, after, or in parallel with the resistor. In any case, the resistance formed by the polycrystalline silicon layer is placed on the substrate via the interlayer insulating film, and there is no impurity diffusion region of the opposite conductivity type to the substrate, metal, polycrystalline silicon wiring, etc. underneath. There are many cases.
半導体装置の高度密度化に伴い、デザインルー
ムは平面的に配線幅や間隔が縮小されてゆくと同
時に、使用される不純物拡散領域の深度は浅くな
り層間絶縁膜の厚さも薄くなつている。この為、
こうした高密度化適応のプロセスを用いて設計す
る際、従来問題とならなかつた新たな障害を避け
る為の工夫が必要となつてくる。 With the increasing density of semiconductor devices, the width and spacing of interconnects in the design room are being reduced in two dimensions, and at the same time, the depth of the impurity diffusion regions used is becoming shallower, and the thickness of the interlayer insulating film is also becoming thinner. For this reason,
When designing using this densification adaptation process, it becomes necessary to devise ways to avoid new obstacles that did not pose problems in the past.
前述した従来の入力保護回路においても、半導
体装置自体が薄い層間絶縁膜を使用する結果、多
結晶シリコンによる抵抗と基板との距離が短かく
なり、従来に無かつた障害が発生する。高電圧の
静電気印加により多結晶シリコン抵抗が層間絶縁
膜を突き破り、基板へ注入することにより生じ
る、基板との短絡である。基板が例えば電源電位
にあれば、結局、入力信号線は電源に短絡されて
しまう。 Even in the conventional input protection circuit described above, as a result of using a thin interlayer insulating film in the semiconductor device itself, the distance between the polycrystalline silicon resistor and the substrate becomes short, resulting in failures that have not occurred in the past. This is a short circuit with the substrate that occurs when the polycrystalline silicon resistor breaks through the interlayer insulating film and is injected into the substrate due to the application of high voltage static electricity. If the substrate is at a power supply potential, for example, the input signal line will end up being shorted to the power supply.
上述した従来の半導体装置は、入力保護抵抗が
絶縁膜を介して半導体基板上に設けられているの
で、高密度化に伴い絶縁膜が薄くなつてくると実
際にパツドから静電気が印加された場合に高電界
が生じ保護回路が破壊するという欠点がある。
In the conventional semiconductor device described above, the input protection resistor is provided on the semiconductor substrate via an insulating film, so as the insulating film becomes thinner due to higher density, if static electricity is actually applied from the pad. The drawback is that a high electric field is generated and the protection circuit is destroyed.
本発明の半導体装置は、信号入力端子に接続さ
れたボンデイングパツドと内部回路の初段のトラ
ンジスタの間に挿入され、半導体基板上に絶縁膜
を介して設けられた低抗層を入力保護抵抗として
有する半導体装置において、前記抵抗層と前記半
導体基板との間に導電層が直流的に周囲と絶縁さ
れて設けられているものである。
In the semiconductor device of the present invention, a low resistance layer is inserted between a bonding pad connected to a signal input terminal and a first stage transistor of an internal circuit, and is provided on a semiconductor substrate with an insulating film interposed therebetween, as an input protection resistor. In the semiconductor device, a conductive layer is provided between the resistive layer and the semiconductor substrate so as to be insulated from the surroundings in terms of direct current.
次に本発明の実施例について図面を参照して説
明する。
Next, embodiments of the present invention will be described with reference to the drawings.
第１図ａは本発明の一実施例の主要部を示す半
導体チツプの平面図、第１図ｂは第１図ａのＸ−
X′線断面図である。 FIG. 1a is a plan view of a semiconductor chip showing the main parts of an embodiment of the present invention, and FIG. 1b is a
It is an X′-line cross-sectional view.
この実施例は、信号入力端子に接続されたボン
デイングパツド１と内部回路の初段の電界効果ト
ランジスタのゲートとの間に挿入され、半導体基
板８上に絶縁膜を介して設けられた多結晶シリコ
ンからなる抵抗層を入力保護抵抗２として有する
半導体装置において、前述の抵抗層と前期半導体
基板８との間に多結晶シリコンからなる導電層５
が直流的に周囲と絶縁されて設けられているもの
である。 In this embodiment, a polycrystalline silicon bonding pad 1 connected to a signal input terminal and a gate of a first stage field effect transistor of an internal circuit is inserted, and is provided on a semiconductor substrate 8 with an insulating film interposed therebetween. In a semiconductor device having a resistance layer made of polycrystalline silicon as an input protection resistor 2, a conductive layer 5 made of polycrystalline silicon is provided between the above-mentioned resistance layer and the semiconductor substrate 8.
is installed so that it is insulated from the surroundings in terms of direct current.
詳述すると、ボンデイングパツド１はこの実施
例を製造する半導体プロセスにおいては最後に形
成される配線層であるアルミニウム層のパターニ
ングして形成される。層の厚さは約1.2μｍであ
る。多結晶シリコン層による入力保護抵抗２は厚
さ0.4μｍ、幅2.5μｍであつて、一端が、この多結
晶シリコン層の形成後ボンデイングパツド１を形
成する以前に形成される厚さ0.3μｍの酸化シリコ
ンからなる層間絶縁膜３に開孔された接続窓４部
においてボンデイングパツド１に接続され、他端
は入力保護回路を構成するトランジスタ等を介す
るか、または直接に、内部回路の初段のトランジ
スタ（図示しない）のゲート電極へ接続されてい
る。他の多結晶シリコン層からなる導電層５（厚
さ0.4μｍ）は層間絶縁膜３とは異なる層間絶縁膜
６（厚さ0.35μｍ）を介して、入力保護抵抗２の
直下の領域を含む領域に形成されている。言い換
えれば導電層５は入力保護抵抗２から半導体基板
８をみた時にちようど相互をさえぎる状態で置か
れていることになる。導電層５は半導体装置内の
いかなる配線にも接続されていない。半導体基板
８はしかるべき場所で電源線に接続されている。 More specifically, the bonding pad 1 is formed by patterning an aluminum layer, which is the last wiring layer formed in the semiconductor process for manufacturing this embodiment. The layer thickness is approximately 1.2 μm. The input protection resistor 2 made of a polycrystalline silicon layer has a thickness of 0.4 μm and a width of 2.5 μm. It is connected to the bonding pad 1 through the connection window 4 formed in the interlayer insulating film 3 made of silicon oxide, and the other end is connected to the first stage of the internal circuit, either through a transistor or the like constituting the input protection circuit, or directly. It is connected to the gate electrode of a transistor (not shown). A conductive layer 5 (thickness: 0.4 μm) made of another polycrystalline silicon layer is connected to a region including the region directly under the input protection resistor 2 via an interlayer insulating film 6 (thickness: 0.35 μm) different from the interlayer insulating film 3. is formed. In other words, when the semiconductor substrate 8 is viewed from the input protection resistor 2, the conductive layers 5 are placed in such a state that they just block each other. The conductive layer 5 is not connected to any wiring within the semiconductor device. The semiconductor substrate 8 is connected to a power supply line at an appropriate location.
いま、ボンデイングパツド１に接地電位を基準
にマイナス方向に静電圧を印加したとする。従来
例では導電層５が無い為に、入力保護抵抗２と半
導体基板８との間には高電界が生じ、これにより
加速された多結晶シリコンの一部が入力保護抵抗
２から半導体基板８へ注入される結果として、入
力端子ピンと電源との短絡が発生した。 Now, assume that an electrostatic voltage is applied to the bonding pad 1 in a negative direction with respect to the ground potential. In the conventional example, since there is no conductive layer 5, a high electric field is generated between the input protection resistor 2 and the semiconductor substrate 8, and this accelerates a part of the polycrystalline silicon from the input protection resistor 2 to the semiconductor substrate 8. As a result of the injection, a short circuit between the input terminal pin and the power supply occurred.
この実施例においては、導電層５の介在により
上記高電界は暖められ、上述の様な現象は極めて
発生しにくい。さらに、非常にまれに、注入が発
生するとしても、注入された多結晶シリコンは層
間絶縁膜６を突破して導電層５にただかが達する
のみで、その下の基板とのフイールド絶縁膜７を
も突破することは無い。従つて、本実施例によ
り、保護抵抗を形成する多結晶シリコンから基板
への注入による漏れ電流不良は解決される。 In this embodiment, the high electric field is warmed by the presence of the conductive layer 5, and the above-mentioned phenomenon is extremely unlikely to occur. Furthermore, even if implantation occurs in very rare cases, the implanted polycrystalline silicon will only break through the interlayer insulating film 6 and reach the conductive layer 5, and the field insulating film 7 with the substrate below. There is no way to break through. Therefore, this embodiment solves the problem of leakage current caused by injection into the substrate from the polycrystalline silicon forming the protective resistor.
これは、入力保護抵抗２と半導体基板間に加わ
る電圧が入力保護抵抗２と導電層５間の静電容量
及び導電層５と半導体基板８間の静電容量によつ
て分割されるため危険分散されるほか、導電層５
の面積を入力保護抵抗のそれより大きくすること
によつて導電層５と半導体基板８間の電界強度が
小となるからである。 This spreads the risk because the voltage applied between the input protection resistor 2 and the semiconductor substrate is divided by the capacitance between the input protection resistor 2 and the conductive layer 5 and the capacitance between the conductive layer 5 and the semiconductor substrate 8. In addition, the conductive layer 5
This is because by making the area larger than that of the input protection resistor, the electric field strength between the conductive layer 5 and the semiconductor substrate 8 is reduced.
以上説明したように本発明は、入力保護抵抗と
半導体基板との間に浮遊状態にある導電層を設け
て、危険分散及び電界緩和を図ることにより、信
号入力端子の漏れ電流の発生を抑えることができ
る効果がある。
As explained above, the present invention suppresses the occurrence of leakage current at the signal input terminal by providing a floating conductive layer between the input protection resistor and the semiconductor substrate to disperse danger and alleviate the electric field. There is an effect that can be done.
第１図ａは本発明の一実施例の主要部を示す半
導体チツプの平面図、第１図ｂは第１図ａのＸ−
X′線断面図である。
１……ボンデイングパツド、２……多結晶シリ
コンからなる入力保護抵抗、３……アルミニウム
−多結晶シリコン層間の層間絶縁膜、４……接続
窓、５……多の他結晶シリコン層からなる導電
層、６……多結晶シリコン層間の層間絶縁膜、７
……フイールド絶縁膜、８……半導体基板。
FIG. 1a is a plan view of a semiconductor chip showing the main parts of an embodiment of the present invention, and FIG. 1b is a
It is an X′-line cross-sectional view. 1... bonding pad, 2... input protection resistor made of polycrystalline silicon, 3... interlayer insulating film between aluminum and polycrystalline silicon layer, 4... connection window, 5... made of polycrystalline silicon layer Conductive layer, 6...Interlayer insulating film between polycrystalline silicon layers, 7
...Field insulating film, 8...Semiconductor substrate.
Claims (1)
ドと内部回路の初段のトランジスタの間に挿入さ
れ、半導体基板上に絶縁膜を介して設けられた抵
抗層を入力保護抵抗として有する半導体装置にお
いて、前記抵抗層と前記半導体基板との間に導電
層が直流的に周囲と絶縁されて設けられているこ
とを特徴とする半導体装置。1. In a semiconductor device having as an input protection resistor a resistor layer inserted between a bonding pad connected to a signal input terminal and a first-stage transistor of an internal circuit and provided on a semiconductor substrate with an insulating film interposed therebetween, the resistor A semiconductor device characterized in that a conductive layer is provided between the layer and the semiconductor substrate so as to be insulated from the surroundings in terms of direct current.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61170215A JPS6327044A (en) | 1986-07-18 | 1986-07-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61170215A JPS6327044A (en) | 1986-07-18 | 1986-07-18 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6327044A JPS6327044A (en) | 1988-02-04 |
| JPH0511667B2 true JPH0511667B2 (en) | 1993-02-16 |
Family
ID=15900803
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61170215A Granted JPS6327044A (en) | 1986-07-18 | 1986-07-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6327044A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009278078A (en) * | 2008-04-18 | 2009-11-26 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2739004B2 (en) * | 1992-01-16 | 1998-04-08 | 三菱電機株式会社 | Semiconductor device |
| JP2006086211A (en) * | 2004-09-14 | 2006-03-30 | Denso Corp | Semiconductor device |
-
1986
- 1986-07-18 JP JP61170215A patent/JPS6327044A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009278078A (en) * | 2008-04-18 | 2009-11-26 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6327044A (en) | 1988-02-04 |
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