JPS59213155A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To contrive to improve the surge withstand voltage by forming a region of the other conductivity type in contact with a buried region of one conductivity type, in the titled device using oxide film isolation. CONSTITUTION:In said device having the oxide film 5 to isolate an N type epitaxial layer 4 frm the other N type epitaxial layer, a P-N diode 15 is formed by contacting the N<+> type buried region 2 with a P<+> type region 3. Said region 3 is enabled to contact only said region 2 on the input stage, not the other N<+> type buried region. In such a construction, when a positive surge voltage is impressed on the input, the series resistance of the four diodes connected to the input is: input SBD 11 at 150OMEGA, input clamp diode 12 at 100OMEGA, parasitic P-N diode 14 at 500OMEGA, and P-N diode 15 at 100OMEGA. Therefore, of the current let flow in by the surge voltage, the current passing through the P-N diode 15 is at 35%, and then the heat generated in the input clamp diode 12 reduces to 65% of conventional one. In other words, the input surge withstand voltage can be enhanced to 1.5 times as much as the conventional one.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit device, particularly to improving the surge withstand voltage of a semiconductor integrated circuit device using oxide film separation.

[Prior art]

An equivalent circuit of an input section of a conventional semiconductor integrated circuit device using this type of oxide film separation is shown in FIG. 1, and a plan view and a cross-sectional view thereof are shown in FIG.

In each of these figures, the symbols (11 is a p-type substrate, (2)
is the n+ type buried region, and (3) is this n+ type buried region (
2) and other r-type buried regions to prevent leakage current (4) is an n-type epitaxial layer, (5)
is an oxide film for separating this n-type epitaxial layer (4) from other n-type epitaxial layers, and (6) is an oxide film that makes contact with the aluminum wiring (8) ohmic, and
The n+ type region (7) is an oxide film to protect the surface of the n type epitaxial layer (4) to lower the resistance between the and buried region (2), and the aluminum wiring (8) is connected to the input terminal. , (9) is the aluminum wiring connected to the GND terminal, 〔 is the aluminum wiring connected to the internal circuit, ■ is the input Schottky barrier diode (hereinafter referred to as input SBD), 02
is the input clamp diode, θ is this manual clamp diode (1 guard ring, 0 is the parasitic pn diode).

There is a positive voltage at the input of this conventional device.

In other words, when a momentary high voltage is applied, the input 5BD
Qυ, the input clamp diode circle, and the parasitic pn diode I break down and current flows. Power equal to the product of this breakdown current and breakdown voltage is dissipated into heat at the junction of each diode, and if the temperature at the junction becomes excessive, the diode is destroyed. In this case, there is no big difference in breakdown voltage,
It can be assumed that the diode through which a large breakdown current flows is more likely to be destroyed, and the series resistance of the diode that limits the breakdown voltage is estimated to be 5 BD (150 Ω for lυ, 1000 Ω for the input clamp diode a, and 500 Ω for the parasitic pn diode αa). Therefore, the input clamp diode (121) was the one most easily destroyed.

[Summary of the invention]

In order to improve the resistance to destruction of the conventional input 2-amp diode, the present invention connects the n+ type buried region and the p+ type buried region to form a pn diode having an appropriate series resistance.
By forming a diode and causing a portion of the current flowing through the input clamp diode to flow through the p+ type region, it is attempted to obtain a semiconductor integrated circuit device that can withstand high surge voltages.

[Embodiments of the invention]

Hereinafter, one embodiment of the inventive device will be described in detail with reference to FIGS. 3 and 4.

Also in this embodiment device, FIG. 3 is an equivalent circuit diagram of the input section, and FIG. 4 is a sectional view of the same as above, and in each of these figures, the same reference numerals as in the conventional example in FIGS. In this example device, the n+ type buried region (2) and the p+ type region 3) are brought into contact with each other.
An n diode a9 is formed.

And the series resistance of the pn diode α is 150Ω,
The capacitance can be estimated to be 2 pF, and although a small capacitance does not pose a problem for input or output, it causes a time delay inside a semiconductor integrated circuit, so the p+ type region 3) is used as an n-type buried region in the input stage. (2) and not other n+ type buried regions.

Consider a case where a positive surge voltage is applied to the input in this embodiment configuration. As mentioned earlier, the series resistance of the four diodes connected to the input is equal to the input 5BD (
lυ is 150Ω, input voltage 2-amp diode a is 100Ω
Ω, the parasitic PM diode I is 500Ω, and the pn diode a9 is 100Ω, so the current flowing from the input due to the surge voltage is proportional to the energy of the surge voltage, and the equivalent of 35Ω is absorbed by this pn diode. In particular, the heat generated in the input clamp diode t1'3 is reduced to 659 g compared to the conventional one. In other words, the human-powered surge withstand voltage is 1.5 times that of conventional methods.
065=1.5). As a result of the experiment, the surge voltage was 220V, which was previously 150V.

The voltage was increased from 170v to 230v.

If even higher surge withstand voltage is required, the concentration of the p shadow region (3) can be increased, and in this case, more heat than is generated in the input clamp diode Q! 9, but the pm diode a
Since the area of the input clamp diode Q3 is about 10 times that of the input clamp diode Q3, the amount of heat per unit area is small and there is no problem.

〔Effect of the invention〕

As described in detail above, according to the present invention, in a semiconductor integrated circuit device using oxide film isolation, a buried region of one conductivity type is simply formed in contact with a conductive shadow region of the other conductivity type.
With an extremely simple configuration, the surge withstand voltage can be improved.

[Brief explanation of the drawing]

1 and 2 (a) and 2 (b) are equivalent circuit diagrams showing a conventional semiconductor integrated circuit device, and a partial plan view and cross-sectional view of the general configuration, and FIGS. 3 and 4. 1 is an equivalent circuit diagram and a sectional view of a schematic configuration of a semiconductor integrated circuit device according to an embodiment of the present invention; FIG. (1)・e...p type substrate, (2)...n type epitaxial layer, (3)...Φ・p+ type region (4)...
n-type epitaxial layer, (5)...isolation oxide film,
(6)...N+ type area (7)...Oxide film for surface protection, (8)~α[...e aluminum wiring, αυ9@・
・Input Schottky barrier diode, az...input clamp diode, α$...pn diode (junction). Agent Masuo Oiwa 1, Indication of the case Japanese Patent Application No. 58-87893 21 Title of the invention Semiconductor integrated circuit device 3, Relationship to the person making the amendment Case Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Hitoshi Katayama 4, Agent address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Brief explanation of drawings column 6 of the description of the amendment No. 6 Correct "n-type epitaxial layer" in lines 18-19 of the page to "n-type buried region" 6.
that's all

Claims (1)

[Claims] A first conductivity type substrate, a second conductivity type region embedded in this substrate, and a substrate formed on the surface of the substrate to selectively form a junction with the second conductivity type region also have an impurity concentration. an epitaxial layer of a second or first conductivity type grown on the second conductivity type region;
1. A semiconductor integrated circuit device comprising at least an oxide film located on a conductive region and separating an epitaxial layer.