JPS6080273A - Semiconductor device of high withstand voltage - Google Patents

Semiconductor device of high withstand voltage

Info

Publication number
JPS6080273A
JPS6080273A JP18819783A JP18819783A JPS6080273A JP S6080273 A JPS6080273 A JP S6080273A JP 18819783 A JP18819783 A JP 18819783A JP 18819783 A JP18819783 A JP 18819783A JP S6080273 A JPS6080273 A JP S6080273A
Authority
JP
Japan
Prior art keywords
region
film
type
substrate
diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18819783A
Other languages
Japanese (ja)
Inventor
Fumihiko Kitahara
北原 文彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP18819783A priority Critical patent/JPS6080273A/en
Publication of JPS6080273A publication Critical patent/JPS6080273A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To obtain the characteristic of stable withstand voltage by a method wherein, when a semiconductor substrate serving as a collector is provided with a base region and an emitter region positioned therein into a bi-polar transistor, the element region is surrounded with a field limit ring of the conductivity type different from that of the substrate, and a conductor layer is provided thereon via insulation film. CONSTITUTION:The P type base region 2 is diffusion-formed in the surface layer part of the N type semiconductor substrate 1 serving as the collector, and the N type emitter region 3 is provided therein into the bi-polar transistor. Next, in addition, the P type field limit ring regions 4 and 5 surrounding the region 2 are perpendicularly diffusion-formed in the substrate at an interval, and an SiO2 film 10 is adhered from above these regions to the end of the region 2. Thereafter, Al films 8 corresponding to the regions 4 and 5 respectively are adhered by being positioned on the film 10, and an Al film 9 is provided at the end of the film 10 and connected to an N<+> type region 11 formed in the substrate at the end of the film 10. Thus, the penetration of external ions to the element region is blocked.

Description

【発明の詳細な説明】 (1) 発明の属する分野 本発明は高耐圧半導体装置に係9、特にプレーナ接合に
より形成される高耐圧トランジスタ又はダイオード、サ
イリスタ、トライブック等の半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION (1) Field of the Invention The present invention relates to high voltage semiconductor devices, and particularly to semiconductor devices such as high voltage transistors or diodes, thyristors, and try books formed by planar junctions.

従来の高耐圧半導体装置に於いて、高耐圧化を計る為に
フィールドリミットリングを用い、加えて安定性を計る
為に熱酸化膜に窒化膜や有機材料を積層していた。また
接合端を鉛ガラス等のガラス系材料により保護する方法
もとられていた。
In conventional high-voltage semiconductor devices, a field limit ring is used to increase the voltage resistance, and in addition, a nitride film or an organic material is layered on top of a thermal oxide film to ensure stability. Another method has been to protect the joint end with a glass-based material such as lead glass.

しかし高耐圧化が進むにつれて、このようなフィールド
リミットリングと窒化膜等を用いる従来構造では充分に
安定な耐圧特性を得られず、ガラス系材料を用いる構造
では温度変化に弱い欠点が明らかになってきた。
However, as voltage resistance increases, it has become clear that conventional structures using field limit rings and nitride films are unable to obtain sufficiently stable voltage resistance characteristics, and structures using glass-based materials have the disadvantage of being susceptible to temperature changes. It's here.

(3)発明の目的 本発明の目的はこれら従来の欠点のない安定な耐圧特性
をもち、温度変化に強い高耐圧半導体装置を提供するも
のである。
(3) Object of the Invention An object of the present invention is to provide a high voltage semiconductor device that does not have these conventional drawbacks, has stable voltage resistance characteristics, and is resistant to temperature changes.

(4)発明の構成 、 本発明の特徴は一導電型の半導体基板の少なくとも
1方の面にブレーナ拡散により形成される一導電型と逆
の導電型を有する第1及び第2いは前記第1及び第2の
拡散層とこれら拡散層の少なくとも一方にこの導電型と
反対の導電型を有する第3の拡散層をもつPNP又はN
PNの3層構造あるいはPNPN 、NPNP04層構
造の第1と第2の拡散層の各々に隣接してこれらの拡散
領域を取り囲みこれらと同導電屋を有する複数個の第4
及び第5の拡散層を持ち第4及び第5の少なくとも一方
の拡散層の露出面上を熱酸化膜等の表面保護膜を介して
アルミ等の導電体(通常金属)により被服する事にある
(4) Structure of the Invention A feature of the present invention is that first and second or said first and second conductivity types having a conductivity type opposite to one conductivity type are formed by Breaner diffusion on at least one surface of a semiconductor substrate of one conductivity type. PNP or N having first and second diffusion layers and a third diffusion layer having a conductivity type opposite to this one in at least one of these diffusion layers.
Adjacent to each of the first and second diffusion layers of the PN three-layer structure, PNPN, or NPNP04-layer structure, a plurality of fourth diffusion layers surround these diffusion regions and have the same conductive layer as these.
and a fifth diffusion layer, and the exposed surface of at least one of the fourth and fifth diffusion layers is covered with a conductor (usually metal) such as aluminum through a surface protection film such as a thermal oxide film. .

本発明はこの導電体で被服する事により外部イオンの侵
入及び影響を防止し、寿命試験、環境試験等にょろり−
l電流の増加を抑制し安定した耐圧特性が得られる。
The present invention prevents the intrusion and influence of external ions by covering with this conductor, and is suitable for life tests, environmental tests, etc.
This suppresses the increase in current and provides stable breakdown voltage characteristics.

(5)実施例及び発明の効果 以下に本発明を図面を診照してより詳細に説明する。(5) Examples and effects of the invention The present invention will be explained in more detail below with reference to the drawings.

第1図はNPN型バイポーラトランジスタの外周断面構
造図である。Nfi半導体基板1にP型のベース領域2
とN型のエミッタ領域3とを有し、ベース領域2を囲む
ようにP型のフィールドリミットリング4,5があり、
このフィールドリミットリング4,5の表面露出部を熱
酸化膜(810z )あるいはこれにチン化膜等を積層
した保護膜10を介してアルミニウム膜8が積層されて
いる。これはアルミニウムの引き出し電極6,7形成時
に同時に形成されており何の子分な工程も増していない
。半導体基板1の周辺表面にはN+領域11が設けられ
てそこに酸化膜10表面から延びるアルミニウム膜9が
被着されている。
FIG. 1 is a sectional view of the outer circumference of an NPN bipolar transistor. P-type base region 2 on Nfi semiconductor substrate 1
and an N-type emitter region 3, and P-type field limit rings 4 and 5 surrounding the base region 2.
An aluminum film 8 is laminated on the exposed surface portions of the field limit rings 4, 5 via a protective film 10 formed by laminating a thermal oxide film (810z) or a tinned film or the like thereon. This is formed at the same time as the aluminum lead electrodes 6 and 7 are formed, and no additional steps are added. An N+ region 11 is provided on the peripheral surface of the semiconductor substrate 1, and an aluminum film 9 extending from the surface of the oxide film 10 is deposited thereon.

このように、アルミ等の導電体材料によりフィールドリ
ミットリング4.5上を被服する事により外的イオンの
侵入による電気的特性への影響が抑制され、コレクタ・
ベース間に逆方向電圧が印加された時にコレクタ層にコ
レクタ・ベース接合から広がる空乏層がフィールドリミ
ットリング4,5近傍で外部イオンの影響を受けること
がなく、安定した耐圧特性が得られる。
In this way, by covering the field limit ring 4.5 with a conductive material such as aluminum, the influence on the electrical characteristics due to the intrusion of external ions is suppressed, and the collector
When a reverse voltage is applied between the bases, the depletion layer that spreads from the collector-base junction to the collector layer is not affected by external ions in the vicinity of the field limit rings 4 and 5, and stable breakdown voltage characteristics can be obtained.

又製造工程上もマスク変更のみで従来工程同様に製作で
きる。加えてパッシベーション膜に熱酸化膜を用いてい
るので温夏変化にも強い等の効果が得られる。フィール
ドリミットリング4゜5上のアルミニウム膜8はベース
領域2に最も近いもの4上に設ければかなり効果があシ
、その外側のフィールドリミットリング5上にも設ける
と更に完全な効果が期待される。
Furthermore, the manufacturing process can be made in the same manner as the conventional process by simply changing the mask. In addition, since a thermal oxide film is used as the passivation film, effects such as resistance to changes in temperature can be obtained. If the aluminum film 8 on the field limit ring 4.5 is provided on the one 4 closest to the base region 2, it will be quite effective, and if it is provided on the field limit ring 5 outside of that, an even more perfect effect is expected. Ru.

同様にフィールドリミットリング上にアルミニウム膜を
形成する構造はダイオードに適用することもでき、この
場合には第1図のN型エミッタ領域3がない状態と同じ
である。更にサイリスタにも同様に適用することができ
る。
Similarly, the structure in which an aluminum film is formed on the field limit ring can also be applied to a diode, and in this case, the structure is the same as the state in which the N-type emitter region 3 of FIG. 1 is not provided. Furthermore, it can be similarly applied to thyristors.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例によるNPN型バイポーラト
ランジスタの部分断面図である。 1・・・・・・N型半導体基板、2・・・・・・P型ベ
ース領域、3・・・・・・N型エミッタ領域、4,5・
・・・・・P型拡散領域(フィールドリミットリング)
、6・・・・・・エミツ9・・・・・・アルミニウム膜
、10・・・・・・表面保護膜(8102もしくはSi
N積層)。
FIG. 1 is a partial cross-sectional view of an NPN bipolar transistor according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... N-type semiconductor substrate, 2... P-type base region, 3... N-type emitter region, 4, 5...
...P-type diffusion region (field limit ring)
, 6... Emitsu 9... Aluminum film, 10... Surface protective film (8102 or Si
N lamination).

Claims (1)

【特許請求の範囲】[Claims] 一導電型をもつ半導体基板の表面に形成された前記−導
電型と逆の導電型を有する半導体領域と該半導体領域の
周囲の前記半導体基板に形成でれた前記逆の導電型の環
状領域と、該環状領域上に絶縁膜を介して形成された導
体層とを有することを特徴とする高耐圧半導体装置。
a semiconductor region having a conductivity type opposite to the -conductivity type formed on the surface of a semiconductor substrate having one conductivity type; and an annular region having the opposite conductivity type formed on the semiconductor substrate around the semiconductor region; and a conductor layer formed on the annular region with an insulating film interposed therebetween.
JP18819783A 1983-10-07 1983-10-07 Semiconductor device of high withstand voltage Pending JPS6080273A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18819783A JPS6080273A (en) 1983-10-07 1983-10-07 Semiconductor device of high withstand voltage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18819783A JPS6080273A (en) 1983-10-07 1983-10-07 Semiconductor device of high withstand voltage

Publications (1)

Publication Number Publication Date
JPS6080273A true JPS6080273A (en) 1985-05-08

Family

ID=16219465

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18819783A Pending JPS6080273A (en) 1983-10-07 1983-10-07 Semiconductor device of high withstand voltage

Country Status (1)

Country Link
JP (1) JPS6080273A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100415189B1 (en) * 1997-01-10 2004-03-19 페어차일드코리아반도체 주식회사 Bipolar transistor having field limiting ring
KR100490333B1 (en) * 1996-09-09 2006-04-28 페어차일드코리아반도체 주식회사 Bipolar Transistors and Manufacturing Method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100490333B1 (en) * 1996-09-09 2006-04-28 페어차일드코리아반도체 주식회사 Bipolar Transistors and Manufacturing Method
KR100415189B1 (en) * 1997-01-10 2004-03-19 페어차일드코리아반도체 주식회사 Bipolar transistor having field limiting ring

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