JPH0120549B2 - - Google Patents
Info
- Publication number
- JPH0120549B2 JPH0120549B2 JP56041525A JP4152581A JPH0120549B2 JP H0120549 B2 JPH0120549 B2 JP H0120549B2 JP 56041525 A JP56041525 A JP 56041525A JP 4152581 A JP4152581 A JP 4152581A JP H0120549 B2 JPH0120549 B2 JP H0120549B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- electrode
- field
- guard
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】
本発明は高耐圧プレーナートランジスタの改良
に関する。従来の高耐圧プレーナートランジスタ
を第１図に示す。１はN+型のコレクタコンタク
ト領域、２はＮ型のコレクタ領域、３はＰ型のベ
ース領域、４はN+型のエミツタ領域、５はシリ
コン酸化膜であり、６はベース領域３を囲むＰ型
のガード領域、７はN+型のアニユラー領域、８
はコレクタ電極、９はベース電極、１０はエミツ
タ電極、１１はアニユラー領域７にオーミツク接
触し内側に拡がるシールド電極である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in high voltage planar transistors. A conventional high voltage planar transistor is shown in FIG. 1 is an N + type collector contact region, 2 is an N type collector region, 3 is a P type base region, 4 is an N + type emitter region, 5 is a silicon oxide film, and 6 surrounds the base region 3. P-type guard region, 7 is N + type annular region, 8
1 is a collector electrode, 9 is a base electrode, 10 is an emitter electrode, and 11 is a shield electrode that is in ohmic contact with the annular region 7 and extends inward.
斯るプレーナートランジスタではガード領域６
によりコレクタ接合が逆バイアスされたときに空
乏層が拡がり易いので高耐圧を得ることは良く知
られている。しかしながら斯るプレーナートラン
ジスタでも特に外側のガード領域６での空乏層が
十分に拡がらない場合があり表面電界降伏により
十分に高耐圧を得られないときがある。 In such a planar transistor, the guard region 6
It is well known that when the collector junction is reverse biased, the depletion layer expands easily, resulting in a high breakdown voltage. However, even in such a planar transistor, the depletion layer especially in the outer guard region 6 may not expand sufficiently, and a sufficiently high breakdown voltage may not be obtained due to surface electric field breakdown.
本発明は斯点に鑑みてなされ、従来の欠点を完
全に除去した高耐圧プレーナートランジスタを提
供するものであり、以下に第２図乃至第４図を参
照して本発明の一実施例を詳述する。 The present invention has been made in view of the above, and provides a high breakdown voltage planar transistor that completely eliminates the drawbacks of the conventional ones.One embodiment of the present invention will be described in detail below with reference to FIGS. 2 to 4. Describe.
本発明に依る高耐圧プレーナートランジスタは
第２図の如く、N+型のコレクタコンタクト領域
２０、Ｎ型エピタキシヤル層より成るコレクタ領
域２１、Ｐ型のベース領域２２、N+型のエミツ
タ領域２３、ベース領域２２を囲みベース領域２
２から一定の間隔で離間された複数本のＰ型ガー
ド領域２４、コレクタ領域２１端部に設けられた
N+型のアニユラー領域２５、夫々の領域にオー
ミツク接触したコレクタ電極２６ベース電極２７
およびエミツタ電極２８、ガード領域２４にオー
ミツク接触しコレクタ領域２１上のシリコン酸化
膜２９をベース領域２２の反対側に延在させたフ
イールド電極３０、アニユラー領域２５にオーミ
ツク接触し酸化膜２９上を内側に延在させたシー
ルド電極３１、少くともフイールド電極３０を被
覆する付着絶縁膜３２より構成される。 As shown in FIG. 2, the high breakdown voltage planar transistor according to the present invention includes an N + type collector contact region 20, a collector region 21 made of an N type epitaxial layer, a P type base region 22, an N + type emitter region 23, Base area 2 surrounding base area 22
2, a plurality of P-type guard regions 24 are provided at the end of the collector region 21 at regular intervals.
N + type annular region 25, collector electrode 26 in ohmic contact with each region, base electrode 27
and an emitter electrode 28, a field electrode 30 which is in ohmic contact with the guard region 24 and extends the silicon oxide film 29 on the collector region 21 to the opposite side of the base region 22, and a field electrode 30 which is in ohmic contact with the annular region 25 and has the oxide film 29 on the inside. It is composed of a shield electrode 31 extending over the area and an attached insulating film 32 covering at least the field electrode 30.
本発明の特徴はフイールド電極３０と付着絶縁
膜３２にある。即ち夫々のガード領域２４，２４
にオーミツク接触したフイールド電極３０，３０
はベース領域２２と反対側に夫々のガード領域２
４，２４のPN接合を越えて酸化膜２９上に延在
させ、斯る隣接したフイールド電極３０，３０を
絶縁するためにプラズマCVD法で形成したシリ
コン窒化膜の付着絶縁物３２でフイールド電極３
０，３０および必要であればベース電極２７エミ
ツタ電極２８を被覆する。 The feature of the present invention lies in the field electrode 30 and the attached insulating film 32. That is, the respective guard regions 24, 24
Field electrodes 30, 30 in ohmic contact with
has a respective guard region 2 on the opposite side to the base region 22.
The field electrode 3 is formed by an attached insulator 32 of a silicon nitride film formed by plasma CVD to extend over the oxide film 29 beyond the PN junctions 4 and 24 and insulate the adjacent field electrodes 30 and 30.
0, 30 and, if necessary, the base electrode 27 and the emitter electrode 28.
第１図および第２図に示す従来および本発明の
トランジスタではベース領域２２と内外のガード
領域２４，２４の間隔を約20μに設定すると、こ
の20μの間隔で約300vの耐圧を確保できる。一方
第４図に示すシリコン酸化膜上に設けた電極の間
隔Ｌと放電電圧Ｖの関係を示すグラフに依れば、
電極を露出した場合特性Ｂとなり、約6000Åのプ
ラズマCVD法によるシリコン窒化膜で電極を被
覆した場合特性Ａとなる。 In the conventional and inventive transistors shown in FIGS. 1 and 2, if the spacing between the base region 22 and the inner and outer guard regions 24, 24 is set to about 20 μ, a breakdown voltage of about 300 V can be secured with this 20 μ spacing. On the other hand, according to the graph shown in FIG. 4 showing the relationship between the distance L between the electrodes provided on the silicon oxide film and the discharge voltage V,
When the electrode is exposed, characteristic B is obtained, and when the electrode is covered with a silicon nitride film of about 6000 Å by plasma CVD method, characteristic A is obtained.
そこで本発明の如くガード領域２４にフイール
ド電極３０を形成すると、フイールド電極３０，
３０の間隔は高々30μ程度しか確保できない。斯
る30μのフイールド電極３０，３０の間隔では第
４図特性Ｂから放電電圧は約240vであり、明ら
かにガード領域２４自体にかかる耐圧より低いの
でフイールド電極３０，３０で放電し従来より耐
圧が低下する結果となる。しかし本発明の特徴と
する付着絶縁膜３２でフイールド電極を被覆する
と第４図特性Ａから放電電圧は約620vに向上で
き、明らかにガード領域２４自体にかかる耐圧以
上になる。この結果フイールド電極３０での放電
は完全に防止でき且つフイールド電極３０により
ガード領域２４のベース領域２２と反対側の端部
で発生し易い表面電界集中を除去して空乏層を拡
がり易くする。 Therefore, if the field electrode 30 is formed in the guard region 24 as in the present invention, the field electrode 30,
30 can only secure a spacing of about 30μ at most. With such a spacing of 30μ between the field electrodes 30, 30, the discharge voltage is about 240V from characteristic B in Figure 4, which is clearly lower than the withstand voltage applied to the guard region 24 itself, so the field electrodes 30, 30 discharge and the withstand voltage is higher than before. This results in a decrease. However, if the field electrode is covered with the deposited insulating film 32, which is a feature of the present invention, the discharge voltage can be increased to about 620 V from characteristic A in FIG. 4, which is clearly higher than the withstand voltage applied to the guard region 24 itself. As a result, discharge at the field electrode 30 can be completely prevented, and the surface electric field concentration that tends to occur at the end of the guard region 24 opposite to the base region 22 is removed by the field electrode 30, making it easier to spread the depletion layer.
斯る本発明の構造に依れば、第３図に示す耐圧
特性（VCBO―IC）から明らかな様に従来の構造で
発生していた表面電界降伏による点線で示す傾斜
部分を有するブレークダウン特性が、実線で示す
如く理想的なブレークダウン特性に改善される。
この結果3.6mm角のチツプサイズで第１図の従来
構造ではVCBOが900v以上のチツプの歩留が65％
であつたものが、本発明の構造では85％以上に向
上できた。 According to the structure of the present invention, as is clear from the withstand voltage characteristics (V CBO - I C ) shown in FIG. The breakdown characteristics are improved to ideal breakdown characteristics as shown by the solid line.
As a result, with a chip size of 3.6 mm square and the conventional structure shown in Figure 1, the yield of chips with V CBO of 900 V or more is 65%.
However, the structure of the present invention was able to improve this by more than 85%.
以上詳述した様に本発明に依れば付着絶縁膜３
２を設けることによつてフイールド電極３０，３
０間の放電電圧を大巾に向上させることによつて
従来では配置できなかつたフイールド電極３０，
３０の配置を実現し、表面電界降伏による耐圧不
良を大巾に改善する有益なものである。 As described in detail above, according to the present invention, the deposited insulating film 3
By providing field electrodes 30, 3
By greatly improving the discharge voltage between 0 and 0, the field electrode 30, which could not be arranged conventionally,
This arrangement is advantageous in that it greatly improves breakdown voltage defects due to surface electric field breakdown.
また斯る付着絶縁膜３２はトランジスタの表面
保護膜としても機能し、更には多層配線の絶縁膜
としても利用できる。 The attached insulating film 32 also functions as a surface protection film for transistors, and can also be used as an insulating film for multilayer wiring.
第１図は従来例を説明する断面図、第２図は本
発明を説明する断面図、第３図は本発明による高
耐圧プレーナートランジスタの耐圧特性を説明す
る特性図、第４図はシリコン酸化膜上に設けられ
た電極の間隔と放電電圧の特性を説明する特性図
である。
主な図番の説明 ２１はコレクタ領域、２２は
ベース領域、２３はエミツタ領域、２４はガード
領域、２９は酸化膜、３０はフイールド電極、３
２は付着絶縁膜である。
FIG. 1 is a cross-sectional view explaining a conventional example, FIG. 2 is a cross-sectional view explaining the present invention, FIG. 3 is a characteristic diagram explaining the breakdown voltage characteristics of a high voltage planar transistor according to the present invention, and FIG. 4 is a silicon oxide FIG. 2 is a characteristic diagram illustrating the characteristics of the distance between electrodes provided on the film and the discharge voltage. Explanation of main figure numbers 21 is the collector region, 22 is the base region, 23 is the emitter region, 24 is the guard region, 29 is the oxide film, 30 is the field electrode, 3
2 is an attached insulating film.
Claims (1)
域を備え該ベース領域を囲み前記コレクタ領域に
複数本のガード領域、該ガード領域を囲み前記コ
レクタ領域にアニユラ領域、該アニユラ領域にオ
ーミツク接触し且つ前記ベース領域の方向へ絶縁
膜上を延在されたシールド電極を設けた高耐圧プ
レーナートランジスタに於いて、 前記ガード領域に夫々オーミツク接触し且つ前
記ベース領域と反対側に前記ガード領域のPN接
合を越えて絶縁膜上を延在されたフイールド電極
を設け、前記フイールド電極を前記フイールド電
極間及び前記フイールド電極と前記シールド電極
との間の放電を防止するプラズマCVDによるシ
リコン窒化膜で覆い、且つ前記シリコン窒化膜は
前記フイールド電極間及び前記フイールド電極と
前記シールド電極との間の前記絶縁膜上をも覆う
ことを特徴とした高耐圧プレーナートランジス
タ。[Scope of Claims] 1. A collector region, a base region, and an emitter region, a plurality of guard regions surrounding the base region and the collector region, an annular region surrounding the guard region and the collector region, and an ohmic contact with the annular region. In a high voltage planar transistor provided with a shield electrode extending on an insulating film in the direction of the base region, the PN of the guard region is in ohmic contact with each of the guard regions and on the opposite side of the base region. providing a field electrode extending over the insulating film beyond the junction, covering the field electrode with a silicon nitride film formed by plasma CVD to prevent discharge between the field electrodes and between the field electrode and the shield electrode; The silicon nitride film also covers the insulating film between the field electrodes and between the field electrode and the shield electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4152581A JPS57155773A (en) | 1981-03-20 | 1981-03-20 | High pressure-resistant planar transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4152581A JPS57155773A (en) | 1981-03-20 | 1981-03-20 | High pressure-resistant planar transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57155773A JPS57155773A (en) | 1982-09-25 |
| JPH0120549B2 true JPH0120549B2 (en) | 1989-04-17 |
Family
ID=12610803
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4152581A Granted JPS57155773A (en) | 1981-03-20 | 1981-03-20 | High pressure-resistant planar transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57155773A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58114434A (en) * | 1981-12-28 | 1983-07-07 | Fujitsu Ltd | High withstand voltage semiconductor device |
| JPS60153164A (en) * | 1984-01-20 | 1985-08-12 | Nec Corp | Semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4968669A (en) * | 1972-11-06 | 1974-07-03 | ||
| JPS5269275A (en) * | 1975-12-08 | 1977-06-08 | Hitachi Ltd | Transistor |
| JPS5318382A (en) * | 1976-08-02 | 1978-02-20 | Rca Corp | Method of manufacturing crt screen structure |
-
1981
- 1981-03-20 JP JP4152581A patent/JPS57155773A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4968669A (en) * | 1972-11-06 | 1974-07-03 | ||
| JPS5269275A (en) * | 1975-12-08 | 1977-06-08 | Hitachi Ltd | Transistor |
| JPS5318382A (en) * | 1976-08-02 | 1978-02-20 | Rca Corp | Method of manufacturing crt screen structure |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57155773A (en) | 1982-09-25 |
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