JPH10135489A - Diode - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a planar diode that attain improvement in breakdown voltage. SOLUTION: The diode comprises an n<-> -type semiconductor region 11, a p-type semiconductor region 13, an n<+> -type semiconductor region 13a, an n-type semiconductor region 13b and a FLR(field limiting ring) region 14. The n<+> -type semiconductor region 13a is formed, so that the shortest distance between the FLR region 14 and the n<+> -type semiconductor region 13a will be longer than the shortest distance between the p-type semiconductor region 12 and the n<+> -type semiconductor region 13a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a diode with improved withstand voltage.

[0002]

BACKGROUND ART As shown in FIG. 1, N ^- planar exposed like islands on the main surface of the type semiconductor region (1) ^- P-type semiconductor region surrounded on type semiconductor region (1) (2) N Shaped diodes are known. In the diode 1, N ^-
In order to reduce the internal resistance P-type semiconductor region (2) and the opposite main surface during device operation type semiconductor region (1) (ON resistance), N ^- type semiconductor region (1) of the impurity concentration than A high N ^{+ type} semiconductor region (3) is formed. Also, N ⁻
In order to improve the breakdown voltage on the outer peripheral side of the PN junction (4) formed at the interface between the P-type semiconductor region (1) and the P-type semiconductor region (2), the outer periphery of the P-type semiconductor region (2) is surrounded. P
Limiting ring composed of a semiconductor region, that is, FLR (Field Limiting Ri).
ng) Region (5) is formed. This FLR region (5) is sometimes called a guard ring, and contributes to the improvement of the breakdown voltage of the planar structure. (6) is an anode electrode, and (7) is a cathode electrode.

[0003]

However, even if the FLR region (5) is simply formed as in the prior art, a sufficient withstand voltage improvement effect has not been obtained. The reason for this is that the depletion layer extending from the FLR region (5) reaches (reach-through) the N ⁺ semiconductor region (3), the expansion of the depletion layer is limited, and the electric field relaxation effect of the depletion layer is not sufficiently exhibited. is there.

Accordingly, an object of the present invention is to provide a planar diode capable of improving the breakdown voltage.

[0005]

According to the present invention, there is provided a semiconductor device, comprising: a first semiconductor region of a first conductivity type in a semiconductor substrate; and a side surface and a bottom surface surrounded by the first semiconductor region. A second semiconductor region of a second conductivity type, which is a conductivity type opposite to the first conductivity type, and the first semiconductor region and the second semiconductor region are in contact with each other on the opposite side, and the first semiconductor region is in contact with the first semiconductor region. A third semiconductor region of the first conductivity type having a higher impurity concentration than the semiconductor region; and a field limiting ring region of the second conductivity type having a side surface and a bottom surface surrounded by the first semiconductor region. A first electrode is connected to the second semiconductor region on one main surface of the semiconductor substrate, and a second electrode is connected to the third semiconductor region on the other main surface of the semiconductor substrate. The third half. A body region having a first portion disposed below the second semiconductor region and a second portion disposed below the field limiting ring region; An interface in contact with the first semiconductor region is located closer to one main surface of the semiconductor substrate than an interface in which the second portion and the first semiconductor region are in contact with each other. The present invention relates to a diode, wherein a shortest distance between the third semiconductor region and the third semiconductor region is longer than a shortest distance between the second semiconductor region and the third semiconductor region. In addition, as shown in claim 2, when viewed in plan, the first
Between the outermost peripheral edge of the portion where the first electrode is connected to the second semiconductor region and the innermost peripheral edge of the field limiting ring region, the outermost peripheral edge of the first portion of the third semiconductor region is Preferably, the first portion is formed to be located.

[0006]

According to the present invention, the shortest distance between the field limiting ring region and the third semiconductor region is longer than the shortest distance in the conventional diode. The occurrence of a state in which the depletion layer extending from the semiconductor region to the field limiting ring region reaches the third semiconductor region can be limited, and the withstand voltage can be improved. Further, when the first portion of the third semiconductor region is formed as in claim 2, the internal resistance during the operation of the diode can be kept low to improve the breakdown voltage.

[0007]

First Embodiment Next, a diode according to a first embodiment of the present invention will be described with reference to FIG. The diode of FIG. 2 includes an N ^{− type} semiconductor region (11) as a first semiconductor region and an N ^{− type} semiconductor region (11) as in FIG.
A P-type semiconductor region of the second semiconductor region (12) side surface and the bottom surface is surrounded, N ^- type semiconductor region (11)
An N ^{+ -type} semiconductor region (13a) and an N-type semiconductor region (13b) as a third semiconductor region in contact with a main surface on a side opposite to a side where the P-type semiconductor region (12) is formed; comprising a type semiconductor region (11) made of P-type semiconductor region surrounding via the field-limiting ring region (FLR region) (14) and the silicon semiconductor substrate (15) having ^- periphery of N (12) . An insulating film (16) is provided on one main surface, that is, an upper surface (15a) of the semiconductor substrate (15), and an anode electrode (18) is connected to the P-type semiconductor region (12) through an opening (17) provided therein. )
Is connected. Further, a cathode electrode (20) is connected to the other main surface, that is, the lower surface (19) of the semiconductor substrate (15).

[0008] N ^- type semiconductor region (11) and the P-type semiconductor region (12) is formed on substantially the same as FIG. 1,
The N ^{+ type} semiconductor region (13a) and the N type semiconductor region (13
b) and the FLR region (14) are different from FIG. Hereinafter, these will be described in detail. The P-type semiconductor region (12) is N ⁻
The bottom and side surfaces are surrounded by the N ⁻ -type semiconductor region (11) in the N-type semiconductor region (11) by impurity diffusion, and a PN junction (2
1) has occurred. The upper surface of the P-type semiconductor region (12)
It is exposed from the upper surface of the semiconductor substrate (15).

[0009] FLR region (14), N in the same diffusion process as P-type semiconductor region (12) ^- is formed by impurity diffusion in a type semiconductor region (11), the bottom and side surfaces are N ^- form It is surrounded by the semiconductor region (11). The FLR region (14) is a P-type semiconductor region (12) in plan view.
Are annularly surrounded via an N ^{− type} semiconductor region (11), and the upper surface thereof is exposed from the upper surface of the semiconductor substrate (15).

The insulating film (16) formed on the upper surface of the semiconductor substrate (15) is made of, for example, a silicon oxide film formed by thermal oxidation and covers the upper surface of the FLR region (14). Opening (17) formed in insulating film (16)
Is located on the upper surface of the P-type semiconductor region (12), but its diameter (opening width) is shorter than the width of the exposed upper surface of the P-type semiconductor region (12). (1
The inner edge of 7) is located inside the outer edge of the P-type semiconductor region (12). Therefore, the anode electrode (18) is connected to the center of the upper surface of the P-type semiconductor region (12) inside the opening (17).

[0011] ^{N +} type semiconductor region (13a) and the N-type semiconductor region (13b) is, N ^- is formed by impurity diffusion in the form semiconductor regions (11), ^{N +} type semiconductor region (13
a) corresponds to the first portion of the third semiconductor region of the present invention and is disposed below the P-type semiconductor region (12);
The N-type semiconductor region (13b) corresponds to the second portion of the third semiconductor region of the present invention, and is disposed outside the N ^{+ -type} semiconductor region (13a) and below the FLR region (14). Hereinafter, the N ^{+ type} semiconductor region (13a) and the N type semiconductor region (13b) may be collectively referred to as a third semiconductor region (13) for convenience. To describe the third semiconductor region (13) in more detail, the outermost peripheral edge of the N ^{+ -type} semiconductor region (13a) is such that the anode electrode (18) is in contact with the P-type semiconductor region (12) in plan view. The portion is formed between the outermost peripheral edge of the portion and the innermost peripheral edge of the FLR region (14). The N type semiconductor region (13b) is adjacent to and surrounds the outer peripheral side of the N ^{+ type} semiconductor region (13a).
The entire LR region (14) is included.

Further, the N ^{+ type} semiconductor region (13a) and N ⁻
The interface where the N-type semiconductor region (11) is in contact with the N-type semiconductor region (11b) is located closer to the upper surface of the semiconductor substrate (15) than the interface where the N-type semiconductor region (13b) and the N ⁻ -type semiconductor region (11) are in contact. Therefore, the third semiconductor region (13) and the FLR region (14)
The shortest distance _{L 2} between is longer than the shortest distance _{L 1} between the P-type semiconductor region (12) and the third semiconductor region (13). The third semiconductor region (13) is formed by first diffusing the N ^{+ type} semiconductor region (13a) relatively deeply into the N ^{− type} semiconductor region (11), and then forming the N type semiconductor region (13).
b) can be obtained by forming a shallower diffusion. An example of the impurity concentration of each semiconductor region is as follows. N ^- type semiconductor region ^{11: 1 × 10 14 ~5 ×} 10 14
cm ⁻³ P-type semiconductor region 12: 1 × 10 ^{18 to} 5 × 10 ¹⁸ c
m ⁻³ FLR region 14: 1 × 10 ^{18 to} 5 × 10 ¹⁸ cm
^-3 N ⁺ type semiconductor region ^{13a: 1 × 10 20 ~5 ×} 10
²⁰ cm ⁻³ N-type semiconductor region 13b: 1 × 10 ^{20 to} 3 × 10 ²⁰
cm ^-3

[0013] P-type semiconductor region 12 and the N diode of Figure 2 ^- the voltage PN junction 21 in a reverse bias to the direction formed between the type semiconductor region 11 is applied, PN junction 2
From 1 the depletion layer expands. This depletion layer is formed by the P-type semiconductor 12
Since the impurity concentration of the N ^{− type} semiconductor region 11 is lower than that of, the N ^{− type} semiconductor region 11 mainly spreads to the N ^{− type} semiconductor region 11 side. As in the diode of FIG. 1, when the applied voltage increases, the depletion layer also spreads from the PN junction 22 formed between the FLR region 14 and the N ^{− type} semiconductor region 11. But F
Since the third semiconductor region 13 is formed below the LR region 14 so as to be deviated downward, the shortest distance between the FLR region 14 and the third semiconductor region 13 is longer than before, and the FLR region It is difficult for the depletion layer extending downward from 14 to reach third semiconductor region 13. Therefore, the depletion layer extending from the main PN junction (21) forms an N ^{+ type} semiconductor region (13
Since the depletion layer extending from the FLR region (14) side can reach the N ^{− type} semiconductor region (11) on the side of the N ^{+ type} semiconductor region (13a) even after reaching the a), the semiconductor substrate 15 The extension of the depletion layer on the surface is not restricted, and a high breakdown voltage is satisfactorily achieved. The P-type semiconductor region (1
Under 2), since the N ^{+ type} semiconductor regions (13a) are formed at relatively small intervals, the shortest distance between the P ^{+ type} semiconductor region (12) and the N ^{+ type} semiconductor region (13a) is the same as the conventional one. Yes, the operating resistance of the diode can be maintained at a sufficiently low level.

[0014]

Second Embodiment Next, a diode according to a second embodiment will be described with reference to FIG. However, in FIG. 3, substantially the same parts as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted. The diode of FIG. 3 has substantially the same configuration as that of FIG. 2 except that the N ^{+ type} semiconductor region (13a) of the diode of FIG. 2 is formed by a buried layer. Diode of Figure 3, as a starting base material of N-type semiconductor substrate corresponding to the N-type semiconductor region (13b), the main surface of the one selectively introducing an N-type impurity N ⁺ type semiconductor region (13a forming a region corresponding to the lower portion of the), then N on one main surface of the N-type semiconductor substrate by a known epitaxial growth method ^- to form a type semiconductor region (11). The epitaxial previously introduced into the N-type semiconductor substrate during the growth impurities the N ^- and out-diffusion in type semiconductor region, N ^- lower type semiconductor region (11) above the N ⁺ -type semiconductor region (13a) An upper portion of the N ^{+ type} semiconductor region (13a) connected to the portion is formed. As a result,
A third semiconductor region (13) in which the upper surface of the N ^{+ type} semiconductor region (13a) is deviated upward from the upper surface of the N type semiconductor region (13b) is obtained. P-type semiconductor region (12) and F
The LR region (14) is formed by diffusing impurities into the N ^{− type} semiconductor region (11) as in FIG. The diode of FIG. 3 has a structure in which the N-type semiconductor region (13b) is exposed on the entire lower surface of the semiconductor substrate (15), but the FLR region (14) and the third semiconductor region ( 13) is the shortest distance between the P-type semiconductor region (12) and the third
Is longer than the shortest distance to the semiconductor region (13), and the internal resistance during operation can be kept low to improve the breakdown voltage. An example of the impurity concentration of each semiconductor region is as follows. N ^- type semiconductor region ^{11: 1 × 10 14 ~5 ×} 10 14
cm ⁻³ P-type semiconductor region 12: 1 × 10 ^{18 to} 5 × 10 ¹⁸ c
m ⁻³ FLR region 14: 1 × 10 ^{18 to} 5 × 10 ¹⁸ cm
^{-3N + type} semiconductor region 13a: 1 * 10 < ^{18 > to} 5 * 10
¹⁸ cm ⁻³ N-type semiconductor region 13b: 1 × 10 ^{18 to} 3 × 10 ¹⁸
cm ^-3

[0015]

[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) In the embodiment, the impurity concentration and the diffusion depth of the FLR region (14) are made the same as those of the second semiconductor region (12), but the impurity concentration of the FLR region (14) is made second semiconductor region. The diffusion depth of the FLR region (14) is made deeper than that of the second semiconductor region (12) by making it smaller than that of (12) (for example, 1 × 10 ^{17 to} 5 × 10 ¹⁷ cm ⁻³ ). May be. In this case, the spread of the depletion layer from the FLR region (14) becomes good, and the cover of the PN junction (21) is further reduced, which is further advantageous for improving the breakdown voltage. (2) FLR region (14) is replaced with second semiconductor region (12)
May be formed so as to surround. (3) The first portion (13) of the third semiconductor region (13)
a) and the second portion (13b) may have the same impurity concentration.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a conventional diode.

FIG. 2 is a sectional view showing a diode according to the first embodiment of the present invention.

FIG. 3 is a sectional view showing a diode according to a second embodiment of the present invention.

[Explanation of symbols]

 11 first semiconductor region 12 second semiconductor region 13a first portion of third semiconductor region 13b second portion of third semiconductor region 14 FLR region

Claims (2)

[Claims] 1. A first semiconductor region of a first conductivity type in a semiconductor substrate, and a second semiconductor region having a side opposite to the first conductivity type and a side surface and a bottom surface surrounded by the first semiconductor region. And a second semiconductor region of the first conductivity type, which is in contact with the second semiconductor region on the opposite side to the first semiconductor region and the second semiconductor region, and has a higher impurity concentration than the first semiconductor region. 3
And a field limiting ring region of the second conductivity type, the side surface and the bottom surface of which are surrounded by the first semiconductor region, wherein the second conductive type field limiting ring region is provided on one main surface of the semiconductor substrate. In a diode in which a first electrode is connected to a semiconductor region and a second electrode is connected to the third semiconductor region on the other main surface of the semiconductor substrate, the third semiconductor region is connected to the second electrode. A first portion disposed below the semiconductor region; and a second portion disposed below the field limiting ring region, wherein the first portion and the first semiconductor region are separated from each other. The contacting interface is located closer to one main surface of the semiconductor substrate than the interface where the second portion contacts the first semiconductor region, and the field limiting ring region and the third semiconductor Diode, wherein a shortest distance between frequency is longer than the shortest distance between the third semiconductor region and the second semiconductor region. 2. A planar view between an outermost peripheral edge of a portion where the first electrode is connected to the second semiconductor region and an innermost peripheral edge of the field limiting ring region. 2. The diode according to claim 1, wherein the first portion is formed such that an outermost peripheral edge of the first portion of the third semiconductor region is located. 3.