JP3329376B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a transistor having an improved withstand voltage.

[0002]

2. Description of the Related Art As shown in FIG. 1, a power transistor in which an emitter region 2 surrounded by a base region 1 is formed in a lattice or island shape is known. In the transistor of FIG. 1, in order to improve the breakdown voltage on the outer peripheral side of the PN junction 5 between the N-type collector region 3 and the P + -type base region 1 adjacent to the N + type collector region 4, Field limiting ring or FL consisting of the same P @ + type semiconductor region as base region 1 so as to surround the outer periphery of FL1.
An R (Field Limiting Ring) region 6 is formed. The FLR region 6 is sometimes called a guard ring, and contributes to the improvement of the breakdown voltage of the planar structure. In addition, 7 is a base electrode, 8 is an emitter electrode, and 9 is a collector electrode.

[0003]

However, as described above, F
Even if the LR region 6 was formed, a sufficient withstand voltage improvement effect could not be obtained. The reason for this is that the depletion layer extending from the FLR region 6 reaches the N + -type collector region 4 (reach-through), the extension of the depletion layer is restricted, and the electric field relaxation effect by the depletion layer is not sufficiently exhibited.

Accordingly, an object of the present invention is to provide a semiconductor device such as a transistor or a diode which can improve the breakdown voltage.

[0005]

SUMMARY OF THE INVENTION In order to solve the above problems and achieve the above object, the present invention provides a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type opposite to the first conductivity type. A semiconductor substrate having a second semiconductor region, a first conductivity type third semiconductor region, and a second conductivity type field limiting ring region, and at least first and second electrodes; The first semiconductor region is arranged such that a part thereof is exposed on one main surface of the semiconductor base, and the second semiconductor region is arranged such that a part thereof is exposed on one main surface of the semiconductor base. The third semiconductor region is disposed in an island shape in the first semiconductor region, the third semiconductor region has an impurity concentration higher than an impurity concentration of the first semiconductor region, and the first semiconductor region and the semiconductor substrate The first electrode disposed between the first main electrode and the other main surface of the first electrode One main surface of the semiconductor substrate is electrically connected to the second semiconductor region, and the second electrode is disposed on the other main surface of the semiconductor substrate and is electrically connected to the third semiconductor region. Connected, the field limiting ring region is arranged on one main surface of the semiconductor substrate so as to surround the second semiconductor region via the first semiconductor region, and is connected to the first semiconductor region. In a semiconductor device formed in an island shape therein, the second semiconductor region is formed by a first portion formed to have a first depth with reference to one main surface of the semiconductor base and the semiconductor portion. A second portion formed to have a second depth greater than the first depth with respect to one main surface of the base, and disposed adjacent to the outer periphery of the first portion ; The third semiconductor region is Viewed in the plane manner is disposed inside the second portion of said second semiconductor regions, the shortest distance between the second portion and the third semiconductor region, the
Set longer than the shortest distance between the portion 1 and the third semiconductor region.
Those related to the semiconductor device which is characterized that you are constant.

Further, it is desirable that the impurity concentration of the second portion as shown in claim 2 lower than the first portion.
Further, a fourth semiconductor region can be provided between the third semiconductor region and the other main surface of the base, as described in claim 3 . Further, it is possible to provide a fourth semiconductor region囲Ri of the third semiconductor region, as shown in claim 4. Also,
It is desirable to configure the transistor as described in claim 5 .

[0007]

According to the first to fourth aspects of the present invention, since the second portion which is the outer peripheral portion of the second semiconductor region is formed deeper than the first portion, the radius of curvature of the corner portion is reduced. The electric field concentration can be reduced. Also,
Since the third semiconductor region is not opposed to the second portion of the second semiconductor region, the depletion layer can be favorably expanded under the second portion, and the withstand voltage can be improved. In addition,
If low impurity concentration of the second part by the invention of claim 2, it is possible to widen the depletion layer it is possible to relax the electric field concentrated around the side of the second semiconductor region well. Also, in the transistor according to the fifth aspect of the present invention,
The same effect as that of the invention can be obtained.

[0008]

Embodiments and Examples Next, embodiments and examples of the present invention will be described with reference to FIGS.

[0009]

First Embodiment A plate-like silicon semiconductor substrate 10 for forming a transistor according to a first embodiment shown in FIGS. 2 and 3 has a base region 11 made of a P @ + type semiconductor region,
An emitter region 12 composed of a + type semiconductor region, a first collector region 13 composed of an N type semiconductor region, and a second collector region 14 composed of an N + type semiconductor region having a higher impurity concentration than the first collector region 13. And an FLR (field limiting ring) region 15 made of the same P + -type semiconductor region as the base region 11. An insulating film 17 is provided on one main surface, that is, an upper surface 16 of the semiconductor substrate 10, a base electrode 18 is connected to the base region 11 through an opening 17a provided here, and an emitter region is connected through an opening 17b. 12 is connected to an emitter electrode 19. A collector electrode 21 is provided on the other main surface, that is, the lower surface 20 of the semiconductor substrate 10, and is connected to the first and second collector regions 13 and 14. The relationship between the first to third semiconductor regions in the claims of the present application and FIG. 2 will be described. The first collector region 13 corresponds to the first semiconductor region, and the base region 11 corresponds to the second semiconductor region. The second collector region 14 corresponds to the third semiconductor region.

[0010] The base region 11 and the first and second collector regions 13 and 14 of the transistor of this embodiment of FIG.
The R region 15 is different from the conventional transistor of FIG. The P @ + -type base region 11 is formed in an island shape in the first collector region 13 by well-known impurity diffusion, and the bottom and side surfaces thereof are surrounded by the first collector region 13, and a PN junction is formed therebetween. Has occurred. This base area 1
1 is a first part 11a and a second part 11b according to the present invention.
And The first portion 11a has a relatively shallow first depth (about 40
μm), and the second portion 11 b
A second depth (approximately 50
μm) and is disposed so as to surround the outer periphery of the first portion 11a. The first portion 11a is a region in which an N-type impurity is diffused from the one main surface 16 side of the base 10, and has an impurity concentration of about 1 × 10 ¹⁶ cm ⁻³ . The second portion 11b is also a region in which an N-type impurity is diffused from the one main surface 16 of the base 10, and is approximately 0.2 μm lower than the first portion 11a.
It has an impurity concentration of 8 × 10 ¹⁶ cm ⁻³ . Second part 1
Since 1b is formed by deep diffusion, the radius of curvature of the curved surface 30 at the corner between the side surface and the bottom surface is increased, and a structure in which electric field concentration hardly occurs is obtained. The second portion 11b is F
It is formed at about the same depth by diffusion at the same time as the LR region 15. The emitter region 12 is a base region 11 when viewed in plan.
It is formed in a lattice by impurity diffusion. As a result,
The base region 11 is exposed in an island shape on the upper surface 16 of the semiconductor substrate 10. That is, the emitter region 12 and the base region 1
1 has a structure called a so-called mesh emitter or base island. FIG. 2 shows only four emitter regions 12 constituting a grating in principle,
In fact, the grid has more eyes.

The first collector region 13 surrounds the base region 11 and the FLR region 15 as in FIG.
Below the LR region 15, it is formed so as to reach the collector electrode 21. The impurity concentration (1 × 10 ¹³ cm ⁻³ ) of the first collector region 13 is higher than that of the first collector region 13 (5 × 10 ¹³ cm ⁻³ ).
Second collector region 14 having a thickness of about 5 × 10 ²⁰ cm ⁻³ )
Are not formed in the entire region of the lower surface 20 of the semiconductor substrate 10 but are formed in a range included in the first portion 11a of the base region 11 in plan view. The second collector region 13 is formed by diffusing impurities from the lower surface 20.

The second collector region 14 will be described in more detail.
1 is not formed below at least the second portion 11 b and the FLR region 15. This second collector region 1
The outermost peripheral edge of No. 4 is disposed inside the innermost peripheral edge of the second portion 11b of the base region 11 in a plan view. Accordingly, the shortest distance L2 between the second portion 11b of the base region 11 and the second collector region 14 is equal to the first distance L2 of the base region 11.
Shortest distance L between the portion 11a and the second collector region 14
1 and the shortest distance L3 between the FLR region 15 and the second collector region 14 is longer than the shortest distance L1 between the first portion 11a of the base region 11 and the second collector region 14. In this embodiment, the second portion 1 of the base region 11
The distance D1 between the imaginary line 31 extending perpendicularly to the lower surface 20 of the base 10 and the second collector region 14 through the innermost point of the deepest region of the base region 1b is the first portion 1 of the base region 11.
It is determined to be at least twice the shortest distance L1 between 1a and the second collector region 14. To illustrate these dimensions,
1 is about 70 μm and D1 is about 150 μm.

[0013] The two FLR regions 15 correspond to the base region 11.
Is formed in an annular shape when viewed in plan so as to surround the outer periphery of the device at a distance. The FLR region 15 is surrounded by the first collector region 13 except for the surface, and the surface is covered with an insulating film 17. FLR formed by diffusion
The impurity concentration of the region 15 is the second portion 1 of the base region 11.
About the same as the impurity concentration of 1b and about 0.8 × 10 ¹⁶ cm
It is ^-3 . The diffusion depth of the FLR region 15 is the same as that of the second portion 11b of the base region 11, and the first portion 1
It is shallower than 1a. Note that a PN junction 23 is also formed between the P + -type FLR region 15 and the N-type first collector region 13.

When a voltage is applied to the base electrode 18 and the collector electrode 21 in a direction to reverse bias the PN junction 22 formed between the base region 11 and the first collector region 13 of the transistor in FIG. A depletion layer extends from the junction 22. Since the first collector region 13 has a lower impurity concentration than the base region 11, the depletion layer mainly spreads to the first collector region 13 side. Also, as in the case of the transistor in FIG.
P formed between region 15 and first collector region 13
The depletion layer also extends from N junction 23. However, since the second collector region 14 is not formed under the FLR region 15 and the shortest distance L3 between the FLR region 15 and the second collector region 14 is longer than in the prior art, the FLR region 15 The depletion layer extending downward from the second collector region 14
, And the spread of the depletion layer on the surface of the semiconductor substrate 10 is not limited. Further, since the depletion layer from the FLR region 15 hardly reaches the second collector region 14 and the collector electrode 21, the impurity concentration of the FLR region 15 can be set lower than that of the transistor of FIG. The depletion layer based on satisfactorily spreads to improve the breakdown voltage. Further, in the present embodiment, the second portion 11b on the outer peripheral side of the base region 11 where the electric field concentration easily occurs is formed deep by diffusion, and the radius of curvature of the curved surface 30 at the corner of the second portion 11b is increased. That this second part 11b
That the second portion 1 has a low impurity concentration.
Based on the fact that the second collector region 14 is not formed below 1b and that D1> 2L1, the depletion layer is easily spread on the outer peripheral side of the base region 11 and the spread is less restricted. As a result, the electric field concentration in the second portion 11b on the outer peripheral edge of the base region 11 is favorably alleviated, and the breakdown voltage is improved. Further, since the second collector region 14 is formed so as to include a region connected to the first portion 11a of the base electrode 18 of the base region 11 in plan view, the normal transistor of this embodiment is used. The operation is substantially the same as the conventional transistor of FIG.

[0015]

Second Embodiment Next, a transistor according to a second embodiment will be described with reference to FIG. However, FIG. 4 and FIG.
In FIG. 6 and FIG. 6, parts substantially the same as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted. The transistor of FIG. 4 has substantially the same configuration as that of FIG. 2 except that a third collector region 40 as a fourth semiconductor region is added to the transistor of FIG. The third collector region 40 in FIG. 4 is an N-type semiconductor region containing, for example, antimony having a low diffusion constant as an impurity and having an impurity concentration of about 1 to 3 × 10 ¹⁸ cm ⁻³ , and is a substrate region for epitaxial growth. Therefore, the entire lower surface of the third collector region 40 is the lower surface 20 of the semiconductor substrate 10. The second collector region 14 is formed so as to be sandwiched between the first and third collector regions 13 and 40, that is, buried.
As in the embodiment, the first region 11a of the base region 11 is opposed to the first region 11a. The second collector region 14 is an N + -type semiconductor region obtained by diffusing, for example, phosphorus with a higher diffusion constant than the impurity of the third collector region 40, and the first and third collector regions 13, 14. It has an impurity concentration of about 1 × 10 ¹⁹ cm ⁻³ higher than 40. The second collector region 14 is obtained by selectively diffusing, for example, phosphorus into the third collector region 40, forming an epitaxial growth layer of an N − type semiconductor thereon, and performing heat treatment. The impurity concentration of the first collector region 13 in FIG. 4 is, for example, 5 × 10 ¹⁸ cm ⁻³ . Also in the transistor of FIG. 4, the relationship between the second collector region 14, the base region 11, and the FLR region 15,
Since the configuration of the base region 11 is the same as that of the transistor of FIG. 2, the same effects as those of the first embodiment can be obtained by the second embodiment.

[0016]

Third Embodiment A transistor according to a third embodiment shown in FIG. 5 is different from the transistor according to the first embodiment in FIG. 2 in that an N @ + -type third collector region 50a as a fourth semiconductor region is added. Others are the same as those of FIG. The third collector region 50 a is arranged on the lower surface 20 of the base 10 so as to surround the second collector region 14, and is connected to the collector electrode 21 together with the second collector region 14. The third collector region 50a is the second collector region 14
This region has substantially the same impurity concentration as that of the first region, and is a region where the impurity is diffused sufficiently shallower than the second collector region 14 from the lower surface 20 side. As a result, the base region 11 and the FLR region 1
The distance between 5 and third collector region 50a is sufficiently large. Therefore, the third collector region 50a does not hinder the spread of the depletion layer. Since the configuration of the base region 11 of the third embodiment is the same as that of the first embodiment, the same effect as that of the first embodiment can be obtained by the third embodiment.

[0017]

Fourth Embodiment The diode shown in the fourth embodiment of FIG. 6 is different from the transistor of the first embodiment in that the emitter region 12
And the emitter electrode 19 is removed, and the anode electrode (first electrode) 61 and the cathode electrode (second electrode) 62 are provided. In FIG. 6, the same portions as those in FIG. 2 are denoted by the same reference numerals, and portions related to the difference between the transistor and the diode are denoted by dashes. Therefore, the regions 11 ', 11a', 11b ', 13', 1
Reference numeral 4 'corresponds to the regions 11, 11a, 11b, 13, and 14 in FIG. 1 and is formed in the same manner as in FIG. Anode electrode 6
1 is connected to the P @ + type region 11 '. Cathode electrode 62 is connected to N-type region 13 'and N + -type region 14' on lower surface 20 of substrate 10.

In the diode shown in FIG.
Since the first and second portions 11a 'and 11b' are formed in the same manner as in FIG. 2 and the N @ + type region 14 'is formed in the same manner as in FIG. 2, the same effect as in the first embodiment is obtained. Is obtained.

[0019]

[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) Also in the diode of FIG. 6, a diode corresponding to the third collector region 50 of FIG. 4 or a diode corresponding to the third collector region 50a of FIG. 5 can be provided at a position indicated by a broken line in FIG. . (2) The FLR region 15 can be formed simultaneously with the first portion 11a or 11a 'of the region 11 or 11', and can have the same depth and the same impurity concentration. However,
In order to reduce the electric field concentration, it is desirable to form the FLR region 15 as shown in FIGS. (3) Electrode 18 or 61 in region 11 or 11 '
May be higher than the impurity concentration of the portion to which is connected, that is, the surface portion of the region 11 or 11 ', than the impurity concentration of the other portion (lower portion) of the region 11 or 11'. As a result, the electrodes 18 or 61 make good ohmic contact.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a conventional transistor.

FIG. 2 is a sectional view showing a transistor according to an example of the present invention.

FIG. 3 is a plan view of the semiconductor substrate of FIG. 2;

FIG. 4 is a sectional view showing a transistor according to a second embodiment.

FIG. 5 is a sectional view showing a transistor according to a third embodiment.

FIG. 6 is a sectional view showing a diode according to a fourth embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Base area 11a, 11b 1st and 2nd part 12 Emitter area 13 1st collector area 14 2nd collector area 15 FLR area

Claims (5)

(57) [Claims] At least a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type opposite to the first conductivity type, a third semiconductor region of a first conductivity type, and a second conductivity region A semiconductor substrate having a mold field limiting ring region; and at least first and second electrodes, wherein the first semiconductor region is partially exposed on one main surface of the semiconductor substrate. The second semiconductor region is arranged in an island shape in the first semiconductor region so that a part thereof is exposed to one main surface of the semiconductor base; A region having an impurity concentration higher than an impurity concentration of the first semiconductor region and disposed between the first semiconductor region and the other main surface of the semiconductor base; The second semiconductor region is provided on one main surface of the base. The second electrode is disposed on the other main surface of the semiconductor substrate and is electrically connected to the third semiconductor region; and the field limiting ring region is electrically connected to the semiconductor substrate. A semiconductor device arranged on one main surface of the first semiconductor region so as to surround the second semiconductor region with the first semiconductor region interposed therebetween and formed in an island shape in the first semiconductor region; A first portion formed to have a first depth with reference to one main surface of the semiconductor substrate, and a first portion formed with reference to one main surface of the semiconductor substrate. A second portion formed so as to have a second depth deeper than the second portion and disposed adjacent to the outer periphery of the first portion ; 2 of the second portion of the semiconductor region Disposed, said second portion of said second semiconductor region and the third conductive
The shortest distance from the body region is the first distance of the second semiconductor region.
Longer than the shortest distance between the portion 1 and the third semiconductor region
A semiconductor device characterized by being set well . 2. The semiconductor device according to claim 1, wherein said second portion of said second semiconductor region has an average impurity concentration lower than that of said first portion. . 3. A semiconductor device according to claim 1, further comprising a fourth semiconductor region of a first conductivity type between the third semiconductor region and the other main surface of the semiconductor base, wherein the second electrode is provided in the fourth semiconductor region. 3. The semiconductor device according to claim 1, wherein the semiconductor device is connected to a semiconductor region. 4. The semiconductor device according to claim 1, further comprising a fourth semiconductor region of a first conductivity type, wherein the fourth semiconductor region is arranged on the other main surface of the semiconductor substrate so as to surround the third semiconductor region, The shortest distance from one main surface of the semiconductor substrate to the fourth semiconductor region is longer than the shortest distance from the one main surface to the third semiconductor region. 4. The semiconductor device according to 3. 5. An emitter region, a base region, a first collector region, a second collector region having an impurity concentration higher than that of the first collector region, and a field limiting ring region. A first base region, a first base region, and a collector electrode, wherein the first collector region is disposed such that a part thereof is exposed to one main surface of the first base region; A base region is arranged in the first collector region in an island shape and is exposed on one main surface of the semiconductor substrate. The emitter region is arranged in the base region in an island shape and is formed in the semiconductor substrate. Exposed on one main surface, wherein the second collector region is disposed between the first collector region and the other main surface of the semiconductor substrate; A region is arranged on one main surface of the semiconductor substrate so as to surround the base region via the first collector region; the emitter electrode is electrically connected to the emitter region; and the base electrode is connected to the base. A semiconductor device comprising a transistor electrically connected to a region, wherein the collector electrode is disposed on the other main surface of the semiconductor substrate and is electrically connected to the second collector electrode; A first portion formed to have a first depth with reference to one main surface of the base; and a second depth deeper than the first depth with reference to one main surface of the semiconductor base. and a second portion disposed adjacent to the outer periphery of the formed且previous SL first portion to have is, the first of said second collector region in plan view the base region Is arranged in the inner part, the base - the second portion of the scan area and the second collector
The shortest distance to the region is the first portion of the base region
Longer than the shortest distance between the second collector region and
A semiconductor device characterized by being performed .