JPH11204804A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-withstand voltage diode having a high reverse recovery characteristic and high surge current resistance at a low cost. SOLUTION: On one surface layer of an n<-> substrate 1, a high-concn. p<+> layer 2 is formed by an ion implanting and thermal diffusion, a trench 3 is formed into the p<+> layer 2, a bottom face 4 of the trench 3 is at a depth not reaching a p-n junction boundary face 5 defined by the substrate 1 and p<+> layer 2 and the top end of a depletion layer extending from the p-n junction boundary face 5 does not reach the bottom face 4 of the trench 3. On the surface of the p<+> layer 2, side face B and bottom face 4, a metal electrode to be an anode electrode 9 is formed. On the surface of the n<+> layer 11 a metal electrode to be a cathode electrode 12 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device such as a mesa-type or planar-type diode.

[0002]

2. Description of the Related Art With the development of devices such as insulated gate bipolar transistors (IGBTs) that enable high-speed switching and obtain a low saturation voltage, a diode such as a freewheel diode (FWD) is used in combination with such devices. Improvements in characteristics are also being pursued.

FIG. 4 is a structural view of a main part of a conventional diode.
FIG. 2A is a plan view, and FIG. 2B is XX in FIG.
It is sectional drawing cut | disconnected by the line. In addition, FIG. 4B also shows tip portions 31 and 32 of the depletion layer for convenience of explanation. In FIG. 4, n ^- on one surface layer of the substrate 1, p ⁺ layer 22 and p ^-
A p layer composed of the layer 27 is formed, and n ⁺
Layer 22 is formed. Usually, in a diode having a pin structure, the p-layer is formed to be flat over the entire surface. However, recently, as described above, a low-concentration p ⁻ layer 27 and a selective In some cases, the p layer is formed of a higher concentration p ⁺ layer 22 formed in the above. In FIG. 4, the planar pattern of the high-concentration p ⁺ layer 22 is a stripe pattern, but there is also a pattern formed in a circular or polygonal island shape. Further, the concentration of the region for forming the p-layer is not limited to two types as shown in the figure, but may be plural types. p ^- layer 27, p ⁺ layer 2
A metal electrode serving as the anode electrode 29 is formed on the surface of the second electrode 2, and a metal electrode serving as the cathode electrode 12 is formed on the surface of the n ⁺ layer 11. The peripheral structure of the semiconductor chip is a well-known peripheral withstand voltage structure 13 in order to secure the withstand voltage of the element.

When a forward voltage is applied to this diode, p
^- layer 27 and the n ^- pn junction of the substrate 1 is forward recovery, p ^- layer 2
Hole injection from 7 into n ^- substrate 1 occurs, conductivity modulation occurs in n ^- substrate 1, and current flows through p ^- layer 27. If this diode is subjected to a reverse recovery operation in this operating state, the density of holes injected into the n ^- substrate 1 is small, so that switching loss is small and good reverse recovery characteristics such as soft recovery characteristics can be obtained. When the forward voltage is further increased, the p ⁺ layer 22 and the n ^+
- now the current flows through the pn junction of the substrate 1,
Even if the conductivity modulation further proceeds and a large current flows, the forward voltage drop of the diode does not increase. However, when the diode performs the reverse recovery operation in this operation state, the carriers accumulated in the pn junction are swept out, and finally the p ⁻ layer 27 and the n ⁻
Since the pn junction of the substrate 1 is recovered, the switching loss is small and the soft recovery characteristic is obtained as described above.

[0005] The above p^-Layer 27 concentration as low as possible
And the shallower diffusion depth is better for the reverse recovery characteristics.
Preferred. However, when a reverse voltage is applied to the diode,
If p ^-The leading end 31 of the depletion layer extending to the layer 27
In other words, a so-called punch-through of reaching the
Thus, the breakdown voltage of the diode is reduced. This punches
The function of preventing the loop⁺On layer 22
You. That is, p when reverse voltage is applied.⁺Layer 22 and n^-Substrate 1
From the pn junction interface 25, n^-The depletion layer spreading on the substrate 1
p^-Pinch off immediately below the layer 27 (the sky spreading from both sides)
The poor layer sticks) n^-A wide depletion layer in the substrate 1
By spreading, p on the other side^-Tip of depletion layer in layer 27
This is because the elongation of 31 is suppressed.

[0006]

The reverse recovery characteristic of the diode has a great influence on the impurity concentration of the p-layer. In the diode as shown in FIG. 4, as described above, since the reverse recovery operation is determined by the low-concentration p ⁻ layer 27,
Good reverse recovery characteristics can be obtained. Further, the high concentration p ⁺ layer 22 in the forward characteristics, to improve surge current withstand made smaller forward voltage drop in the high current region (that of the on-voltage), also in the high-concentration p ⁺ layer 22 By
As described above, the withstand voltage characteristics are also improved.

However, in this structure, p constitutes a p layer ^- must form two layers of the layer 27 and the p ⁺ layer 22. This requires two ion implantation steps, a dedicated photo step for selective ion implantation, and two heat treatment steps, which increases the number of manufacturing steps and increases the manufacturing cost. In addition, since the ion implantation is performed twice, crystal defects are easily generated. Furthermore, since the p layer is not flat and undulates, the elongation of the tip portions 31 and 32 of the depletion layer is not uniform and undulates. Therefore, there is a possibility that the electric field concentration 33 occurs in a portion where the depletion layer is narrow.

An object of the present invention is to provide a low-cost, high-withstand-voltage semiconductor device having a large reverse recovery characteristic and a large surge current resistance.

[0009]

In order to achieve the above object, a second conductive type semiconductor layer is formed on one main surface of a first conductive type semiconductor substrate, and a high concentration first conductive semiconductor layer is formed on the other main surface. Forming a conductive type semiconductor layer, forming at least one groove having a predetermined depth in the second conductive type semiconductor layer, and selectively forming a first main electrode on an exposed surface of the second conductive type semiconductor layer. And a second main electrode is selectively formed on the surface of the first conductivity type semiconductor layer.

A first conductivity type semiconductor substrate and a second conductivity type semiconductor
The distance between the pn junction boundary formed by the layer and the bottom of the groove
It is preferable that the separation is a length that ensures the withstand voltage of the semiconductor device. This
This is a groove formed in the second conductivity type semiconductor layer when a reverse withstand voltage is applied.
By preventing the depletion layer from reaching the bottom of the
The purpose of the present invention is to prevent the loop and secure the pressure resistance. 2nd conductivity type
The surface concentration of the semiconductor region is 1 × 10¹⁸cm^-3Or 1 × 1
0²⁰cm^-3And a groove formed in the second conductivity type semiconductor layer.
Surface concentration of 1 × 10¹⁶cm ^-3Or 1 × 10¹⁷
cm^-3Is effective. This is the second conductivity type semiconductor
The surface concentration of the body region is 1 × 10¹⁸cm^-3If smaller
1 × 10²⁰cm^-3Bigger
Then, crystal defects due to ion implantation are likely to occur, which is preferable.
Not good. On the other hand, the groove formed in the second conductivity type semiconductor layer
Surface concentration of the bottom is 1 × 10¹⁷cm^-3If you make it larger,
Reverse recovery characteristics such as soft recovery characteristics are hindered,
× 10¹⁶cm^-3If you make it smaller, the punch-through phenomenon
As a result, the withstand voltage characteristics decrease, which is not preferable.

[0011]

FIG. 1 is a diagram showing a first embodiment of the present invention.
FIG. 2A is a plan view of the main part of FIG.
FIG. 2B is a cross-sectional view taken along line XX of FIG.
You. In FIG. 1, n^-High concentration on one surface layer of substrate 1
P⁺Layer 2 is formed by ion implantation and thermal diffusion. This p⁺
A groove 3 is formed in the layer 2 by dry etching. Of this groove 3
The plane pattern is a stripe, and the bottom surface 4 of the groove 3 is n^-Base
Plate 1 and p⁺Do not reach the pn junction interface 5 formed by layer 2
With a large depth, a voltage equivalent to the withstand voltage of the diode can be secured.
As described above, the end of the depletion layer extending from the pn junction interface 5
The end (not shown) reaches the bottom surface 4 of the groove 3
No depth. p⁺The diffusion profile of layer 2 is described below
As shown in FIG. 3, the concentration is high on the surface and low in the depth direction.
Has become. Therefore, the surface concentration of the bottom surface 4 of the groove 3 is p⁺layer
2 is lower than the surface concentration. This bottom 4
From the pn junction interface 5 to the low concentration p.^-Layer 7. p
⁺An anode electrode 9 is provided on the surface, the side surface 8 and the bottom surface 4 of the layer 2.
Forming a metal electrode of⁺Cathode voltage is applied to the surface of layer 11
A metal electrode to be the pole 12 is formed.

[0012] In the structure of FIG. 1, the concentration of the p layer in FIG. 4 p ^-
Basically the same characteristics are obtained as in the case of using two types of layer 27 and p ⁺ layer 22. In the manufacturing process of the diode of FIG. 1, the impurity ion implantation process and the thermal diffusion process at the time of forming the p-layer are each performed from twice as in the case of the diode of FIG.
Since the number of times of ion implantation is reduced, damage to the silicon crystal due to ion implantation can be reduced, and introduction of crystal defects and the like can be suppressed low because the number of high-temperature heat treatment steps is small. For this reason, the device characteristics, particularly, the ON characteristics such as the forward voltage drop are improved. Further, since the number of manufacturing steps is reduced, manufacturing costs can be reduced.

More specifically, in the manufacturing process of the diode shown in FIG. 1, the impurity profile of the p ⁺ layer 2 is checked in advance, and the depth of the groove 3 is determined in accordance with the impurity profile. The impurity concentration of the p ⁻ layer 7 to be adjusted is adjusted. When the bottom surface 4 of the groove 3 enters the n ⁻ substrate 1 beyond the pn junction boundary surface 5, the diode cannot maintain the reverse blocking state. Therefore, the position of the bottom surface 4 is the p layer (p ⁺ layer 2 and p ⁻ layer 7). )
I have to come in. The lower the concentration of the p ^- layer 7, the better the reverse recovery characteristics can be obtained. However, when the withstand voltage of the diode is in the 2500 V class, if the thickness of the p ⁻ layer 7 is set to about 2 μm, the surface concentration of the p ⁻ layer 7 becomes 1 from the viewpoint of ensuring the withstand voltage.
A concentration of 10 ¹⁶ cm ^-3 or more is required. On the other hand, if the upper limit is set to 1 10 ¹⁷ cm ^-3 from the reverse recovery characteristic, good characteristics can be obtained. The p ⁺ layer 2 of this structure does not have a pinch-off effect unlike the conventional structure, but has an effect of improving the surge current resistance. Next, this will be described.

When a forward voltage is applied, when the forward voltage is low, a current similarly flows from the low concentration p ^- layer 7 and the p ⁺ layer 2. However, when the state is high, the injection of holes from the p ⁺ layer 2 increases, the conductivity modulation in the n ⁻ substrate 1 increases, and the forward voltage drop of the diode is suppressed even at a large current such as a surge current. As a result, the surge current resistance is improved. On the other hand, at the time of reverse recovery, high lifetime of the p ⁺ layer 2 for concentration p ^- shorter than layer 7, and quickly extinguished the carrier flowing through the p ⁺ layer 2, finally p ^- current through the layer 7 Determines the reverse recovery characteristic, and obtains a good reverse recovery characteristic.
In order to improve the surge current resistance, the surface concentration of the high concentration p ⁺ layer 2 needs to be 1 × 10 ¹⁸ cm ⁻³ or more. However, if it exceeds 1 × 10 ²⁰ cm ⁻³ , the ion implantation amount becomes too large and crystal defects easily occur. Therefore, the upper limit of the surface concentration of the p ⁺ layer 2 is set to 1 × 10 ²⁰ cm ^−3. Specifically, 1 × 10 ¹⁹ cm ⁻³ is preferable.

When the ratio of the area of the surface pattern of the p ^- layer 7 to that of the p ⁺ layer 2 constituting the p layer is changed, the forward characteristics and the reverse recovery characteristics are changed. If the ratio of the p ^- layer 7 becomes too high,
Although the reverse recovery characteristic is improved, the characteristic in a large current region such as a surge current is deteriorated. In the opposite case, the reverse recovery characteristic is deteriorated. Therefore, the ratio of the area is adjusted while looking at the respective balance.

Although the width of the groove 3 at the surface and the width at the bottom surface 4 are equal in FIG. 1, the cross-sectional shape of an inverted trapezoidal groove having a narrower bottom surface 4 may be used. The groove structure also has an effect of dispersing a force on the element surface, such as a pressing force in wire bonding and a pressing force in a pressure contact structure. FIG.
FIG. 4 is a configuration diagram of a main part of a diode according to a second embodiment of the present invention.
FIG. 2A is a plan view, and FIG. 2B is XX in FIG.
It is sectional drawing cut | disconnected by the line.

FIG. 2 differs from FIG. 1 in that the planar pattern of the groove 3a is circular. This plane pattern may of course be a polygon. Alternatively, the groove 3a may have an inverted trapezoidal shape in which the width of the surface is smaller than the width of the bottom portion 4. Here, the cross-sectional structure is the same as that of FIG. FIG. 3 shows the diffusion profile of the p-layer of the diode of the present invention. The p ⁺ layer 2 has a depth of 7 μm up to the pn junction interface 5. For example, using boron as the impurity ion species,
The dose is about 1 × 10 ¹⁵ cm ^-2 and the diffusion temperature is 1150 ° C
Here, the diffusion time is a diffusion profile when the diffusion time is set to ten and several hours. When the breakdown voltage of this diode is equivalent to 2500 V, it is preferable that the surface concentration at the bottom 4 of the groove 3 is 1 × 10 ¹⁶ cm ⁻³ and the depth of the groove is about 5 μm. Of course, when the breakdown voltage of the diode and the shape of the diffusion profile are different, the depth of the groove 4 is different.

[0018]

Effect of the Invention] The present invention constitutes a p layer p ^-
The formation of the layer and the p ⁺ layer is performed in the same ion implantation step and thermal diffusion step, so that the manufacturing cost can be reduced. In addition, the number of times of the ion implantation process and the number of thermal diffusion processes are
Since the number of times can be reduced, the introduction of crystal defects is suppressed, and the device characteristics such as the ON characteristics of the diode are improved.
By flattening the pn junction surface, the withstand voltage characteristic can be improved while maintaining or improving the reverse recovery characteristic and the surge current resistance of the conventional diode.

[Brief description of the drawings]

FIGS. 1A and 1B are main part configuration diagrams of a diode according to a first embodiment of the present invention, wherein FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along line XX of FIG.

FIGS. 2A and 2B are main part configuration diagrams of a diode according to a second embodiment of the present invention, wherein FIG. 2A is a plan view and FIG. 2B is a cross-sectional view taken along line XX of FIG.

FIG. 3 is a diagram showing a diffusion profile of a p-layer of the diode of the present invention.

4 (a) is a plan view, and FIG. 4 (b) is a cross-sectional view taken along line XX of FIG. 4 (a).

[Explanation of symbols]

Reference Signs List 1 n ^- substrate 2 p ⁺ layer 3 groove 3 a groove 4 bottom surface 5 pn junction boundary surface 7 p ^- layer 8 side surface 9 anode electrode 11 n ⁺ layer 12 cathode electrode 13 peripheral breakdown voltage structure 22 p ⁺ layer 25 pn junction boundary surface 27 p ^- the distal end portion 32 depletion layer 29 anode electrode 31 depletion tip 33 field concentration

Claims (3)

[Claims] A first conductive type semiconductor substrate having a second main surface on one main surface thereof;
A conductive semiconductor layer is formed, and a high-concentration first layer is formed on the other main surface.
A conductive semiconductor layer is formed, at least one groove having a predetermined depth is formed in the second conductive semiconductor layer, and a first main electrode is selectively formed on an exposed surface of the second conductive semiconductor layer. And a second main electrode is selectively formed on the surface of the first conductivity type semiconductor layer. 2. The semiconductor device according to claim 1, wherein a distance between a pn junction boundary formed by the first conductivity type semiconductor substrate and the second conductivity type semiconductor layer and a bottom surface of the groove is a length for ensuring a withstand voltage of the semiconductor device. 2. The semiconductor device according to claim 1, wherein 3. The method according to claim 1, wherein the surface concentration of the second conductivity type semiconductor layer is 1 × 10 5.
¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ , and the surface concentration of the bottom surface of the groove formed in the second conductivity type semiconductor layer is 1 × 10 ¹⁶ c
2. The semiconductor device according to claim 1, wherein the ^thickness is from m ^-3 to 1 × 10 ¹⁷ cm ^-3 .