JP2000216381A - Field effect transistor - Google Patents
Field effect transistorInfo
- Publication number
- JP2000216381A JP2000216381A JP11013919A JP1391999A JP2000216381A JP 2000216381 A JP2000216381 A JP 2000216381A JP 11013919 A JP11013919 A JP 11013919A JP 1391999 A JP1391999 A JP 1391999A JP 2000216381 A JP2000216381 A JP 2000216381A
- Authority
- JP
- Japan
- Prior art keywords
- region
- effect transistor
- insulating film
- band gap
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 23
- 239000004065 semiconductor Substances 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 abstract description 13
- 239000011229 interlayer Substances 0.000 abstract description 4
- 230000015556 catabolic process Effects 0.000 abstract description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 14
- 229910010271 silicon carbide Inorganic materials 0.000 description 14
- 238000004519 manufacturing process Methods 0.000 description 7
- 239000012535 impurity Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000010410 layer Substances 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
- H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はＳｉ（珪素）よりバ
ンドギャップの広いＳｉＣ（炭化珪素）等の半導体から
なるワイドバンドギャップ半導体基板を有するパワーＭ
ＯＳＦＥＴ等の電界効果トランジスタに関するものであ
る。The present invention relates to a power M having a wide band gap semiconductor substrate made of a semiconductor such as SiC (silicon carbide) having a wider band gap than Si (silicon).
It relates to a field effect transistor such as an OSFET.
【０００２】[0002]
【従来の技術】図７は従来の電界効果トランジスタ（特
開平９−７４１９１号公報）を示す断面図である。図に
示すように、高濃度Ｎ+型ＳｉＣからなるワイドバンド
ギャップ半導体基板１０上にＮ型ＳｉＣからなるエピタ
キシャル領域２０が形成され、エピタキシャル領域２０
上にＰ型ＳｉＣからなるエピタキシャル領域６０が形成
され、エピタキシャル領域６０内に溝５０およびＮ+型
ＳｉＣからなるソース領域４０が形成され、溝５０の側
壁にＮ型ＳｉＣからなるチャンネル領域３０が形成さ
れ、溝５０内にゲート絶縁膜７０を介してゲート電極８
０が形成されている。また、層間絶縁膜９０によりゲー
ト電極８０と絶縁されてソース領域４０に接続されたソ
ース電極１００が形成され、ワイドバンドギャップ半導
体基板１０の裏面にドレイン電極１１０が形成されてい
る。2. Description of the Related Art FIG. 7 is a sectional view showing a conventional field effect transistor (Japanese Patent Application Laid-Open No. 9-74191). As shown in the figure, an epitaxial region 20 made of N-type SiC is formed on a wide band gap semiconductor substrate 10 made of high-concentration N + -type SiC.
An epitaxial region 60 made of P-type SiC is formed thereon, a groove 50 and a source region 40 made of N + -type SiC are formed in the epitaxial region 60, and a channel region 30 made of N-type SiC is formed on the side wall of the groove 50. The gate electrode 8 is formed in the trench 50 via the gate insulating film 70.
0 is formed. Further, a source electrode 100 connected to the source region 40 while being insulated from the gate electrode 80 by the interlayer insulating film 90 is formed, and a drain electrode 110 is formed on the back surface of the wide band gap semiconductor substrate 10.
【０００３】この電界効果トランジスタにおいては、ド
レイン電極１１０とソース電極１００との間に電圧が印
加された状態で、ゲート電極８０に電圧が印加される
と、ゲート電極８０に対向したチャンネル領域３０の表
面にＮ型蓄積層のチャンネルが形成され、ドレイン電極
１１０からソース電極１００に電流が流れる。In this field effect transistor, when a voltage is applied to the gate electrode 80 in a state where a voltage is applied between the drain electrode 110 and the source electrode 100, the channel region 30 facing the gate electrode 80 A channel of the N-type accumulation layer is formed on the surface, and current flows from the drain electrode 110 to the source electrode 100.
【０００４】[0004]
【発明が解決しようとする課題】しかし、図７に示した
電界効果トランジスタにおいては、ドレイン電極１１０
に高電圧が印加されたとき、溝５０の底部のゲート絶縁
膜７０に電界が加わるので、ドレイン耐圧が低い。ま
た、溝５０の側壁にチャンネル領域３０をエピタキシャ
ル法によって形成するので、プロセス工程が複雑とな
る。そして、トレンチエッチングにより形成した溝５０
の側壁にエピタキシャル法により均質で欠陥の少ないチ
ャンネル領域３０を形成するのは困難であり、トレンチ
エッチングのダメージの影響によりチャンネル抵抗が高
い。However, in the field effect transistor shown in FIG.
When a high voltage is applied to the gate insulating film 70, an electric field is applied to the gate insulating film 70 at the bottom of the groove 50, so that the drain breakdown voltage is low. Further, since the channel region 30 is formed on the side wall of the groove 50 by the epitaxial method, the process steps are complicated. Then, the groove 50 formed by the trench etching
It is difficult to form a uniform and less defective channel region 30 on the side wall of the trench by the epitaxial method, and the channel resistance is high due to the influence of the trench etching damage.
【０００５】本発明は上述の課題を解決するためになさ
れたもので、ドレイン耐圧が高く、プロセス工程が単純
であり、チャンネル抵抗が低い電界効果トランジスタを
提供することを目的とする。An object of the present invention is to provide a field effect transistor having a high drain breakdown voltage, a simple process, and a low channel resistance.
【０００６】[0006]
【課題を解決するための手段】この目的を達成するた
め、本発明においては、Ｓｉよりバンドギャップの広い
半導体からなるワイドバンドギャップ半導体基板を有す
る電界効果トランジスタにおいて、第１導伝型の上記ワ
イドバンドギャップ半導体基板の一主面の所定の領域に
複数の溝を形成し、隣接する上記溝の間に第１導伝型の
チャンネル領域を形成し、上記溝に隣接した部分に第２
導伝型の半導体領域を形成し、上記溝内にゲート絶縁膜
を形成し、上記ゲート絶縁膜により上記チャンネル領域
と絶縁してゲート電極を形成する。According to the present invention, there is provided a field effect transistor having a wide bandgap semiconductor substrate made of a semiconductor having a bandgap wider than Si. A plurality of grooves are formed in a predetermined region of one main surface of the band gap semiconductor substrate, a first conductive type channel region is formed between the adjacent grooves, and a second channel region is formed in a portion adjacent to the grooves.
A conductive semiconductor region is formed, a gate insulating film is formed in the trench, and a gate electrode is formed insulated from the channel region by the gate insulating film.
【０００７】さらに、上記ワイドバンドギャップ半導体
基板としてＳｉＣからなるものを用いるのが好ましい。Furthermore, it is preferable to use a substrate made of SiC as the wide band gap semiconductor substrate.
【０００８】[0008]
【発明の効果】本発明に係る電界効果トランジスタにお
いては、ドレイン電極とソース電極との間に高電圧が印
加された場合、半導体領域から伸びる空乏層によってゲ
ート絶縁膜にかかる電界がシールドされるから、ドレイ
ン耐圧が高く、またチャンネル領域を溝の側壁にエピタ
キシャル成長させる必要がないから、プロセス工程が単
純であり、また均質で欠陥の少ないチャンネル領域を形
成することができるから、チャンネル抵抗が低い。According to the field effect transistor of the present invention, when a high voltage is applied between the drain electrode and the source electrode, the electric field applied to the gate insulating film is shielded by the depletion layer extending from the semiconductor region. Since the drain withstand voltage is high and the channel region does not need to be epitaxially grown on the side wall of the groove, the process steps are simple, and a uniform and less defective channel region can be formed, so that the channel resistance is low.
【０００９】[0009]
【発明の実施の形態】図１は本発明に係る電界効果トラ
ンジスタを示す一部切断斜視図である。図に示すよう
に、Ｎ+型ＳｉＣからなるワイドバンドギャップ半導体
基板２１０上にＮ型ＳｉＣからなるエピタキシャル領域
２２０が形成され、エピタキシャル領域２２０上にＮ型
ＳｉＣからなるチャンネル領域２３０が形成され、チャ
ンネル領域２３０上にＮ+型ＳｉＣからなるソース領域
２４０が形成され、エピタキシャル領域２２０の一主面
側の所定の領域にエピタキシャル領域２２０に達する複
数の凹型の溝２５０が形成されている。すなわち、隣接
する溝２５０間にチャンネル領域２３０が形成されてい
る。また、溝２５０の下部と隣接する部分およびチャン
ネル領域２３０の一部の表面にＰ型ＳｉＣからなる半導
体領域２６０が形成され、溝２５０内にゲート絶縁膜２
７０を介してゲート電極２８０が形成されている。ここ
で、ゲート電極２８０の材料としてはチャンネル領域２
３０の多数キャリアが空乏化するような仕事関数の値を
有するものを選択している。また、層間絶縁膜２９０に
よりゲート電極２８０と絶縁されてソース領域２４０に
接続されたソース電極３００が形成され、ワイドバンド
ギャップ半導体基板２１０の裏面にドレイン電極３１０
が形成され、ソース電極３００にソース端子３２０が接
続され、ドレイン電極３１０にドレイン端子３３０が接
続され、ゲート電極２８０にゲート端子３４０が接続さ
れている。FIG. 1 is a partially cutaway perspective view showing a field effect transistor according to the present invention. As shown in the figure, an epitaxial region 220 made of N-type SiC is formed on a wide band gap semiconductor substrate 210 made of N + -type SiC, and a channel region 230 made of N-type SiC is formed on the epitaxial region 220. A source region 240 made of N + -type SiC is formed on region 230, and a plurality of concave grooves 250 reaching epitaxial region 220 are formed in a predetermined region on one main surface side of epitaxial region 220. That is, the channel region 230 is formed between the adjacent grooves 250. Further, a semiconductor region 260 made of P-type SiC is formed in a portion adjacent to a lower portion of the groove 250 and a part of the surface of the channel region 230, and the gate insulating film 2 is formed in the groove 250.
A gate electrode 280 is formed via the gate electrode 70. Here, the material of the gate electrode 280 is the channel region 2
Those having a work function value such that 30 majority carriers are depleted are selected. Further, a source electrode 300 connected to the source region 240 while being insulated from the gate electrode 280 by the interlayer insulating film 290 is formed, and the drain electrode 310 is formed on the back surface of the wide band gap semiconductor substrate 210.
Are formed, a source terminal 320 is connected to the source electrode 300, a drain terminal 330 is connected to the drain electrode 310, and a gate terminal 340 is connected to the gate electrode 280.
【００１０】この電界効果トランジスタにおいては、ゲ
ート電極２８０に電圧が印加されていない状態では、ゲ
ート電極２８０とチャンネル領域２３０との仕事関数差
により多数キャリアが空乏化しており、ドレイン電極３
１０とソース電極３００との間は電流が非導通状態とな
る。そして、ドレイン電極３１０とソース電極３００と
の間に電圧が印加された状態で、ゲート電極２８０に電
圧が印加されると、ゲート電極２８０と対向したチャン
ネル領域２３０の表面にＮ型蓄積層型のチャンネルが形
成され、ドレイン電極３１０からソース電極３００に電
流が流れる。In this field-effect transistor, when no voltage is applied to the gate electrode 280, majority carriers are depleted due to a work function difference between the gate electrode 280 and the channel region 230.
The current is non-conductive between 10 and the source electrode 300. When a voltage is applied to the gate electrode 280 in a state where a voltage is applied between the drain electrode 310 and the source electrode 300, an N-type accumulation layer type is formed on the surface of the channel region 230 facing the gate electrode 280. A channel is formed, and current flows from the drain electrode 310 to the source electrode 300.
【００１１】このような電界効果トランジスタにおいて
は、ドレイン電極３１０とソース電極３００との間に高
電圧が印加された場合、溝２５０の下部と隣接する部分
に形成された半導体領域２６０から伸びる空乏層によっ
てゲート絶縁膜２７０にかかる電界がシールドされるか
ら、ドレイン耐圧が高い。また、チャンネル領域２３０
を溝２５０の側壁にエピタキシャル成長させる必要がな
いから、プロセス工程が単純である。また、チャンネル
領域２３０へのプロセス形成上のダメージが少なく、均
質で欠陥の少ないチャンネル領域２３０を形成すること
ができるから、チャンネル抵抗が低い。また、ゲート電
極２８０の材料としてチャンネル領域２３０の多数キャ
リアが空乏化するような仕事関数の値を有するものを選
択しているから、ゲート電極２８０に電圧が印加されな
い状態でチャンネルをオフにすることが容易である。In such a field effect transistor, when a high voltage is applied between drain electrode 310 and source electrode 300, a depletion layer extending from semiconductor region 260 formed in a portion adjacent to the lower portion of trench 250 This shields the electric field applied to the gate insulating film 270, so that the drain withstand voltage is high. Also, the channel area 230
Need not be epitaxially grown on the sidewalls of the groove 250, the process steps are simple. In addition, since the channel region 230 is less likely to be damaged in process formation and can be formed in a uniform and less defective channel region, the channel resistance is low. In addition, since a material having a work function value such that majority carriers in the channel region 230 are depleted is selected as a material of the gate electrode 280, the channel is turned off in a state where no voltage is applied to the gate electrode 280. Is easy.
【００１２】つぎに、図１に示した電界効果トランジス
タの製造方法を図２〜図６により説明する。まず、図２
に示すように、ワイドバンドギャップ半導体基板２１０
上に例えば不純物濃度が１×１０14〜１×１０18ｃ
ｍ-3、厚さが０．１〜数十μｍのエピタキシャル領域２
２０を形成し、エピタキシャル領域２２０の表面に例え
ば不純物濃度が１×１０14〜１×１０17ｃｍ-3、厚さが
数千Å〜数μｍのチャンネル領域２３０を形成し、さら
にチャンネル領域２３０の表面に例えば不純物濃度が１
×１０18〜１×１０21ｃｍ-3、厚さが数十Å〜数μｍの
ソース領域２４０を形成する。つぎに、図３に示すよう
に、所定の領域にパターンニングされた絶縁膜４１０を
マスクとして、エピタキシャル領域２２０に達するよう
に溝２５０を形成する。つぎに、図４に示すように、絶
縁膜４１０をマスクとして溝２５０の下部と隣接する部
分に溝２５０からの不純物の拡散によって半導体領域２
６０を形成する。このとき、所定の領域の絶縁膜４１０
を除去したのちに半導体領域２６０を形成することによ
り、チャンネル領域２３０の一部の表面にも半導体領域
２６０を形成する。つぎに、図５に示すように、溝２５
０内に例えば厚さが１００〜３０００Åの酸化膜よりな
るゲート絶縁膜２７０を形成し、さらに溝２５０の内部
にゲート電極２８０を形成する。つぎに、図６に示すよ
うに、溝２５０内に層間絶縁膜２９０を形成したのち、
ソース領域２４０の表面にソース電極３００を形成す
る。その後、ワイドバンドギャップ半導体基板２１０の
裏面にドレイン電極３１０を形成する。Next, a method of manufacturing the field effect transistor shown in FIG. 1 will be described with reference to FIGS. First, FIG.
As shown in FIG.
For example, the impurity concentration is 1 × 10 14 to 1 × 10 18 c
m −3 , an epitaxial region 2 having a thickness of 0.1 to several tens μm
Then, a channel region 230 having an impurity concentration of, for example, 1 × 10 14 to 1 × 10 17 cm −3 and a thickness of several thousand to several μm is formed on the surface of the epitaxial region 220. For example, the surface has an impurity concentration of 1
A source region 240 having a size of × 10 18 to 1 × 10 21 cm −3 and a thickness of several tens to several μm is formed. Next, as shown in FIG. 3, a groove 250 is formed to reach the epitaxial region 220 using the insulating film 410 patterned in a predetermined region as a mask. Next, as shown in FIG. 4, the semiconductor region 2 is diffused into the portion adjacent to the lower portion of the trench 250 by diffusion of impurities from the trench 250 using the insulating film 410 as a mask.
Form 60. At this time, the insulating film 410 in a predetermined region
The semiconductor region 260 is formed on the surface of a part of the channel region 230 after removing the semiconductor region 260. Next, as shown in FIG.
A gate insulating film 270 made of, for example, an oxide film having a thickness of, for example, 100 to 3000 ０ is formed in the gate electrode 250, and a gate electrode 280 is formed in the trench 250. Next, as shown in FIG. 6, after forming an interlayer insulating film 290 in the groove 250,
A source electrode 300 is formed on the surface of the source region 240. Thereafter, a drain electrode 310 is formed on the back surface of the wide band gap semiconductor substrate 210.
【００１３】この電界効果トランジスタの製造方法にお
いては、溝２５０からの不純物の拡散によって半導体領
域２６０を形成するから、ＳｉＣにおいては高温でも不
純物が拡散しにくく、深い接合を形成することが困難で
あったとしても、エピタキシャル領域２２０の内部に半
導体領域２６０を容易に形成することができる。In this method of manufacturing a field effect transistor, since the semiconductor region 260 is formed by diffusion of the impurity from the trench 250, it is difficult for SiC to diffuse the impurity even at a high temperature, and it is difficult to form a deep junction. Even if it does, semiconductor region 260 can be easily formed inside epitaxial region 220.
【００１４】なお、上述実施の形態においては、第１導
伝型をＮ型とし、第２導伝型をＰ型としたが、第１導伝
型をＰ型とし、第２導伝型をＮ型としてもよい。また、
上述実施の形態においては、溝２５０の下部と隣接する
部分に半導体領域２６０を形成したが、溝に隣接する部
分に半導体領域を形成すればよい。In the above embodiment, the first conductive type is N-type and the second conductive type is P-type. However, the first conductive type is P-type and the second conductive type is P-type. It may be N-type. Also,
In the above-described embodiment, the semiconductor region 260 is formed in a portion adjacent to the lower portion of the groove 250, but a semiconductor region may be formed in a portion adjacent to the groove.
【図１】本発明に係る電界効果トランジスタを示す一部
切断斜視図である。FIG. 1 is a partially cutaway perspective view showing a field effect transistor according to the present invention.
【図２】図１に示した電界効果トランジスタの製造方法
の説明図である。FIG. 2 is an explanatory diagram of a method for manufacturing the field-effect transistor shown in FIG.
【図３】図１に示した電界効果トランジスタの製造方法
の説明図である。FIG. 3 is an explanatory diagram of a method for manufacturing the field-effect transistor shown in FIG.
【図４】図１に示した電界効果トランジスタの製造方法
の説明図である。FIG. 4 is an explanatory diagram of a method for manufacturing the field-effect transistor shown in FIG.
【図５】図１に示した電界効果トランジスタの製造方法
の説明図である。FIG. 5 is an explanatory diagram of a method for manufacturing the field-effect transistor shown in FIG.
【図６】図１に示した電界効果トランジスタの製造方法
の説明図である。FIG. 6 is an explanatory diagram of the method for manufacturing the field-effect transistor shown in FIG.
【図７】従来の電界効果トランジスタを示す断面図であ
る。FIG. 7 is a sectional view showing a conventional field-effect transistor.
２１０…ワイドバンドギャップ半導体基板 ２３０…チャンネル領域 ２５０…溝 ２６０…半導体領域 ２７０…ゲート絶縁膜 210: wide band gap semiconductor substrate 230: channel region 250: groove 260: semiconductor region 270: gate insulating film
Claims (2)
なるワイドバンドギャップ半導体基板を有する電界効果
トランジスタにおいて、第１導伝型の上記ワイドバンド
ギャップ半導体基板の一主面の所定の領域に複数の溝を
形成し、隣接する上記溝の間に第１導伝型のチャンネル
領域を形成し、上記溝に隣接した部分に第２導伝型の半
導体領域を形成し、上記溝内にゲート絶縁膜を形成し、
上記ゲート絶縁膜により上記チャンネル領域と絶縁して
ゲート電極を形成したことを特徴とする電界効果トラン
ジスタ。1. A field effect transistor having a wide band gap semiconductor substrate made of a semiconductor having a band gap wider than that of Si, wherein a plurality of grooves are formed in a predetermined region on one main surface of the first conduction type wide band gap semiconductor substrate. A channel region of the first conductivity type is formed between the adjacent grooves, a semiconductor region of the second conductivity type is formed in a portion adjacent to the groove, and a gate insulating film is formed in the groove. Forming
A field effect transistor, wherein a gate electrode is formed insulated from the channel region by the gate insulating film.
てＳｉＣからなるものを用いたことを特徴とする請求項
１に記載の電界効果トランジスタ。2. A field effect transistor according to claim 1, wherein said wide band gap semiconductor substrate is made of SiC.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11013919A JP2000216381A (en) | 1999-01-22 | 1999-01-22 | Field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11013919A JP2000216381A (en) | 1999-01-22 | 1999-01-22 | Field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000216381A true JP2000216381A (en) | 2000-08-04 |
Family
ID=11846594
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11013919A Pending JP2000216381A (en) | 1999-01-22 | 1999-01-22 | Field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000216381A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004032244A1 (en) * | 2002-10-04 | 2004-04-15 | Shindengen Electric Manufacturing Co., Ltd. | Semiconductor device and process for fabricating the same |
| JP2005236267A (en) * | 2004-01-23 | 2005-09-02 | Toshiba Corp | Semiconductor device |
| US7470953B2 (en) | 2003-10-08 | 2008-12-30 | Toyota Jidosha Kabushiki Kaisha | Insulated gate type semiconductor device and manufacturing method thereof |
-
1999
- 1999-01-22 JP JP11013919A patent/JP2000216381A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004032244A1 (en) * | 2002-10-04 | 2004-04-15 | Shindengen Electric Manufacturing Co., Ltd. | Semiconductor device and process for fabricating the same |
| US7196376B2 (en) | 2002-10-04 | 2007-03-27 | Shindengen Electric Manufacturing Co., Ltd., | Trench-type power MOSFET with embedded region at the bottom of the gate and increased breakdown voltage |
| KR100958561B1 (en) | 2002-10-04 | 2010-05-17 | 신덴겐코교 가부시키가이샤 | Semiconductor device and process for fabricating the same |
| US7470953B2 (en) | 2003-10-08 | 2008-12-30 | Toyota Jidosha Kabushiki Kaisha | Insulated gate type semiconductor device and manufacturing method thereof |
| JP2005236267A (en) * | 2004-01-23 | 2005-09-02 | Toshiba Corp | Semiconductor device |
| JP4564362B2 (en) * | 2004-01-23 | 2010-10-20 | 株式会社東芝 | Semiconductor device |
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