JP2005136208A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, capable of improving the switching characteristics at the time of gate-off by reducing the ON-resistance in a conventional L-IGBT. <P>SOLUTION: The semiconductor device is provided with a 1st conductive type semiconductor substrate, a 2nd conductive type extended drain region, a 2nd conductive type high-concentration drain region, a 2nd conductive type source region, a 1st conductive type adjacent region, and a 1st conductive type high-concentration drain adjacent region. The semiconductor substrate is constituted of forming an epitaxial layer of low concentration on the upper part of the high-concentration layer. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device such as a high breakdown voltage lateral insulated gate bipolar transistor.

  Conventionally, various structures have been proposed for high breakdown voltage lateral insulated gate bipolar transistors (hereinafter referred to as L-IGBTs) as semiconductor devices. Hereinafter, a semiconductor device disclosed in Patent Document 1 will be described as an example with reference to the drawings.

FIG. 3 is a cross-sectional view showing a conventional L-IGBT. In FIG. 3, an extended drain region 52 of the second conductivity type is formed on the surface portion of the semiconductor substrate 51 of the first conductivity type. A high-concentration drain region 53 of the second conductivity type is formed on the surface portion of the extended drain region 52. A high concentration drain adjacent region 54 of the first conductivity type is formed so as to surround the high concentration drain region 53. The drain adjacent region 54 is electrically connected to the high concentration drain region 53. In addition, a top region 55 of the first conductivity type is formed on the surface portion of the extended drain region 52 so as to surround the high concentration drain region 53 and the drain adjacent region 54. The top region 55 is electrically connected to the semiconductor substrate 51. In addition, a high-concentration source region 56 of the second conductivity type is formed on the surface portion of the semiconductor substrate 51. A high-concentration substrate contact region 57 of the first conductivity type is formed in the central portion of the high-concentration source region 56. The high-concentration channel stopper 58 of the first conductivity type is formed so as to surround the high-concentration source region 56. Further, on the surface of the semiconductor substrate 51, an insulating film 60 extending from the drain adjacent region 54 to the high concentration source region 56, and a drain having a T-shaped cross section electrically connected to the high concentration drain region 53 and the drain adjacent region 54. An electrode 61 and a source electrode 62 having a T-shaped cross section electrically connected to the high concentration source region 56 and the substrate contact region 57 are formed. The gate electrode 63 is made of a polycrystalline silicon film and is formed from the end of the extended drain region 52 to the end of the high concentration source region 56. A channel is formed below the gate oxide film 64 below the gate electrode 63.
JP-A-6-224426

  In the conventional L-IGBT, the carriers injected from the first conductivity type high concentration drain adjacent region 54 pass through the extended drain region 52 from the first conductivity type high concentration substrate contact region 57 to the source electrode. It flows into 111. Here, for the purpose of realizing a high breakdown voltage characteristic, the first conductivity type semiconductor substrate 51 is formed at a low concentration. Accordingly, the inflow of carriers to the semiconductor substrate 51 side is remarkably limited, and there is a limit in reducing the on-resistance.

  Further, residual minority carriers injected from the high concentration drain adjacent region 54 to the extended drain region 52 at the time of gate-off are attracted by the electric field of the depletion layer formed in the extended drain region 52, and the substrate contact region via the semiconductor substrate 51. 57 is removed from the source electrode 111. Here, as described above, since the semiconductor substrate 51 is formed at a low concentration, the extraction of carriers to the semiconductor substrate 51 side is remarkably limited, and there is a drawback in that there is a limit in improving the switching characteristics at the time of off. .

  Therefore, an object of the present invention is to provide a semiconductor device capable of reducing the on-resistance in a conventional L-IGBT and improving the switching characteristics when the gate is off.

  In order to achieve the above object, a semiconductor device according to the present invention has the following configuration. That is, the semiconductor device according to the first aspect of the present invention includes a first conductivity type semiconductor substrate in which a low concentration epitaxial layer is formed on a high concentration layer, and a second conductivity type formed on a surface portion of the epitaxial layer. An extended drain region; a second conductivity type high-concentration drain region formed on a surface portion of the extended drain region; and a second conductivity type formed on the surface portion of the epitaxial layer at a predetermined interval from the extended drain region. A source region, a top region of a first conductivity type formed in a portion between the high concentration drain region and the source region on the surface of the extended drain region and electrically connected to the semiconductor substrate; and a surface portion of the extended drain region And is formed at a portion between the high concentration drain region and the top region and adjacent to the high concentration drain region, and electrically connected to the high concentration drain region. And a heavily doped drain adjacent region of the first conductivity type continued.

  According to a second aspect of the invention, there is provided a first conductivity type semiconductor substrate having a low concentration epitaxial layer formed on a high concentration layer, and a second conductivity type semiconductor substrate formed on a surface portion of the epitaxial layer. An extended drain region; a second conductivity type high-concentration drain region formed on a surface portion of the extended drain region; and a second conductivity type formed on the surface portion of the epitaxial layer at a predetermined interval from the extended drain region. One or more buried regions of the first conductivity type formed in a portion between the source region and the high concentration drain region and the source region inside the extended drain region and electrically connected to the semiconductor substrate, and the extended drain region Formed on the surface portion of the substrate and between the high concentration drain region and the buried region and adjacent to the high concentration drain region. And an electrical connection is heavily doped drain adjacent region of the first conductivity type was a.

  The semiconductor device may further include a drain electrode connected to the high concentration drain adjacent region, a contact electrode connected to the high concentration drain region, and a resistor inserted between the drain region and the contact electrode. .

  According to the present invention, the first conductivity type epitaxial layer on the first conductivity type high concentration semiconductor substrate is formed to reduce the impedance between the extended drain region and the semiconductor substrate, thereby ensuring a high breakdown voltage. However, the on-resistance of the L-IGBT can be reduced and the switching characteristics when the gate is off can be improved.

(First embodiment)
The semiconductor device according to the first embodiment of the present invention will be described below with reference to the drawings. FIG. 1A is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention. Hereinafter, a detailed configuration of the present semiconductor device which is an L-IGBT will be described.

  In FIG. 1A, a p-type epitaxial layer 100-2 (impurity concentration: about 1014 / cm3 to about 1015) is formed on a p-type high concentration semiconductor substrate 100-1 (impurity concentration: about 1018 / cm3 to about 1020 / cm3). / Cm3) is formed. After introducing an n-type impurity into the semiconductor substrate, thermal diffusion is performed to form an extended drain region 101 made of an n-type impurity layer having a depth of about 5 to 15 μm. A p-type top region 103 that is electrically connected to the semiconductor substrate is formed on the surface of the extended drain region 101. Further, an n-type high concentration drain region 109 and a p-type high concentration drain adjacent region 110 are formed on the surface of the extended drain region 101. The high concentration drain adjacent region 110 is formed at a position between the high concentration drain region 109 and the top region 103 and adjacent to the high concentration drain region 109. The high concentration drain adjacent region 110 is electrically connected to the high concentration drain region 109. In FIG. 1A, the high concentration drain adjacent region 110 is formed so as to surround the high concentration drain region 109. The top region 103 is formed so as to surround the high concentration drain region 109 and the high concentration drain adjacent region 110. An insulating film 108 is formed on the surface of the semiconductor substrate, and the extended drain region 101 is connected to a drain electrode 112 having a T-shaped cross section extending through the insulating film 108. That is, the extended drain region 101 is electrically connected to the drain electrode 112.

  In addition, a source region 104 made of an n-type region and a substrate contact region 105 made of a p ++ type region are formed on the surface portion of the epitaxial layer 100-2 at a distance from the extended drain region 101. The substrate contact region 105 is electrically connected to the epitaxial layer 100-2. The source region 104 and the substrate contact region 105 are connected to a source electrode 111 having a T-shaped cross section that extends through the insulating film 108. The source region 104 is set to the same potential as the epitaxial layer 100-2. The source region 104 and the substrate contact region 105 are surrounded by a p + type anti-punch through region 102 having an impurity concentration higher than that of the semiconductor substrate. Since the depletion layer extending from the extended drain region 101 to the channel region side is suppressed from being expanded by the anti-punch through region 102, the punch-through phenomenon is prevented by the anti-punch through region 102.

  A gate electrode 107 is formed on the epitaxial layer 100-2 between the extended drain region 101 and the source region 104 with a gate insulating film 106 interposed therebetween. The region of the epitaxial layer 100-2 below the gate electrode 107 functions as a channel region.

  In the semiconductor device according to the first embodiment, a p-type top region 103 is formed in the extended drain region 101. Therefore, when a high voltage is applied to the extended drain region 101, the extended drain region 101, the epitaxial layer 100-2, and the top region 103 are in a reverse bias state. For this reason, as shown in FIG. 1A, each depletion layer expands from the junction between the p-type top region 103 and the extended drain region 101 and the junction between the extended drain region 101 and the epitaxial layer 100-2. The depletion layers are continuous with each other, and the region of the depletion layer becomes large, and the extended drain region 101 is completely depleted. Thus, it becomes easy to achieve a high breakdown voltage in the semiconductor device shown in FIG. 1A.

  In addition, since the epitaxial layer 100-2 has a low concentration, it is difficult to form a depletion layer, whereby a high breakdown voltage can be achieved. The epitaxial layer 100-2 needs to be formed thicker than the thickness at which the epitaxial layer 100-2 becomes a depletion layer, depending on the magnitude of the applied voltage. For example, in the first embodiment, when the applied voltage is about 700 (V), the thickness of the epitaxial layer 100-2 needs to be about 100 μm from the surface of the semiconductor substrate. Thus, when the applied voltage is known in advance according to the application of the semiconductor device, it is preferable to form the epitaxial layer 100-2 in consideration of the thickness at which the semiconductor substrate becomes depleted.

  In addition, when a voltage is applied to the gate electrode 107 to make the channel flow region of the MOS transistor conductive, the electron current of the MOS transistor flows below the top region 103 and below the high-concentration drain adjacent region 110, and high-concentration. The drain electrode 112 is reached through the drain region 109. At this time, when the electron current of the MOS transistor increases and the voltage drop below the high concentration drain adjacent region 110 reaches 0.7 (V), the high concentration drain adjacent region 110 becomes the emitter, and the high concentration drain adjacent region 110. A PNP bipolar transistor having the lower extended drain region 101 as a base and the substrate contact region 105 as a collector is turned on. As a result, minority carriers are injected from the high concentration drain adjacent region 110 into the extended drain region 101, and the bipolar operation of the L-IGBT is started.

  In the present embodiment, the semiconductor substrate is formed of a high concentration semiconductor substrate 100-1 and a low concentration epitaxial layer 100-2. By forming such a high-concentration semiconductor substrate 100-1, the impedance between the extended drain region 101 and the semiconductor substrate is reduced. Here, when the PNP bipolar transistor becomes conductive, minority carriers are injected from the p-type high concentration drain adjacent region 110 into the extended drain region 101 as described above. In this embodiment, since the impedance between the extended drain region 101 and the high concentration semiconductor substrate 100-1 is reduced, minority carriers flow not only to the high concentration substrate contact region 105 but also to the semiconductor substrate side. It will be. As a result, the resistance value decreases, and according to the present embodiment, the on-resistance can be reduced.

  Further, when the gate is turned off, the residual minority carriers injected from the high concentration drain adjacent region 110 into the extended drain region 101 are attracted by the electric field of the depletion layer formed in the extended drain region 101, or the substrate contact region 105 or the high concentration semiconductor. It will come off to the board | substrate 100-1. At this time, in this embodiment, since the impedance between the extended drain region 101 and the high concentration semiconductor substrate 100-1 is reduced, the residual minority carriers in the extended drain region 101 are p-type high concentration substrate contact regions. Not only in the 105 direction but also drawn by the electric field of the depletion layer in the direction of the high concentration semiconductor substrate 100-1, it escapes to the semiconductor substrate. Therefore, according to the present embodiment, it is possible to improve the switching characteristics when the gate is off.

  As described above, in the semiconductor device according to the present embodiment, in order to reduce the impedance between the low concentration layer (epitaxial layer 100-2) for realizing the high breakdown voltage characteristics and the extended drain region 101 and the semiconductor substrate. The high concentration layer (high concentration semiconductor substrate 100-1) constitutes a semiconductor substrate. As a result, it is possible to realize a semiconductor device that can reduce the on-resistance and improve the switching characteristics when the gate is off while ensuring a high breakdown voltage.

  As a modification of the first embodiment, the semiconductor device according to the present invention may be configured as shown in FIG. 1B. The configuration shown in FIG. 1B is a configuration in which the high concentration drain adjacent region 110 is connected to the drain electrode 112 and the high concentration drain region 109 is connected to the contact electrode 113. Further, a resistor 114 is inserted between the drain electrode 112 and the contact electrode 113.

  In the configuration shown in FIG. 1B, when the channel flow region of the MOS transistor becomes conductive, the electron current of the MOS transistor flows below the top region 103 and below the high concentration drain adjacent region 110 and passes through the high concentration drain region 109. It reaches the drain electrode 112. At this time, when the electron current of the MOS transistor increases and the voltage drop below the high concentration drain adjacent region 110 reaches 0.7 (V), the high concentration drain adjacent region 110 becomes the emitter, and the high concentration drain adjacent region 110. A PNP bipolar transistor having the lower extended drain region 101 as a base and the substrate contact region 105 as a collector is turned on. As a result, minority carriers are injected from the high concentration drain adjacent region 110 into the extended drain region 101, and the bipolar operation of the L-IGBT is started. Therefore, the configuration shown in FIG. 1B can operate as an L-IGBT as in FIG. 1A, and the same effect as in FIG. 1A can be obtained.

(Second Embodiment)
Next, a semiconductor device according to a second embodiment of the present invention will be described. FIG. 2A is a cross-sectional view of a semiconductor device according to the second embodiment of the present invention. The second embodiment is the same as the configuration shown in FIG. 1A except that the structure of the top region 103 inside the extended drain region 101 is different from that of the first embodiment. Therefore, in the following, the structure inside the extended drain region 101 will be mainly described.

  As shown in FIG. 2A, a p-type epitaxial layer 100-2 (impurity concentration: about 1014 / cm3) is formed on a p-type high concentration semiconductor substrate 100-1 (impurity concentration: about 1018 / cm3 to about 1020 / cm3). About 10 15 / cm 3), and after the n-type impurity is introduced, thermal diffusion is performed to form an extended drain region 101 made of an n-type impurity layer having a depth of about 5 to 15 μm. This is the same as in the first embodiment. In the second embodiment, a p-type buried region 103 </ b> A is formed inside the extended drain region 101. Further, a plurality of p-type buried regions 103B and the like are formed below the buried region 103A at intervals in the vertical direction. In FIG. 2A, only the embedded regions 103A and 103B are shown, but the number of embedded regions may be any number. These buried regions are electrically connected to the epitaxial layer 100-2 or are in a floating state.

  In the case of the second embodiment, the electron current of the MOS transistor is different from that of the first embodiment in that the current flows by dividing between a plurality of buried regions. However, the mechanism for performing a bipolar operation as an L-IGBT when minority carriers flow from the high-concentration drain adjacent region 110 is the same as in the first embodiment. Therefore, also in the second embodiment, as in the first embodiment, the impedance between the extended drain region 101 and the high-concentration semiconductor substrate 100-1 is reduced by forming the epitaxial layer 100-2 on the semiconductor substrate. In addition, it is possible to reduce the on-resistance and improve the switching characteristics when off.

  As described above, also in the second embodiment, the same effect as that of the first embodiment can be obtained. Also in the second embodiment, a modification similar to the first embodiment as shown in FIG. 2B can be considered. Also in the configuration shown in FIG. 2B, the same effect as in the first embodiment can be obtained.

  The semiconductor device of the present invention is particularly useful as a power semiconductor device and the like because it can operate at high speed and satisfies high breakdown voltage characteristics.

Sectional drawing of the semiconductor device which concerns on 1st Embodiment Sectional drawing of the semiconductor device which concerns on the modification of 1st Embodiment. Sectional drawing of the semiconductor device which concerns on 2nd Embodiment Sectional drawing of the semiconductor device which concerns on the modification of 2nd Embodiment Sectional view of a conventional semiconductor device

Explanation of symbols

100 p-type semiconductor substrate 100-1 p-type high-concentration semiconductor substrate 100-2 p-type epitaxial layer 101 n-type extended drain region 102 p-type anti-punch-through region 103 p-type top region 103A p-type first region 1 buried region 103B p type second buried region 104 n type source region 105 p type substrate contact region 106 gate insulating film 107 gate electrode 108 insulating film 109 n type high concentration drain region 110 p type high concentration Drain adjacent region 111 Source electrode 112 Drain electrode 113 Contact electrode 114 with n-type high concentration drain region Resistance

Claims (3)

A first conductivity type semiconductor substrate in which a low-concentration epitaxial layer is formed on the high-concentration layer;
An extended drain region of a second conductivity type formed on the surface portion of the epitaxial layer;
A high-concentration drain region of the second conductivity type formed on the surface of the extended drain region;
A source region of a second conductivity type formed at a predetermined distance from the extended drain region in the surface portion of the epitaxial layer;
A top region of a first conductivity type formed in a portion between the high-concentration drain region and the source region on the surface of the extended drain region and electrically connected to the semiconductor substrate;
Formed in a surface portion of the extended drain region and formed in a portion between the high concentration drain region and the top region and adjacent to the high concentration drain region; And a first conductivity type high concentration drain adjacent region connected to each other. A first conductivity type semiconductor substrate in which a low-concentration epitaxial layer is formed on the high-concentration layer;
An extended drain region of a second conductivity type formed on the surface portion of the epitaxial layer;
A high-concentration drain region of the second conductivity type formed on the surface of the extended drain region;
A source region of a second conductivity type formed at a predetermined distance from the extended drain region in the surface portion of the epitaxial layer;
One or more buried regions of a first conductivity type formed in a portion between the high concentration drain region and the source region inside the extended drain region and electrically connected to the semiconductor substrate;
Formed in a surface portion of the extended drain region and formed in a portion between the high concentration drain region and the buried region and adjacent to the high concentration drain region; And a first conductivity type high concentration drain adjacent region connected to each other. A drain electrode connected to the high concentration drain adjacent region;
A contact electrode connected to the high concentration drain region;
The semiconductor device according to claim 1, further comprising a resistor inserted between the drain region and the contact electrode.

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