JPH04343475A - Insulating gate type bipolar transistor - Google Patents

Abstract

PURPOSE:To provide an insulating gate type bipolar transistor that allows faster switching at turn off by annihilating the accumulated carrier on the base layer with an ON voltage dropped. CONSTITUTION:A p type base layer 3, n<+> type source layer 4 and p<+> type drain layer 5 are formed on the surface of an n<-> base layer 2 located on a silicon substrate. On the surface of the n<-> type base layer 2, an electrode 8 is formed through a gate insulating film 7, while a source electrode 9 is arranged so that it simultaneously contact both the p type base layer 3 and n<+> type source layer 4, and a drain electrode 10 is arranged contacted with a p<+> type drain layer 5. N type buffer layers 11, 12 and 13 are selectively formed on the surface of the n<->type base layer 2 locating between the p type base layer 3 and p<+> type drain layer 5, and the drain electrode 10 is contacted with these n<+> type buffers 11, 12 and 13 through a resistor 16.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate bipolar transistor.

0002

[Prior art] Insulated gate bipolar transistor (
In conductivity modulated MOSFET), JP-A-2-13
Japanese Patent No. 8774 discloses a technique for improving switching characteristics at turn-off with an anode short configuration. As shown in FIG. 15, this forms a diffusion layer 27 in the drain layer 26 with a conductivity type different from that of the drain region.
A drain electrode 28 is brought into contact with this diffusion layer 27.

0003

However, in this case, the injection of holes from the drain layer 26 to the base layer 29 is suppressed, and the effect of conduction modulation cannot be obtained sufficiently, resulting in an increase in the on-state voltage. An object of the present invention is to provide an insulated gate bipolar transistor that can quickly eliminate carriers accumulated in the base layer while keeping the on-state voltage low, thereby increasing the switching speed at turn-off.

0004

[Means for Solving the Problems] The present invention includes a semiconductor substrate, a base layer of a first conductivity type selectively formed on the surface of the semiconductor substrate, and a base layer of a first conductivity type selectively formed on the surface of the base layer. a source layer of a second conductivity type; a drain layer of a first conductivity type formed on the surface of the semiconductor substrate; a gate electrode formed on the surface of the semiconductor substrate with a gate insulating film interposed therebetween; In an insulated gate bipolar transistor having a source electrode disposed in simultaneous contact with a base layer and a drain electrode disposed in contact with the drain layer, a semiconductor layer between the base layer and the drain layer is provided. The gist is an insulated gate bipolar transistor in which a second conductivity type diffusion layer is selectively formed on the surface of a substrate, and the drain electrode is in contact with this diffusion layer via a resistor.

[0005]

[Effect] When a large current flows during turn-on and the carrier density in the base layer becomes higher than the impurity concentration in the drain layer, the injection efficiency of the drain layer decreases, but the structure has a structure in which electrons are bypassed to the drain by the diffusion layer. Therefore, the carrier density does not become excessively high, and the drop in the injection effect of the drain layer can be suppressed. Furthermore, at turn-off, when the inversion layer in the channel region under the gate electrode disappears and no electron injection from the source layer occurs, the electrons accumulated in the device are transferred to the diffusion layer in the base layer until the injection becomes low. The holes pass through the base layer to the source layer. Therefore,
Accumulated carriers are dissipated via the short-circuit resistor, and the switching speed at turn-off is increased.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment embodying the present invention will be described below with reference to the drawings. FIG. 1 shows a plan view of a horizontal insulated gate bipolar transistor (conductivity modulation type MOSFET), and FIG. 2 shows a cross section taken along line AA in FIG. FIG. 3 shows a cross section taken along line BB in FIG.

A high resistance n- type base layer 2 is formed by epitaxial growth on an n+ type silicon substrate 1, constituting a semiconductor substrate. Note that the silicon substrate 1 is p-
Alternatively, it may be p+ type. A p-type base layer 3 is formed on the surface of the n--type base layer 2, and an n+-type source layer 4 is selectively formed therein. In addition, the n- type base layer 2
A p+ type drain layer 5 is formed on the surface. Then, the n+ type source layer 4 and the n+ type source layer 4 in the p type base layer 3
- A region sandwiched between the mold base layers 2 is used as a channel region 6, and a gate electrode 8 is arranged on the channel region 6 with a gate insulating film 7 interposed therebetween. The source electrode 9 is arranged so as to be in contact with the n+ type source layer 4 and the p type base layer 3 at the same time, and the drain electrode 10 is in contact with the p+ type drain layer 5.

[0008] Furthermore, p on the surface of the n- type base layer 2
Between the type base layer 3 and the p+ type drain layer 5, n+ type buffer layers 11, 12, and 13 as island-shaped diffusion layers are selectively formed in a line. Each n+ type buffer layer 1
1, 12, and 13 are formed in a rectangular shape whose length and width are W1 and W2, and are spaced apart from the p-type base layer 3 by a distance La and from the p+-type drain layer 5 by a distance Lb. Also, the distance L between the n+ type buffer layers 11 and 12 is
The n+ type buffer layers 12 and 13 are separated by a distance Lw2. The n+ type buffer layers 11, 12, and 13 are electrically connected by a wiring material 14 and have the same potential.

Furthermore, an n+ type layer 15 for contact is formed on the surface of the n- type base layer 2.
The + type layer 15 is connected to the n + type buffer layers 11, 12, and 13 via a bulk resistor 16 (see FIG. 3). The bulk resistor 16 is connected to the drain electrode 10. In other words, these wired n+ type buffer layers 11,
12 and 13 are the spread bulk resistance 1 of the n- type base layer 2
6 and is connected to the drain electrode 10 via the n+ layer 15 for contact.

[0010] Note that the n+ type buffer layers 11, 12, 13
The arrangement on the n- type base layer 2 can be formed using a two-dimensional mask pattern, and the area (=W1/W2) and distance Lb of the n+-type buffer layers 11, 12, 13 are related to the carrier ejection ability. It is. Moreover, the n+ type buffer layer 11,
By appropriately setting the distances Lw1 and Lw2 between 12 and 13, the carrier conduction path from the source to the drain is not obstructed. Furthermore, since the distance La is related to the breakdown voltage of this element, it is determined by the design of the DS breakdown voltage.

Next, the operation of the insulated gate bipolar transistor constructed as described above will be explained. The turn-on operation is performed by applying a positive bias to the gate electrode 8 with respect to the source electrode 9, inverting the channel region 6, and injecting electrons from the source electrode 9 into the n-type base layer 2. A part of the electrons injected into the n- type base layer 2 is transferred to the selectively formed n+ type buffer layer 11.
, 12, and 13, and the rest is injected into the p+ type drain layer 5. These n+ type buffer layers 11, 12, 13
The electrons flow into the drain electrode 10 via the bulk resistor 16, and the electrons injected into the p+ type drain layer 5 cause holes to be injected into the n- type base 2. This causes conductivity modulation within the n- type base layer 2. At this time, the n+ type buffer layers 11, 12, and 13 are arranged apart from the p+ type drain layer 5, and the bulk resistor 16
Since they are connected at
It is lowered relative to the type drain layer 5.

Normally, when a large current flows and the carrier density in the n- type base layer 2 becomes higher than the impurity concentration in the p+ type drain layer 5, the injection efficiency of the p+ type drain layer 5 decreases. Buffer layers 11, 12, 13
Since it has a structure in which electrons are bypassed to the drain, the carrier density does not become excessively high, and the drop in the injection effect of the p+ type drain layer 5 is suppressed. This means that p+
Unlike the anode short structure in which the current gain of the pnp transistor consisting of the drain layer 5 to n- type base layer 2 to the p-type base layer 3 is zero, as shown in FIG.
An electronic current flows through the bulk resistor 16 and the pnp transistor T
r1 emitter (p+ type drain layer 5) to base (n
- The structure has a bias resistance R between the mold base layer 2).

On the other hand, the turn-off operation is performed by applying a negative bias or zero bias to the gate electrode 8. As a result, the inversion layer of the channel region 6 under the gate electrode 8 disappears, and electron injection from the n- type source layer 2 is eliminated. In this state, the electrons accumulated in the device are discharged to the n+ type buffer layers 11, 12, 13 in the n- type base layer 2 until the injection becomes low, and the holes pass through the p-type base layer 3. It exits to the source electrode 9. That is, the operation of dissipating the accumulated carriers is performed via the short-circuit resistor R between the base and emitter of the pnp transistor Tr1 described above, and the switching speed at turn-off is increased.

As described above, in this embodiment, n+ type buffer layers 11 and 12 are selectively formed on the surface of the semiconductor substrate between the p type base layer 3 and the p+ type drain layer 5 in the horizontal insulated gate bipolar transistor. , 13 were formed, and the drain electrode 10 was contacted to the n+ type buffer layers 11, 12, 13 via a resistor 16. As a result, at turn-on, a large current flows and the n- type base layer 2
When the carrier density in the p+ type drain layer 5 becomes higher than the impurity concentration in the p+ type drain layer 5, the injection efficiency of the p+ type drain layer 5 decreases, but since the n+ type buffer layers 11, 12, and 13 have a structure in which electrons are bypassed to the drain. The carrier density does not become excessively high, and the drop in the injection effect of the p+ type drain layer 5 can be suppressed. Furthermore, when the inversion layer of the channel region 6 under the gate electrode 8 disappears during turn-off and electron injection from the n- type source layer 2 is eliminated, the electrons accumulated in the device remain n- until the injection becomes low. The holes are discharged to the n+ type buffer layers 11, 12, and 13 in the base layer 2, and the holes pass through the p type base layer 3 to the n+ type source layer 4. In other words, the accumulated carriers are erased via the short-circuit resistor 16, and the switching speed at turn-off is increased.

It should be noted that the present invention is not limited to the above-mentioned embodiment, but may be implemented as shown in FIGS. 5 and 6, for example. In other words, the n+ type buffer layer 17 is connected to the p type base layer 3 (
The n+ type source layer 4 and the gate electrode 8 are disposed opposite each other at a distance L from each other. The n+ type buffer layer 17 is wired to have the same potential as the n+ type buffer layers 11, 12, and 13.

Then, when a negative bias or zero bias is applied to the gate electrode 8, the transistor is turned off, and the potential of the drain electrode 10 is increased relative to the source electrode 9, as shown in FIG. A depletion layer spreads between the base layer 3 and the n- type base layer 2 so as to cancel out the external electric field. At this time, when the drain-source potential increases, the depletion layer becomes n
- spreads in the mold base layer 2, but as shown in FIG.
When the + type buffer layer 17 exists, the expansion of the depletion layer is suppressed in the n + type buffer layer 17, and the p type base layer 3
Junction critical electric field Ec between and n- type base layer 2
If you cross that junction, it will break down. Since the breakdown current flows from the drain to the source side through the resistor 16, the potential of the n+ type buffer layer 17 is lower than that of the drain. In this way, the arrangement position of the n+ type buffer layer 17 (adjustment of L dimension)
This allows the breakdown voltage to be adjusted appropriately. Note that since the n+ type buffer layer 17 is connected to the n+ type buffer layers 11 to 13 by wiring, the p type drain and the n− base layer are biased in the forward direction.

FIG. 9 shows this in an equivalent circuit. That is, it becomes a potential clamp circuit between DS and S. In addition, in the potential clamp circuit, the reference voltage is the Zener diode part Dz, and the main clamp circuit is the p+
Since the pnp transistor Tr1 is composed of the drain layer 5, the n-type base layer 2, and the p-type base layer 3, the load applied to the resistor R is small.

In another embodiment, as shown in FIG. 10, the shape of the n+ type buffer layers 17, 18, and 19 may not be rectangular but may be circular. In addition, in FIG. 10, n+ type buffer layers 20 and 21 are arranged so as to capture electrons that are injected into the n- type base layer 2 from the n+ type source layer 4 and try to flow out of the channel. are doing.

Furthermore, as shown in FIG. 11, the n- type buffer layers 22 do not need to be arranged in a row, but the n+ type buffer layers 22 may be arranged randomly on the n- type base layer 2 to prevent the carriers from flowing. The sampling efficiency may be increased. Furthermore,
The n+ type buffer layer is connected to the drain electrode via a resistor, and the resistor can be formed by using the n+ type buffer layer 23 as shown in FIG. 12, or by using the n+ type buffer layer 23 as shown in FIG. A polysilicon resistor 24 may be used, or an external resistor 25 may be used as shown in FIG.

[0020]

[Effects of the Invention] As detailed above, according to the present invention,
It exhibits the excellent effect of rapidly extinguishing carriers accumulated in the base layer while keeping the on-state voltage low, thereby increasing the switching speed at turn-off.

[Brief explanation of the drawing]

FIG. 1 is a plan view of an insulated gate bipolar transistor according to an example.

FIG. 2 is a sectional view taken along line AA in FIG. 1;

FIG. 3 is a sectional view taken along line BB in FIG. 1;

FIG. 4 is an equivalent circuit of the insulated gate bipolar transistor of the example.

FIG. 5 is a plan view of another example of an insulated gate bipolar transistor.

FIG. 6 is a sectional view taken along line CC in FIG. 5;

FIG. 7 is a diagram for explaining the spread of an electric field.

FIG. 8 is a diagram for explaining the spread of an electric field.

FIG. 9 is an equivalent circuit of another example of an insulated gate bipolar transistor.

FIG. 10 is a plan view of another example of an insulated gate bipolar transistor.

FIG. 11 is a plan view of another example of an insulated gate bipolar transistor.

FIG. 12 is a cross-sectional view showing the arrangement structure of resistors.

FIG. 13 is a cross-sectional view showing the arrangement structure of resistors.

FIG. 14 is a cross-sectional view showing the arrangement structure of resistors.

FIG. 15 is a plan view of a conventional insulated gate bipolar transistor.

[Explanation of symbols]

1 Silicon substrate constituting a semiconductor substrate 2 N- type base layer 3 constituting a semiconductor substrate P-type base layer 4 N+ type source layer 5 P+ type drain layer 7 Gate insulating film 8 Gate electrode 9 Source electrode 10 Drain electrode 11 Diffusion layer N+ type buffer layer 12 as a diffusion layer N+ type buffer layer 13 as a diffusion layer N+ type buffer layer 16 as a diffusion layer Bulk resistance

Claims (1)

[Claims] 1. A semiconductor substrate, a base layer of a first conductivity type selectively formed on a surface of the semiconductor substrate, and a source layer of a second conductivity type selectively formed on a surface of the base layer. , a drain layer of a first conductivity type formed on the surface of the semiconductor substrate, a gate electrode formed on the surface of the semiconductor substrate via a gate insulating film, and disposed in simultaneous contact with the source layer and the base layer. In an insulated gate bipolar transistor having a source electrode provided therein and a drain electrode provided in contact with the drain layer, selectively applied to the surface of the semiconductor substrate between the base layer and the drain layer. An insulated gate bipolar transistor characterized in that a diffusion layer of a second conductivity type is formed, and the drain electrode is in contact with the diffusion layer via a resistor.