JP4241158B2

JP4241158B2 - Semiconductor device

Info

Publication number: JP4241158B2
Application number: JP2003112592A
Authority: JP
Inventors: 健一大塚; 陽一郎樽井; 昌之今泉; 博司杉本; 哲也高見
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 2003-04-17
Filing date: 2003-04-17
Publication date: 2009-03-18
Anticipated expiration: 2023-04-17
Also published as: JP2004319815A

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置に関し、特に高耐圧でかつオン抵抗が低くかつ素子特性の劣化が生じにくい半導体装置に関するものである。
【０００２】
【従来の技術】
従来の半導体装置の一種である縦型ＭＯＳＦＥＴでは、例えば、特許文献１でで開示されるように、デプレッション領域をドリフト層と同様にエピタキシャル成長で形成し、ベース領域およびソース領域をイオン注入で形成していた（特許文献１中の図１）。あるいは、ベース領域をドリフト層と同様にエピタキシャル成長で形成し、デプレッション領域およびソース領域をイオン注入で形成していた（特許文献１中の図６）。
【０００３】
【特許文献１】
特許公報第３２０６７２７号
【０００４】
【発明が解決しようとする課題】
従来の縦型ＭＯＳＦＥＴにおけるデプレッション領域の長さとドーピング濃度に関しては、デプレッション領域の長さに応じてオン抵抗を増加させないためのドーピング濃度の下限および素子耐圧を確保するための上限が存在する。特に、素子寸法の微細化を図った素子構造では、デプレッション領域のドーピング高不純物濃度化による低オン抵抗化、素子耐圧が低下しないためのチャネル領域下の低不純物濃度化が必須であった。しかしながら、特許文献１中の図１における素子構造では、ドリフト層とデプレッション領域が単一のエピタキシャル結晶層で形成されており、同一のドーピング濃度では必要な素子特性に対する最適設計が困難であるという問題があった。
【０００５】
一方、特許文献１中の図６における素子構成によれば、ドリフト層とデプレッション領域とはドーピングによって不純物濃度をそれぞれ独立に設定できるものの、ゲート電極下の高電界が印加されるデプレッション領域はエピタキシャル結晶成長したｐ型ベース領域に対して高不純物濃度のｎ型不純物をイオン注入する手段によって形成されるため、イオン注入の際、デプレッション領域に導入される結晶欠陥によって素子特性の劣化が生じる問題があった。
【０００６】
この発明は、上記のような問題点を解決するためになされたものであり、高素子耐圧・低オン抵抗でかつ素子特性の劣化が生じにくい半導体装置を得ることを目的とする。
【０００７】
【課題を解決するための手段】
この発明に係る半導体装置は、第１導電型の半導体基板と、上記半導体基板上に形成された第１導電型のドリフト層と、上記ドリフト層上に形成された第１導電型の第１半導体層と、上記第１半導体層上に形成された第１導電型の第２半導体層と、上記第１および第２半導体層中に設けられ所定の間隔で離間した複数の第２導電型のベース領域と、上記各ベース領域内にそれぞれ選択的に形成された第１導電型のソース領域と、上記各ソース領域の一部の表面上にそれぞれ設けられたソース電極と、上記各ソース領域の一部の表面および上記ソース領域間の上記半導体層の表面にゲート絶縁膜を介して設けられたゲート電極と、を備え、上記第１半導体層および上記第２半導体層がエピタキシャル成長によって形成された結晶層であり、かつ上記ドリフト層の不純物濃度Ｎ_１、上記第１半導体層の不純物濃度Ｎ _２、上記第２半導体層の不純物濃度Ｎ _３が、Ｎ _３＜Ｎ _１＜Ｎ _２の関係を有することとした。
【０００８】
【発明の実施の形態】
実施の形態１．
本発明の実施の形態１による半導体装置の断面図を図１に示す。ｎ型半導体基板（第１導電型の半導体基板）１上に、層厚３〜３０μｍのｎ型ドリフト層（第１導電型のドリフト層）２、層厚０．３〜１．０μｍでｎ型ドリフト層２よりもｎ型不純物が高濃度にドーピングされたｎ型第１半導体層（第１導電型の第１半導体層）３、層厚０．３〜１．０μｍでｎ型ドリフト層２およびｎ型第１半導体層３よりもｎ型不純物が低濃度にドーピングされたｎ型第２半導体層（第１導電型の第２半導体層）４、が順次エピタキシャル成長によって形成されている。なお、以下、ｎ型第１半導体層３とｎ型第２半導体層４を併せてｎ型半導体層（第１導電型の半導体層）と称する。
【０００９】
所定の間隔に離間された層厚０．５〜１．５μｍの２つのｐ型ベース領域（第２導電型のベース領域）５がｎ型半導体層中に選択的に形成され、さらに、層厚０．２〜０．４μｍのｎ型ソース領域（第１導電型のソース領域）６が各ｐ型ベース領域５中にそれぞれ選択的に形成されている。ｐ型ベース領域５におけるｎ型半導体基板１側のｐｎ接合界面は、ｎ型ドリフト層２あるいはｎ型第２半導体層４と接する界面もしくはｎ型第１半導体層３中に形成されている。ｎ型ソース領域６とｐ型ベース領域５とｎ型第２半導体層４とからなるウエハ表面にゲート絶縁膜７、ゲート電極８、絶縁膜９で構成されたゲート構造が設けられている。
【００１０】
また、各ｎ型ソース領域６の表面上の一部に各ソース電極１０、ｎ型半導体基板１の裏面側にドレーン電極１１がそれぞれ設けられている。半導体装置におけるＭＯＳＦＥＴ部の周囲領域、すなわち、２つのｐ型ベース領域５を取り囲む領域のｎ型半導体層中には、一端が各ｐ型ベース領域５に接するようにしてｐ型ガードリング領域１２が設けられている。かかるｐ型ガードリング領域１２はウエハ表面に対して水平方向のｐｎ接合がｎ型第１半導体層３とｎ型第２半導体層４との界面近傍になるように設けられている。
【００１１】
以下、本実施の形態の半導体装置の動作について説明する。ゲート電極８にゲート電圧を印加するとゲート電極８直下のｐ型ベース領域５の表面近傍にチャネルが誘起され、ｎ型ソース領域６とｎ型第２半導体層４間が電気的に導通する。これによって、ソース電極１０からｐ型ソース領域６、ｎ型ベース領域５の表面近傍のチャネル領域、ｎ型第２半導体層４、ｎ型第１半導体層３、ｎ型ドリフト層２、ｎ型半導体基板１、を経てドレーン電極１１へと流れる電流経路ができる。かかる電流は、ゲート電極８に印加されるゲート電圧によって制御され、例えばスイッチング動作等が可能となる。なお、ゲート電極８直下のｎ型第２半導体層４やｎ型第１半導体層３にはデプレッション領域が形成される。
【００１２】
次に、上述の各層の不純物濃度について説明する。本実施の形態の半導体装置では、ｎ型ドリフト層２の不純物濃度をＮ_１，ｎ型第１半導体層３の不純物濃度をＮ_２、ｎ型第２半導体層４の不純物濃度をＮ_３とすると、
Ｎ_３＜Ｎ_１＜Ｎ_２（１）
の関係を有する。このような構成では、ゲート電極８直下のデプレッション領域に相当するｎ型第２半導体層４の不純物濃度はｎ型ドリフト層２より低濃度であるため、ゲート電圧印加の際に空乏領域が層厚方向に深く伸長する結果、素子耐圧は従来の素子構造に比べて格段に向上する。一方、ｎ型ドリフト層２とｎ型第２半導体層４との間に設けられたｎ型第１半導体層３の不純物濃度はｎ型ドリフト層２より高濃度であるため、かかる領域の抵抗が従来に比べて減少する結果、オン抵抗の実効的な低減が実現できる。
【００１３】
以下に、各層毎の好適な不純物濃度を具体的に説明する。ｎ型ドリフト層２の不純物濃度Ｎ_１は２．０×１０^１５ｃｍ^−３以上５.０×１０^１６ｃｍ^−３以下の範囲、ｎ型第１半導体層３はｎ型ドリフト層２の不純物濃度Ｎ_１に対して１．２〜３．０倍、つまり１．２Ｎ_１以上３．０Ｎ_１以下の範囲の不純物濃度、ｎ型第２半導体層４はｎ型ドリフト層２の不純物濃度Ｎ_１に対して０．３〜０．７倍、つまり０．３Ｎ_１以上０．７Ｎ_１以下の範囲が好適である。なお、かかる各不純物濃度の範囲内では、上述した（１）式を満足している。また、ｐ型ベース領域５は５．０×１０^１７ｃｍ^−３以上２．０×１０^１８ｃｍ^−３以下の範囲の不純物濃度、ｎ型ソース領域６は１．０×１０^１９ｃｍ^−３以上の不純物濃度がそれぞれ好適である。
【００１４】
本実施の形態の素子構造では、チャネル領域長、つまり、ｐ型ベース領域５を介して対向するゲート電極８直下のｎ型第２半導体層４とｎ型ソース領域６との間の距離Ｌ_ｃｈは、１〜３μｍが好適である。また、デプレッション領域の幅、つまり、ゲート電極８直下のｎ型第２半導体層４のゲート長方向における幅２Ｌ_ｄは２〜７μｍが好適である。もっともＬ_ｃｈ，Ｌ_ｄはＭＯＳＦＥＴ部全体の寸法に依存するので、より普遍的には、Ｌ_ｄ／Ｌ_ｃｈが０．５〜３．０の場合に前述の優れた素子特性が得られる。
【００１５】
以上、本実施の形態の素子構造では、ＭＯＳＦＥＴ部におけるデプレッション領域の形成において、ｎ型ドリフト層２より高不純物濃度のｎ型第１半導体層３を導入することにより層厚方向の実効的な抵抗成分が減少するため動作時のオン抵抗の低減が可能となる一方、ゲート電極８直下に低不純物濃度のｎ型第２半導体層４を導入したため、従来の素子構造に比べて空乏領域は層厚方向に一層伸長するようになるので、素子耐圧の低下を効果的に防止できる。さらに、ゲート電極８直下でデプレッション領域に相当する部分はエピタキシャル成長によって形成されたｎ型第２半導体層４で構成されているため、かかる領域をイオン注入によって形成した従来の素子構造に比べて結晶欠陥密度が顕著に低減されるので、素子特性の劣化も格段に改善される。
【００１６】
また、素子周囲部分においてはガードリング領域１２の層厚方向のｐｎ接合が高不純物濃度のｎ型第１半導体層３中に、ウエハ表面に対して水平方向のｐｎ接合がｎ型第１半導体層３とｎ型第２半導体層４との界面近傍にそれぞれ形成され、それぞれの方向において不純物の濃度勾配が緩やかになるため、ｐ型ベース領域５の端部で生じる電界集中がガードリング領域１２に伸びる形で緩和され、終端構造として有効に機能するので、リーク電流の小さい優れた半導体装置が得られる。
【００１７】
実施の形態２．
本発明の実施の形態２による半導体装置の断面図を図２に示す。実施の形態１の半導体装置との構造上の相違は、実施の形態１の素子構造ではｎ型第１半導体層３とｎ型第２半導体層４の２つで構成されていた半導体層が、単一のｎ型半導体層４ａとなっている点である。ｎ型半導体層４ａの不純物濃度Ｎ_ｓはｎ型ドリフト層２の不純物濃度Ｎ_１よりも低不純物濃度のドーピングに設定されている。すなわち、
Ｎ_ｓ＜Ｎ_１（２）
の関係が成立する。
【００１８】
実施の形態１の半導体装置ではオン抵抗を低減するためにｎ型ドリフト層２よりも高不純物濃度にドーピングされたｎ型第１半導体層３を導入したが、本実施の形態の半導体装置ではｎ型ドリフト層２の不純物濃度Ｎ_１でもオン抵抗への影響が少ない場合に対応したものである。このような素子構成によれば、ゲート電極８直下のデプレッション領域の形成において、低不純物濃度であるｎ型半導体層４ａを導入したことで、実用上充分な素子耐圧を確保することができる。
【００１９】
実施の形態３．
本発明の実施の形態３による半導体装置の断面図を図３に示す。実施の形態２の半導体装置との構造上の相違は、実施の形態２のｎ型半導体層４ａに代えてｎ型ドリフト層２より不純物濃度の高いｎ型半導体層３ａを設け、ＭＯＳＦＥＴ部の周辺部分のｎ型半導体層３ａ上にさらにｎ型第３半導体層（第１導電型の第３半導体層）１３を形成し、また、ガードリング領域１２ａがｎ型第３半導体層１３を貫通してｎ型半導体層３ａ中にその一端をベース領域５に接するように形成されている点にある。なお、ｎ型第３半導体層１３の不純物濃度はｎ型ドリフト層２およびｎ型半導体層３ａよりも低濃度に設定されている。
【００２０】
実施の形態２の素子構造では素子耐圧を確保するためにｎ型ドリフト層２よりも低不純物濃度にドーピングされたｎ型半導体層４ａをＭＯＳＦＥＴ部に導入したが、本実施の形態の素子構造ではｎ型ドリフト層２よりも高不純物濃度でドーピングされたｎ型半導体層３ａの不純物濃度設定でも、素子耐圧への影響が少ない場合に対応する。このような素子構成によれば、ｎ型ドリフト層２より高不純物濃度であるｎ型半導体層３ａを導入することにより、ｎ型半導体層３ａ中へのデプレッション領域形成時におけるオン抵抗が低減できる。
【００２１】
本実施の形態の素子構造では、ＭＯＳＦＥＴ部の周囲部分のガードリング領域１２ａにおけるウエハ表面に対して水平方向のｐｎ接合は高不純物濃度のｎ型半導体層３ａ内に形成される一方、層厚方向のｐｎ接合は低不純物濃度であるｎ型第３半導体層１３内でベース領域５に接している面と対向する端部に主に形成されるため、ｐ型ベース領域５の端部での電界集中がガードリング領域１２ａに伸びる形で緩和され、終端構造として有効に機能するので、リーク電流が小さい優れた半導体装置が得られる。
【００２２】
実施の形態４．
本発明の実施の形態４による半導体装置の断面図を図４に示す。実施の形態４の半導体装置では実施の形態１で示したＭＯＳＦＥＴ部に隣接して、ｎ型第２半導体層４上にベース領域５とも接続された形でアノード電極１４が形成され、ドレーン電極１１をカソード電極としたショットキダイオード領域がオンチップ化されている。かかる素子構造では、ショットキダイオード領域でもアノード電極１４は低不純物濃度化されたｎ型第２半導体層４と接している結果、ショットキダイオードの逆方向リーク電流を低減することができる。
【００２３】
本実施の形態の半導体装置では、実施の形態１で示した優れた特性を具備するＭＯＳＦＥＴ部に併せて、逆方向リーク電流の小さいショットキダイオードも同一半導体基板上でオンチップ化されているので、より高機能の半導体装置を得ることができる。
【００２４】
なお、上述の各実施の形態では、ｎ型の導電型を第１導電型、ｐ型の導電型を第２導電型としたが、逆の導電型の場合でも同様の効果を発揮する。
【００２５】
また、上述の各実施の形態では、半導体装置を構成する結晶材料については特に言及しなかったが、具体的な結晶材料としては、例えばシリコン（Ｓｉ）や炭化珪素（ＳｉＣ）が挙げられる。
【００２６】
【発明の効果】
本発明に係る半導体装置では、第１導電型の半導体基板と、上記半導体基板上に形成された第１導電型のドリフト層と、上記ドリフト層上に形成された第１導電型の第１半導体層と、上記第１半導体層上に形成された第１導電型の第２半導体層と、上記第１および第２半導体層中に設けられ所定の間隔で離間した複数の第２導電型のベース領域と、上記各ベース領域内にそれぞれ選択的に形成された第１導電型のソース領域と、上記各ソース領域の一部の表面上にそれぞれ設けられたソース電極と、上記各ソース領域の一部の表面および上記ソース領域間の上記半導体層の表面にゲート絶縁膜を介して設けられたゲート電極と、を備え、上記第１半導体層および上記第２半導体層がエピタキシャル成長によって形成された結晶層であり、かつ上記ドリフト層の不純物濃度Ｎ_１、上記第１半導体層の不純物濃度Ｎ _２、上記第２半導体層の不純物濃度Ｎ _３が、Ｎ _３＜Ｎ _１＜Ｎ _２の関係を有することとしたので、実用上充分な素子耐圧を有し、かつ素子特性の劣化が生じにくい半導体装置を容易に得られる。
【図面の簡単な説明】
【図１】実施の形態１による半導体装置の断面図である。
【図２】実施の形態２による半導体装置の断面図である。
【図３】実施の形態３による半導体装置の断面図である。
【図４】実施の形態４による半導体装置の断面図である。
【符号の説明】
１ｎ型半導体基板（第１導電型の半導体基板）、２ｎ型ドリフト層（第１導電型のドリフト層）、３ｎ型第１半導体層（第１導電型の第１半導体層）、３ａｎ型半導体層（第１導電型の半導体層）、４ｎ型第２半導体層（第１導電型の第２半導体層）、４ａｎ型半導体層（第１導電型の半導体層）、５ｐ型ベース領域（第２導電型のベース領域）、６ｎ型ソース領域（第１導電型のソース領域）、７ゲート絶縁膜、８ゲート電極、９絶縁膜、１０ソース電極、１１ドレーン電極、１２、１２ａｐ型ガードリング領域、１３ｎ型第３半導体層（第１導電型の第３半導体層）、１４アノード電極。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor device that has a high breakdown voltage, a low on-resistance, and is unlikely to deteriorate element characteristics.
[0002]
[Prior art]
In a vertical MOSFET that is a kind of conventional semiconductor device, for example, as disclosed in Patent Document 1, a depletion region is formed by epitaxial growth in the same manner as a drift layer, and a base region and a source region are formed by ion implantation. (FIG. 1 in Patent Document 1). Alternatively, the base region is formed by epitaxial growth similarly to the drift layer, and the depletion region and the source region are formed by ion implantation (FIG. 6 in Patent Document 1).
[0003]
[Patent Document 1]
Patent Publication No. 3206727 [0004]
[Problems to be solved by the invention]
Regarding the length of the depletion region and the doping concentration in the conventional vertical MOSFET, there are a lower limit of the doping concentration and an upper limit for ensuring the device breakdown voltage so as not to increase the on-resistance according to the length of the depletion region. In particular, in an element structure in which element dimensions are miniaturized, it is indispensable to reduce the on-resistance by increasing the doping impurity concentration in the depletion region and to reduce the impurity concentration under the channel region so that the element breakdown voltage does not decrease. However, in the element structure in FIG. 1 in Patent Document 1, the drift layer and the depletion region are formed of a single epitaxial crystal layer, and it is difficult to optimally design necessary element characteristics at the same doping concentration. was there.
[0005]
On the other hand, according to the element configuration in FIG. 6 in Patent Document 1, the impurity concentration of the drift layer and the depletion region can be set independently by doping, but the depletion region to which a high electric field under the gate electrode is applied is an epitaxial crystal. Since it is formed by means of ion-implanting high impurity concentration n-type impurities into the grown p-type base region, there is a problem in that device characteristics deteriorate due to crystal defects introduced into the depletion region during ion implantation. It was.
[0006]
The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a semiconductor device having a high element breakdown voltage, a low on-resistance, and hardly causing deterioration of element characteristics.
[0007]
[Means for Solving the Problems]
A semiconductor device according to the present invention includes a first conductivity type semiconductor substrate, a first conductivity type drift layer formed on the semiconductor substrate, and a first conductivity type first semiconductor formed on the drift layer. A first conductive type second semiconductor layer formed on the first semiconductor layer, and a plurality of second conductive type bases provided in the first and second semiconductor layers and spaced apart at a predetermined interval A source region of a first conductivity type selectively formed in each of the base regions, a source electrode provided on a part of the surface of each of the source regions, and one of the source regions. And a gate electrode provided on the surface of the semiconductor layer between the source region and the surface of the semiconductor layer via a gate insulating film, and the first semiconductor layer and the second semiconductor layer are formed by epitaxial growth And Impurity concentration _{N 1} of the serial drift layer, the impurity concentration _{N 2} of the first semiconductor layer, an impurity concentration _{N 3} of the second semiconductor _layer, was to have a relationship N _{3 <N} 1 _{<N 2.}
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
A cross-sectional view of the semiconductor device according to the first embodiment of the present invention is shown in FIG. On an n-type semiconductor substrate (first conductivity type semiconductor substrate) 1, an n-type drift layer (first conductivity type drift layer) 2 having a layer thickness of 3 to 30 μm and an n-type layer having a layer thickness of 0.3 to 1.0 μm N-type first semiconductor layer (first semiconductor layer of the first conductivity type) 3 doped with n-type impurities at a higher concentration than drift layer 2, n-type drift layer 2 having a layer thickness of 0.3 to 1.0 μm, and An n-type second semiconductor layer (first conductivity type second semiconductor layer) 4 doped with an n-type impurity at a lower concentration than the n-type first semiconductor layer 3 is sequentially formed by epitaxial growth. Hereinafter, the n-type first semiconductor layer 3 and the n-type second semiconductor layer 4 are collectively referred to as an n-type semiconductor layer (first conductivity type semiconductor layer).
[0009]
Two p-type base regions (base regions of second conductivity type) 5 having a layer thickness of 0.5 to 1.5 μm spaced apart by a predetermined distance are selectively formed in the n-type semiconductor layer, and the layer thickness is further increased. An n-type source region (first conductivity type source region) 6 of 0.2 to 0.4 μm is selectively formed in each p-type base region 5. The pn junction interface on the n-type semiconductor substrate 1 side in the p-type base region 5 is formed in the interface in contact with the n-type drift layer 2 or the n-type second semiconductor layer 4 or in the n-type first semiconductor layer 3. A gate structure including a gate insulating film 7, a gate electrode 8, and an insulating film 9 is provided on the wafer surface including the n-type source region 6, the p-type base region 5, and the n-type second semiconductor layer 4.
[0010]
In addition, each source electrode 10 is provided on a part of the surface of each n-type source region 6, and a drain electrode 11 is provided on the back side of the n-type semiconductor substrate 1. A p-type guard ring region 12 has one end in contact with each p-type base region 5 in the n-type semiconductor layer in the region surrounding the MOSFET portion in the semiconductor device, that is, the region surrounding the two p-type base regions 5. Is provided. The p-type guard ring region 12 is provided so that the pn junction in the horizontal direction with respect to the wafer surface is near the interface between the n-type first semiconductor layer 3 and the n-type second semiconductor layer 4.
[0011]
The operation of the semiconductor device of this embodiment will be described below. When a gate voltage is applied to the gate electrode 8, a channel is induced in the vicinity of the surface of the p-type base region 5 immediately below the gate electrode 8, and the n-type source region 6 and the n-type second semiconductor layer 4 are electrically connected. Thus, the source electrode 10 to the p-type source region 6, the channel region near the surface of the n-type base region 5, the n-type second semiconductor layer 4, the n-type first semiconductor layer 3, the n-type drift layer 2, and the n-type semiconductor. A current path flows through the substrate 1 to the drain electrode 11. Such a current is controlled by a gate voltage applied to the gate electrode 8, and for example, a switching operation or the like is possible. A depletion region is formed in the n-type second semiconductor layer 4 and the n-type first semiconductor layer 3 immediately below the gate electrode 8.
[0012]
Next, the impurity concentration of each layer described above will be described. In the semiconductor device of the present embodiment, the impurity concentration of the n-type drift layer 2 is N ₁ , the impurity concentration of the n-type first semiconductor layer 3 is N ₂ , and the impurity concentration of the n-type second semiconductor layer 4 is N _3. ,
N ₃ <N ₁ <N ₂ (1)
Have the relationship. In such a configuration, since the impurity concentration of the n-type second semiconductor layer 4 corresponding to the depletion region immediately below the gate electrode 8 is lower than that of the n-type drift layer 2, the depletion region has a layer thickness when the gate voltage is applied. As a result of extending deeply in the direction, the device breakdown voltage is remarkably improved as compared with the conventional device structure. On the other hand, since the impurity concentration of the n-type first semiconductor layer 3 provided between the n-type drift layer 2 and the n-type second semiconductor layer 4 is higher than that of the n-type drift layer 2, the resistance of the region is reduced. As a result of the reduction compared to the prior art, an effective reduction in on-resistance can be realized.
[0013]
Hereinafter, a suitable impurity concentration for each layer will be described in detail. The impurity concentration N ₁ of the n-type drift layer 2 is in the range of 2.0 × 10 ¹⁵ cm ⁻³ or more and 5.0 × 10 ¹⁶ cm ⁻³ or less, and the n-type first semiconductor layer 3 is the impurity concentration of the n-type drift layer 2. 1.2-3.0 times the n _1, i.e. 1.2 n ₁ or 3.0 n ₁ impurity concentration of the range, the n-type second semiconductor layer 4 on the impurity concentration _{n 1} of n-type drift layer 2 On the other hand, a range of 0.3 to 0.7 times, that is, 0.3 N ₁ or more and 0.7 N ₁ or less is preferable. Note that, within the range of each impurity concentration, the above-described expression (1) is satisfied. The p-type base region 5 has an impurity concentration in the range of 5.0 × 10 ¹⁷ cm ⁻³ or more and 2.0 × 10 ¹⁸ cm ⁻³ or less, and the n-type source region 6 has 1.0 × 10 ¹⁹ cm ⁻³ or more. The impurity concentration of each is preferable.
[0014]
In the element structure of the present embodiment, the channel region length, that is, the distance L _ch between the n-type second semiconductor layer 4 and the n-type source region 6 immediately below the gate electrode 8 facing each other with the p-type base region 5 interposed therebetween. Is preferably 1 to 3 μm. The width of the depletion region, i.e., the width 2L _d in the gate length direction of the n-type second semiconductor layer 4 under the gate electrode 8 is suitably 2-7 [mu] m. However, since L _ch and L _d depend on the dimensions of the entire MOSFET part, the above-described excellent device characteristics can be obtained more universally when L _d / L _ch is 0.5 to 3.0.
[0015]
As described above, in the element structure of the present embodiment, in forming the depletion region in the MOSFET portion, the effective resistance in the layer thickness direction is introduced by introducing the n-type first semiconductor layer 3 having a higher impurity concentration than the n-type drift layer 2. The on-resistance during operation can be reduced because the component is reduced. On the other hand, since the n-type second semiconductor layer 4 having a low impurity concentration is introduced immediately below the gate electrode 8, the depletion region has a layer thickness that is smaller than that of the conventional element structure. Since it further extends in the direction, it is possible to effectively prevent a reduction in the element breakdown voltage. Furthermore, since the portion corresponding to the depletion region immediately below the gate electrode 8 is composed of the n-type second semiconductor layer 4 formed by epitaxial growth, the crystal defects are compared with the conventional device structure formed by ion implantation. Since the density is remarkably reduced, the deterioration of the element characteristics is remarkably improved.
[0016]
Further, in the peripheral portion of the element, the pn junction in the layer thickness direction of the guard ring region 12 is in the n-type first semiconductor layer 3 having a high impurity concentration, and the pn junction in the direction horizontal to the wafer surface is the n-type first semiconductor layer. 3 and the n-type second semiconductor layer 4 are formed in the vicinity of the interface, and the concentration gradient of the impurity in each direction becomes gentle, so that the electric field concentration generated at the end of the p-type base region 5 is generated in the guard ring region 12. Since it is relaxed in a stretched manner and effectively functions as a termination structure, an excellent semiconductor device with small leakage current can be obtained.
[0017]
Embodiment 2. FIG.
FIG. 2 shows a cross-sectional view of the semiconductor device according to the second embodiment of the present invention. The difference in structure from the semiconductor device of the first embodiment is that the semiconductor layer composed of the n-type first semiconductor layer 3 and the n-type second semiconductor layer 4 in the element structure of the first embodiment is This is a single n-type semiconductor layer 4a. The impurity concentration N _s of the n-type semiconductor layer 4 a is set to a doping with a lower impurity concentration than the impurity concentration N ₁ of the n-type drift layer 2. That is,
N _s <N ₁ (2)
The relationship is established.
[0018]
In the semiconductor device of the first embodiment, the n-type first semiconductor layer 3 doped with a higher impurity concentration than the n-type drift layer 2 is introduced in order to reduce the on-resistance. However, in the semiconductor device of the present embodiment, n This corresponds to the case where the impurity concentration N ₁ of the type drift layer 2 has little influence on the on-resistance. According to such an element configuration, a practically sufficient element breakdown voltage can be secured by introducing the n-type semiconductor layer 4a having a low impurity concentration in the formation of the depletion region immediately below the gate electrode 8.
[0019]
Embodiment 3 FIG.
FIG. 3 shows a cross-sectional view of the semiconductor device according to the third embodiment of the present invention. The difference in structure from the semiconductor device of the second embodiment is that an n-type semiconductor layer 3a having an impurity concentration higher than that of the n-type drift layer 2 is provided instead of the n-type semiconductor layer 4a of the second embodiment, and the periphery of the MOSFET portion An n-type third semiconductor layer (first conductivity type third semiconductor layer) 13 is further formed on the partial n-type semiconductor layer 3 a, and the guard ring region 12 a penetrates the n-type third semiconductor layer 13. The n-type semiconductor layer 3 a is formed so that one end thereof is in contact with the base region 5. The impurity concentration of the n-type third semiconductor layer 13 is set to be lower than that of the n-type drift layer 2 and the n-type semiconductor layer 3a.
[0020]
In the element structure of the second embodiment, the n-type semiconductor layer 4a doped with a lower impurity concentration than the n-type drift layer 2 is introduced into the MOSFET portion in order to ensure the element breakdown voltage. Even when the impurity concentration of the n-type semiconductor layer 3a doped with a higher impurity concentration than that of the n-type drift layer 2 is set, the influence on the device breakdown voltage is small. According to such an element configuration, by introducing the n-type semiconductor layer 3a having a higher impurity concentration than the n-type drift layer 2, the on-resistance during the formation of the depletion region in the n-type semiconductor layer 3a can be reduced.
[0021]
In the element structure of the present embodiment, the pn junction in the horizontal direction with respect to the wafer surface in the guard ring region 12a around the MOSFET portion is formed in the high impurity concentration n-type semiconductor layer 3a, while the layer thickness direction Since the pn junction is formed mainly at the end facing the surface in contact with the base region 5 in the n-type third semiconductor layer 13 having a low impurity concentration, the electric field at the end of the p-type base region 5 is formed. Since the concentration is relaxed in such a way as to extend to the guard ring region 12a and effectively functions as a termination structure, an excellent semiconductor device with a small leakage current can be obtained.
[0022]
Embodiment 4 FIG.
FIG. 4 shows a cross-sectional view of a semiconductor device according to Embodiment 4 of the present invention. In the semiconductor device of the fourth embodiment, an anode electrode 14 is formed on the n-type second semiconductor layer 4 so as to be connected to the base region 5 adjacent to the MOSFET portion shown in the first embodiment. The Schottky diode region with the cathode electrode as the cathode electrode is on-chip. In such an element structure, the anode electrode 14 is in contact with the low impurity concentration n-type second semiconductor layer 4 even in the Schottky diode region, so that the reverse leakage current of the Schottky diode can be reduced.
[0023]
In the semiconductor device of the present embodiment, the Schottky diode with a small reverse leakage current is also formed on the same semiconductor substrate in addition to the MOSFET portion having the excellent characteristics shown in the first embodiment. A highly functional semiconductor device can be obtained.
[0024]
In each of the above-described embodiments, the n-type conductivity type is the first conductivity type, and the p-type conductivity type is the second conductivity type. However, the same effect is exhibited even in the opposite conductivity type.
[0025]
In each of the above-described embodiments, the crystal material constituting the semiconductor device is not particularly mentioned, but specific crystal materials include, for example, silicon (Si) and silicon carbide (SiC).
[0026]
【The invention's effect】
In the semiconductor device according to the present invention, a first conductivity type semiconductor substrate, a first conductivity type drift layer formed on the semiconductor substrate, and a first conductivity type first semiconductor formed on the drift layer. A first conductive type second semiconductor layer formed on the first semiconductor layer, and a plurality of second conductive type bases provided in the first and second semiconductor layers and spaced apart at a predetermined interval A source region of a first conductivity type selectively formed in each of the base regions, a source electrode provided on a part of the surface of each of the source regions, and one of the source regions. And a gate electrode provided on the surface of the semiconductor layer between the source region and the surface of the semiconductor layer via a gate insulating film, and the first semiconductor layer and the second semiconductor layer are formed by epitaxial growth And Impurity concentration _{N 1} of the serial drift layer, the impurity concentration _{N 2} of the first semiconductor layer, an impurity concentration _{N 3} of the second semiconductor _layer, so it was decided to have a relationship N _{3 <N} 1 _{<N 2,} practical In addition, it is possible to easily obtain a semiconductor device that has a sufficient element breakdown voltage and is unlikely to deteriorate element characteristics.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment.
FIG. 2 is a sectional view of a semiconductor device according to a second embodiment.
FIG. 3 is a cross-sectional view of a semiconductor device according to a third embodiment.
FIG. 4 is a sectional view of a semiconductor device according to a fourth embodiment.
[Explanation of symbols]
1 n type semiconductor substrate (first conductivity type semiconductor substrate), 2 n type drift layer (first conductivity type drift layer), 3 n type first semiconductor layer (first conductivity type first semiconductor layer), 3a n-type semiconductor layer (first conductivity type semiconductor layer), 4 n-type second semiconductor layer (first conductivity-type second semiconductor layer), 4a n-type semiconductor layer (first conductivity-type semiconductor layer), 5 p Type base region (second conductivity type base region), 6 n type source region (first conductivity type source region), 7 gate insulating film, 8 gate electrode, 9 insulating film, 10 source electrode, 11 drain electrode, 12 , 12a p-type guard ring region, 13 n-type third semiconductor layer (first conductivity type third semiconductor layer), 14 anode electrode.

Claims

A first conductivity type semiconductor substrate;
A first conductivity type drift layer formed on the semiconductor substrate;
A first semiconductor layer of a first conductivity type formed on the drift layer;
A second semiconductor layer of a first conductivity type formed on the first semiconductor layer;
A plurality of second conductivity type base regions provided in the first and second semiconductor layers and spaced apart at a predetermined interval;
A first conductivity type source region selectively formed in each of the base regions;
A source electrode provided on a part of the surface of each source region;
A gate electrode provided on a part of the surface of each source region and a surface of the second semiconductor layer between the source regions via a gate insulating film,
The first semiconductor layer and the second semiconductor layer are crystal layers formed by epitaxial growth, and the impurity concentration N _{1 of} the drift layer, the impurity concentration N ₂ of the first semiconductor layer , and the second semiconductor layer The semiconductor device, wherein the impurity concentration N ₃ has a relationship of N ₃ <N ₁ <N ₂ .

In the second semiconductor layer or the first and second semiconductor layers , a second conductivity type guard ring region is provided at a portion surrounding the plurality of base regions while contacting one end with the base region. The semiconductor device according to claim 1 .

2. The impurity concentration N _{1 of the} drift layer is in the range of 2.0 × 10 ¹⁵ cm ⁻³ or more and 5.0 × 10 ¹⁶ cm ⁻³ or less, and the impurity concentration N ₂ of the first semiconductor layer is 1.2 N ₁ or more and 3. 0N ₁ following range, the semiconductor device according to claim 1 or 2, wherein said second semiconductor layer impurity concentration _{N 3} of is in the range of 0.3 N ₁ or 0.7 N ₁ or less.

The distance between the second semiconductor layer directly below the gate electrode and the source region facing each other via the base region is L _ch , and the width of the second semiconductor layer directly below the gate electrode in the gate length direction is 2L _d . _when, _L d _/ L _ch semiconductor device according to any one of claims 1 to 3, characterized in that 0.5 to 3.0.

The semiconductor device of any one of claims 1 to 4, characterized in that it comprises a Schottky diode region to the drift layer and the pressure-resistant layer on the same semiconductor substrate.

6. The semiconductor device according to claim 5, wherein an anode electrode of the Schottky diode is connected to the base region.

7. The semiconductor device according to claim 1, wherein the drift layer, the first semiconductor layer, and the second semiconductor layer are made of silicon (Si) or silicon carbide (SiC).