JPS5972166A - Plural conductor layer structure for monolithic semiconduct-or integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to multiple conductor layer structures for monolithic semiconductor integrated circuit devices having high breakdown voltages.

In typical conventional integrated circuit (IC) structures, monolithic, junction-insulated semiconductor designs are commonly used.

For normal processing, such devices are limited to approximately 40 volts as an upper limit for operation. However, the basic devices typically have diode breakdown limits in excess of 120 volts, and conventional planar device processing can consistently provide such high voltage devices. If the 40 volt limit is widened, IC
It will be available for many applications that are not currently available for drilling. One common problem limiting IC voltage is the well-known P-N junction breakdown voltage drop caused by metallization passing over the junction. When this metallization is biased, the electric field rapidly reduces junction breakdown. For example, A-S, G
Written by rove (7) rPHYsIcs AND TEC
HNOLOGY OF SEMICONDUCTORDE
VICES J (Johm Wi 1 and 5
ons, 1967). The beginning of freezing chapter on page 611 details this phenomenon. It can be seen that at a bias level of 100 volts, the diode breakdown voltage can be modulated over a wide range with significant impact on the IC characteristics. For basic information about IC devices and configuration, see Alan B, Qreb
r ANALOGINTEGRATED C by ene
IRCUIT DESIGNJ (VanNostra
nd Re1nhold Company+ 1972
) can be referenced. "High Voltage Circuit" starting on page 386
The chapter on describes the use of conventional IC field plates to form 100 volt IC designs.

It is an object of the present invention to use a two-layer conductor structure on the IC so that high voltage methanization is shielded from the P-N junction.

Another object of the present invention is to provide a first capacitor on an IC operating at a low voltage to act as a capacitive shield under a high voltage metallization that changes the P-N junction breakdown voltage.
layer conductor.

These and other objectives are realized in a P-N junction isolated monolithic IC by using a first conductor layer that is compatible with a Brenner device structure that is designed to operate at low voltages. be done. The first layer is preferably conductively doped polycrystalline silicon. The first layer is covered with a suitable strength insulator and then a second metal layer, preferably conventional planar device aluminum, is applied over the first layer. The first layer is formed over the underlying P-N junction, particularly the P-N junction underlying the high voltage metallization. This metallization is restricted to the second metal layer. This structure is suitable for raw high voltage PNP lateral transistors or high voltage vertical NPN transistors.
It can also be applied to devices and high voltage resistance.

In fact, PN junctions operated at high voltages can shield the overlying metallization from breakdown modulation by intervening a conductive shield layer.

FIG. 1 is a diagram showing a conventional lateral transistor structure. FIG. 2 is a cross-sectional view of FIG. 1 taken along line 2--2. Portion 10 represents a portion of a semiconductor wafer;
Therein, an IC is fabricated using conventional and well-known planar bibolar construction techniques. Typically, portion 10 is N
type silicon, typically grown evixively on a P type substrate wafer 11. Although not shown, the device is typically surrounded by a P-type insulating diffusion region.

The N0 buried layer 12 typically underlies the active devices.

The rectangular diffusion 13 forms the collector of the transistor with a circular central hole at 14. The round emitter 15 is located inside the hole of the collector 0 metallization 1
6 is formed so as to overlap the emitter 15 and is in ohmic contact with the semiconductor. Here holes 17 are etched through the planar oxide 18 which normally covers the conductor surface.

Metallization 19 forms a collector electrode that is contacted via holes 20 etched through oxide 18 . Diffusions 16 and 15 are P-type, extend approximately 6 microns into the semiconductor structure, and are identified as the base diffusions of the (NPN) Lanzoster. The N region 22, which is the emitter diffusion of a conformal NPN transistor approximately 2.5 microns deep, is in resistive contact with the N-type epitaxial semiconductor material that serves as the base of the lateral PNP transistor. oxide 18
Holes 24 etched through the holes 24 provide forming mink-based electrode connections.

The operation will be explained. The emitter 15 emits minority carriers (holes) 1fjT into the peripheral N-type base region existing between the emitter 15 and the collector hole 14. This minority carrier is collected in the hole 14 after passing through the base and appears as a current in the metallization 19.

According to traditional lateral transistor practice,
Emitter metal 16 is configured to extend over the active transistor base region.

The metallization on top of the planar oxide is P −
It is known that the junction breakdown voltage can be varied across the N-junction. In typical low voltage PNP lateral transistors, this is not a factor.

However, the structures of Figures 1 and 2 are problematic when the collector-base junction is to be operated at large reverse voltages, e.g., greater than about 40 volts. - One may wish to operate some junctions at voltages up to 120 volts. A typical example is the well-known LM39f.

The structure of FIG. 6 has been used where high voltage junctions have been developed. In this class of devices, the emitter 15'-collector 16' spacing is made sufficiently thick that the electric field generated by the collector does not reach through the base region, and the collector 16' has a junction with the emitter metallization. It is formed so that it cannot pass underneath. Although not shown, the device of FIG. 6 has collector metallization 19 extending completely over collector diffusion 16'. Also, if desired,
The contact hole 20 can extend into a horseshoe shape to reduce contact resistance. Although the PNP lateral transistor of FIG. 6 can be formed to operate at high collector voltages, the configuration substantially acts to lower the base-collector current gain of the device. The typical β of the transistor of FIG. 1 is on the order of 100, while the β of the device of FIG. 6 configured to operate at voltages greater than 100 volts is as low as 10. From a circuit design standpoint, this latter number is unacceptably low. If two such PNPs are required to match, the exit hole in the collector diffusion will degrade the match.

The present invention will be described in detail below with reference to the drawings.

Figure 4 shows a high voltage PNP using the multilayer conductor structure of the present invention.
Shows a lateral transistor. Figure 5 shows line 5-5
FIG. 4 is a cross-sectional view of FIG. 4 taken at .

The same element numbers are used for the same elements as in FIGS. 1-6.

Wafer portion 10 shows an epitaxial semiconductor layer grown on a P-type substrate wafer 11 .

The active transistor is constructed on the low resistance buried layer 12.

A P-type diffusion 15' creates the emitter of the transistor, which is completely surrounded by a P-type collector diffusion 1'5 similar to that shown in FIGS. 1-2.

However, since a high voltage device is desired, the emitter-collector spacing is larger than that of FIG.

First, the holes and 20 are etched into the oxide layer 18;
A first conductive layer N30 is then formed on the semiconductor wafer being fabricated. Preferably, this first conductive layer comprises polycrystalline silicon, which is deposited using the well-known CVD method or equivalent means. This first conductive layer is formed approximately 0.5 microns thick and doped with boron (after deposition) to make it conductive by exposure to a boron atmosphere. Alternatively, boron doping can also be done by vapor deposition. Where the holes 17 and 2o are formed, the first conductive layer makes ohmink contact with the exposed silicon. The first layer of conductors is then photolithographically etched to form electrodes 30 and 61.

These electrodes are collector 13 and emitter 15, respectively.
is in ohmic contact with and covers the diffusion of .

The first layer of conductors is then covered with an insulating layer 32. This can be a doped or undoped deposited nitride or oxide, or an oxide grown on polycrystalline silicon. In this latter case, layer 62 is
Exists only on the 0 and 61 surfaces. Layer 62 is preferably formed to a thickness of about 0.6 microns. Holes 63 are then photolithographically etched into layer 32 directly over emitter contact 61 so as to act as passageways, and at the same time holes 24 are also aligned with and act as contacts to diffusion 22. Etched into layers 18 and 32. A conventional metallization layer is then applied based on conventional Zolenar IC technology and etched by photolithography to form electrodes 26 and 65. This metal is conformally deposited aluminum to a thickness of about 1 micron.

Electrodes 60 extend laterally to contact other circuit elements as shown. Alternatively, paths (not shown) can be etched through layer 62 so that contacts can be made wherever desired toward the upper metallization layer.

Collector electrode 60 makes ohmic contact with collector diffusion 16, and the collector-base junction is completely covered by electrode 60, which can be seen here intersecting the surface of the semiconductor. Thus, the closest conductor passing over the oxide on the junction is at collector potential. This means that the junction breakdown voltage depends on the diffusion and resistivity of layer 10.
l:9 will be determined. When emitter metal 35 passes over the collector junction, conductor 60 acts as a shield and the collector-base junction breakdown voltage is not affected by the emitter potential.

FIG. 6 shows a PNP lateral transistor formed within an insulating region of semiconductor material. Where the emitter and base traces of the transistor intersect the insulating junction, the first conductive layer shield shields the junction and maintains its high voltage breakdown characteristics regardless of the applied emitter and base voltages. It works like this. Section 10 represents the N-type epitaxial material on the surface of the silicon wafer. Emitter diffusion 15', collector diffusion 16 and base contact diffusion 22 are the same as described with respect to FIGS. 4 and 5. This transistor is a PN junction isolated from other IC components by a heavily doped P-type edge ring 40. This ring 40
completely passes through the N-type epitaxial layer to form an insulating tab of N-type material. The first layer conductor 60 not only covers the collector diffusion 16, but also extends over the insulating junction over which the emitter and collector metal passes in regions 41 and 42.

This type of configuration consists of an insulating tag made of N-type material and an insulating ring 4.
It is useful where it is necessary to operate at high voltages relative to zero. Under these conditions, base metal 2
6 is at a high positive potential with respect to the insulating ring. Base metal 23 is positively biased relative to collector metal 30, and emitter metal 65 is typically only one port higher.

Figure 7 shows how a system of two conductor layers can be
This shows whether it can be applied to PN vertical IC bipolar transistors. FIG. 8 is a cross-sectional view of the structure of FIG. 7 taken along line 8--8. Portion 1o of the wafer is a conventional N-type epitaxial layer on a P-type substrate wafer 11. A heavily doped P-shaped road edge ring is shown at 44. An N-type buried layer 12 underlies this transistor structure. The base of the transistor is a P-type diffusion 45 J:
is formed. A heavily doped N-type emitter diffusion 46 is formed within base 45. A collector contact 47 of the emitter type material makes ohmic contact with the N type epitaxial material.

Holes are etched through the planar oxide 18 to contact the underlying silicon 48, 49 and 50, providing contacts to the emitter, base and collector, respectively. 1st
The conductor 51 of the layer is provided to contact the paste 45 at the hole 49. This conductor overlaps the pace-emitter junction over its entire circumference and extends over the insulating junction in region 52 over which the collector metal passes. The conductor 51 is covered with the insulating layer 32 so as to be electrically insulated from the second metal layer as described above. Second metal electrodes 56 and 54 are provided in this transistor as emitter and collector contacts at 48 and 5D in the usual manner, and a first layer conductor 51 and other elements (not shown) are provided in this transistor.
It extends over the IC so that it makes contact with the IC. Since the collector metal 54 is at a high positive potential with the insulating N-type epitaxial tab relative to the insulating ring 44, no shielding is required. In ring 44, the collector metal passes over the insulating junction at 52. An extended portion of the first conductor layer 51 below the illustrated collector metal 54 forms this shield.

FIG. 9 shows how the present invention can be applied to diffused IC resistors. Portion 10 represents the surface of an N-type epitaxial layer within which a P-type ion implantation or diffusion 56 has been formed. If such a resistor is to be operated at high voltages, it will comprise a long narrow section joining the extended ends in the well-known dog bone configuration. End contacts 57 and 60 extend through the planar oxide to form resistive contacts.

In the case shown, the ends of the contacts 57 are connected to the first conductive layer 58
It is a low potential end that makes ohmink contact with.

Layer 58 extends around the entire resistive junction. The second layer metal 59 is confined to the highest or most positive potential end of the resistance shown, so that it lies inside the contour of the first conductor layer 58. A resistive contact 60 couples metal 59 to the other end of the resistive element. Thus, where metal 59 intersects a resistive junction in region 61, this junction is shielded by metal 58. Although not shown, the resistor structure includes an overlying N+ layer to form a pinch region, which is often used for high value resistors.

[Brief explanation of the drawing]

Figure 1 is a diagram showing a commonly used conventional IC type of a lateral PNP transistor, Figure 2 is a cross-sectional view of the transistor in Figure 1, and Figure 6 is a diagram showing a conventional IC type of a high voltage lateral transistor. , FIG. 4 is a diagram showing a high-voltage lateral IC transistor of the present invention, FIG. 5 is a cross-sectional view of the transistor of FIG. 4, and FIG. 6 is a diagram showing the present invention applied to an individual high-voltage PNP lateral IC transistor. Figure 7 is a diagram showing the present invention applied to an individual high-voltage NPN vertical IC transistor, Figure 8 is a cross-sectional view of the transistor in Figure 7, and Figure 9 is a diagram showing the present invention applied to a high-voltage IC resistor. FIG. 10: Semiconductor wafer 11 = P type substrate wafer 12:
N1 buried layer 16: Diffusion 14: Collector 15: Emitter 16.19,2
3: Metallization 17. 20: Hole 18:
Planar oxide 22: N0 region 30, 31: Electrode patent applicant National Semiconductor M-Corporation (4 others)

Claims (1)

Claims: (1) A metallization line is formed on top of the insulating oxide to cross the P-N junction, such that the potential on the di-metallization line exceeds the breakdown potential of the junction. In a multi-conductor layer structure for use in a monolithic semiconductor integrated circuit device, as may be modified, a first layer of conductors disposed on top of the insulating oxide and wrapped around at least a portion of the junction; means for making ohmic contact between the first conductor layer and the first portion of the semiconductor; an insulating coating disposed on top of the first layer of conductor; , and a second metal layer wrapped around the junction so as to pass over the junction only where the junction is covered by the first metal layer, and the second metal layer and the second portion of the semiconductor. 1. A multi-conductor layer structure for a monolithic semiconductor integrated circuit device comprising: means for making ohmic contact between said second metal layer so that the potential on said second metal layer does not change the breakdown voltage of said junction. (2. A multi-conductor layer structure for a monolithic semiconductor integrated circuit device according to claim 1, wherein the first conductor layer extends to cover the entire junction. (3) Claim 2 2, wherein the integrated circuit device is a lateral PNP transistor having an emitter-base and a collector, the first layer conductor is in ohmic contact with the collector, and the emitter second metal layer is in ohmic contact with the collector, and the emitter second metal layer is in ohmic contact with the collector, A multi-conductor layer structure for a monolithic semiconductor integrated circuit device, shielding said collector from a base junction passing through. (4) The integrated circuit device of claim 6, wherein the integrated circuit device is a lateral transistor with an insulating diffusion around the PNP transistor, and the first layer conductor further comprises the second layer conductor. A multi-conductor layer structure for a monolithic semiconductor integrated circuit device in which the emitter and base electrodes of a metal layer extend laterally below the emitter and base electrodes passing over the base to an insulating junction. (5) In claim 2, the integrated circuit device is a vertical PNP transistor having an emitter and a base diffusion electrode formed in a semiconductor material of a collector, and the first conductive metal is a semiconductor material of the base. A multi-conductor layer structure for a monolithic semiconductor integrated circuit device that is in ohmink contact with and extends to completely cover the base-collector junction. (6) The integrated circuit device further comprises a surrounding region of heavily doped insulating material, wherein the first conductive layer has a collector metallization of a second metal layer thereon. A multi-conductor layer structure for monolithic semiconductor integrated circuit devices that extends over a collector insulating junction that runs through it. (7) In claim 2, the integrated circuit device is a resistor formed on a surface of the semiconductor, and the first conductor layer extends so as to completely cover the resistive junction and the resistor a monolithic semiconductor integrated circuit in which the first conductor layer shields the resistor-to-substrate junction from a second layer of metal contacting the highest potential end of the resistor; Multi-conductor layer structure for devices.