JPS6231164A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6231164A JPS6231164A JP17070685A JP17070685A JPS6231164A JP S6231164 A JPS6231164 A JP S6231164A JP 17070685 A JP17070685 A JP 17070685A JP 17070685 A JP17070685 A JP 17070685A JP S6231164 A JPS6231164 A JP S6231164A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- substrate
- diode
- covered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 35
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000002184 metal Substances 0.000 claims abstract description 6
- 230000006866 deterioration Effects 0.000 abstract 2
- 238000011109 contamination Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 23
- 230000015556 catabolic process Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000002955 isolation Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000004577 thatch Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0744—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
- H01L27/075—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. lateral bipolar transistor, and vertical bipolar transistor and resistor
- H01L27/0783—Lateral bipolar transistors in combination with diodes, or capacitors, or resistors
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にトランジスタのベース
、エミッタ間にダイオードを接続した半導体装置に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device in which a diode is connected between the base and emitter of a transistor.
従来１．サイリスタ制御用等に用いられるトランジスタ
とダイオードとを並列に接続した半導体装置は、例えば
第３図（ａ）、（ｂ）に示すように、Ｐ型拡散層３゜Ｎ
型半導体基板４及びＰ型拡散層５をそれぞれトランジス
タのコレクタ領域、ベース領域及びエミッタ領域とし、
Ｐ型拡散層６及びＮ型拡散層７をそれぞれダイオードの
アノード領域及びカソード領域として形成し、コンタク
ト８からコレクタ電極９を、コンタクト１０からエミッ
タ電極１１を取出し、エミッタ電極１１はダイオードの
カソード領域のコンタクト１２と短絡させ、さらにダイ
オードのアノード領域のコンタクト１３とトランジスタ
のベース領域のコンタクト１５とを短絡電極１４で短絡
させている。Conventional 1. A semiconductor device in which a transistor and a diode are connected in parallel, used for controlling a thyristor, has a P-type diffusion layer 3°N, as shown in FIGS. 3(a) and 3(b), for example.
The type semiconductor substrate 4 and the P type diffusion layer 5 are respectively used as a collector region, a base region and an emitter region of a transistor,
A P-type diffusion layer 6 and an N-type diffusion layer 7 are formed as the anode region and cathode region of the diode, respectively, and the collector electrode 9 is taken out from the contact 8 and the emitter electrode 11 is taken out from the contact 10. The contact 12 is short-circuited, and the contact 13 in the anode region of the diode and the contact 15 in the base region of the transistor are further short-circuited by a short-circuit electrode 14.
第４図は第３図（ａ）、（ｂ）に示した半導体装置の等
価回路図である。FIG. 4 is an equivalent circuit diagram of the semiconductor device shown in FIGS. 3(a) and 3(b).
尚、第３図（ａ）、（ｂ）において２１は絶縁膜、２２
は誘電体層、１７及び２３はＮ 型拡散層、２５は多結
晶シリコン等からなる支持体である。In addition, in FIGS. 3(a) and 3(b), 21 is an insulating film, and 22 is an insulating film.
1 is a dielectric layer, 17 and 23 are N-type diffusion layers, and 25 is a support made of polycrystalline silicon or the like.
上述した従来の半導体装置は、Ｐ型拡散層５とＮ型拡散
層７及びＰ型拡散層６とＮ＋型型数散層１７をそれぞれ
相互に配線で接続する必要からどうしてもＰＮ接合の表
面露出部１６を完全に覆うことができない、この為外部
からの汚れ、光等に対し弱い構造となり、リーク電流が
多くなったり耐圧が低下しやすいという欠点があった。In the conventional semiconductor device described above, it is necessary to connect the P-type diffusion layer 5 and the N-type diffusion layer 7 and the P-type diffusion layer 6 and the N+ type scattering layer 17 to each other with wiring, so that the surface exposed portion of the PN junction is unavoidable. 16 cannot be completely covered, resulting in a structure that is vulnerable to external dirt, light, etc., and has the disadvantage that leakage current increases and breakdown voltage tends to decrease.
本発明の目点は、上記欠点を除去し、ＰＮ接合部を完全
に覆うことによりリーク電流が少く、耐圧の向上した半
導体装置を提供することにある。An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a semiconductor device with a reduced leakage current and improved breakdown voltage by completely covering the PN junction.
本発明の半導体装置は、一導電型半導体基板をベース領
域としこの半導体基゛板上に形成された逆導電型のエミ
ッタ領域とコレクタ領域とからなるトランジスタと、前
記半導体基板上に設けられかつ前記トランジスタのベー
ス領域に接続された逆導電型のアノード領域とこのアノ
ード領域上に設けられかつ前記トランジスタのエミッタ
領域に接続された一導電型カソード領域とからなるダイ
オードとを有する半導体装置であって、前記ダイオード
のアノード領域を環状に形成し、そして半導体基板表面
のＰＮ接合部を金属電極で覆った構造となっている。A semiconductor device of the present invention includes a transistor having a base region formed on a semiconductor substrate of one conductivity type and an emitter region and a collector region of opposite conductivity type formed on the semiconductor substrate, and A semiconductor device having a diode comprising an anode region of an opposite conductivity type connected to a base region of a transistor and a cathode region of one conductivity type provided on the anode region and connected to an emitter region of the transistor, The anode region of the diode is formed in an annular shape, and the PN junction on the surface of the semiconductor substrate is covered with a metal electrode.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）、（ｂ）は本発明の第１の実施例の平面図
及びＡ−Ａ’線断面図である。FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line AA' of a first embodiment of the present invention.
第１図において、Ｎ型半導体基板４上には、この半導体
基板４をベース領域とし、この上にＰ型拡散層３をコレ
クタ領域、Ｐ型拡散層５をエミッタ領域とするＰＮＰト
ランジスタと、Ｎ型半導体基板４上に設けられ、かつ環
状に形成されるＰ型拡散層６をアノード領域とし、この
アノード領域上に設けられたＮ型拡散層７をカソード領
域とするダイオードとが形成されている。In FIG. 1, a PNP transistor is formed on an N-type semiconductor substrate 4, with the semiconductor substrate 4 as a base region, the P-type diffusion layer 3 as a collector region, and the P-type diffusion layer 5 as an emitter region. A diode is formed in which the P-type diffusion layer 6 provided on the annular semiconductor substrate 4 serves as an anode region, and the N-type diffusion layer 7 provided on the anode region serves as a cathode region. .
そしてエミッタ電極１１によりＰＮＰトランジスタのエ
ミッタ領域とダイオードのカソード領域が接続されてお
り、又短絡電極１４によりＰＮＰトランジスタのベース
領域とダイオーダのアノード領域とがベース領域の一部
を構成するＮ÷型拡散領域１７を介して接続されている
。The emitter electrode 11 connects the emitter region of the PNP transistor and the cathode region of the diode, and the short-circuit electrode 14 connects the base region of the PNP transistor and the anode region of the diode to the N÷ type diffusion that forms part of the base region. They are connected via region 17.
このように構成された本実施例においては、Ｎ型半導体
基板４の表面に形成されたＰ、 Ｎ接合部を全て金属電
極により覆うことができる。In this embodiment configured in this way, the P and N junctions formed on the surface of the N-type semiconductor substrate 4 can all be covered with metal electrodes.
すなわち、Ｐ型拡散層３とＮ型半導体基板４とで形成さ
れるＰＮ接合は従来と同様にコレクタ電極９により覆わ
れ、またＮ型半導体基板４とＰ型拡散層６とで形成され
るＰＮ接合１９及び２０はエミッタ電極１１及び短絡電
極１４により完全に覆われる。この為、従来の半導体装
置のようにＰＮ接合の露出部に起因するリーク電流の増
加や耐圧の低下は生じることはなくなる。That is, the PN junction formed by the P-type diffusion layer 3 and the N-type semiconductor substrate 4 is covered by the collector electrode 9 as in the conventional case, and the PN junction formed by the N-type semiconductor substrate 4 and the P-type diffusion layer 6 is covered by the collector electrode 9 as in the conventional case. Junctions 19 and 20 are completely covered by emitter electrode 11 and shorting electrode 14. Therefore, unlike conventional semiconductor devices, an increase in leakage current and a decrease in breakdown voltage due to the exposed portion of the PN junction do not occur.
第２図（ａ）、（ｂ）は本発明の第２の実施例の平面図
及びＢ−Ｂ′線断面図であり、トランジスタとダイオー
ドを誘電体分離領域内に形成した場合を示している。FIGS. 2(a) and 2(b) are a plan view and a sectional view taken along the line B-B' of a second embodiment of the present invention, showing a case where a transistor and a diode are formed in a dielectric isolation region. .
第２図（ａ）、（ｂ）において、ＰＮＰ）ランジスタと
ダイオードが形成されるＮ型半導体基板４は多結晶シリ
コン等からなり支持体２５上に誘電体層２２を介して形
成されており、このＰＮＰ）ランジスタとダイオーダは
第１図（ａ＞、＜ｂ）の場合とほぼ同様に構成されてい
る。In FIGS. 2(a) and 2(b), an N-type semiconductor substrate 4 on which a PNP transistor and a diode are formed is made of polycrystalline silicon or the like and is formed on a support 25 with a dielectric layer 22 interposed therebetween. This PNP) transistor and diorder are constructed almost in the same way as in the case of FIG. 1 (a>, <b).
すなわち、ＰＮＰ トランジスタはＮ型半導体基板４と
Ｐ型拡散層５及び３とをそれぞれベース領域、エミッタ
領域及びコレクタ領域としており、またダイオードはＰ
型拡散層６及びＮ型拡散層７をそれぞれアノード領域及
びカソード領域としている。That is, the PNP transistor has the N-type semiconductor substrate 4 and the P-type diffusion layers 5 and 3 as the base region, emitter region, and collector region, respectively, and the diode has the P-type semiconductor substrate 4 and the P-type diffusion layers 5 and 3 as the base region, emitter region, and collector region, respectively.
The type diffusion layer 6 and the N type diffusion layer 7 are used as an anode region and a cathode region, respectively.
このアノード領域は、中央に島状の短絡防止用の絶縁膜
２１を有する誘電体層２２による四角錐の周囲に環状に
形成されており、誘電体層２２上に形成されたＮ＋型型
数散層２３アノード領域であるＰ型拡散層６とによるＰ
Ｎ接合２０の半導体基板表面における部分は短絡電極１
４により完全に覆われている。従って本第２の実施例に
おいてもＰＮ接合の露出によりリーク電流の増加や耐圧
の低下は生しることはない。This anode region is formed in an annular shape around a square pyramid formed by a dielectric layer 22 having an island-shaped insulating film 21 for short-circuit prevention in the center. layer 23 and the P type diffusion layer 6 which is the anode region.
The portion of the N-junction 20 on the surface of the semiconductor substrate is the short-circuit electrode 1
completely covered by 4. Therefore, even in the second embodiment, the exposure of the PN junction does not cause an increase in leakage current or a decrease in breakdown voltage.
尚、上記実施例においてはＮ型半導体基板を用いた場合
について説明したが、Ｐ型半導体基板を用いてもよく、
同様の効果が得られる。Note that in the above embodiments, the case where an N-type semiconductor substrate was used was explained, but a P-type semiconductor substrate may also be used.
A similar effect can be obtained.
以上説明したように、本発明は、ダイオードのアノード
領域を環状に形成し、その中央部に、トランジスタのベ
ース領域を構成する拡散層を設けたので外部からの汚れ
及び光等の影響を受は易い半導体基板表面のＰＮ接合部
を完全に金属電極で覆うことができ、リーク電流の増加
や耐圧の低下を防止できる効果がある。As explained above, in the present invention, the anode region of the diode is formed into an annular shape, and the diffusion layer constituting the base region of the transistor is provided in the center of the anode region, so that it is not affected by external dirt, light, etc. The PN junction on the surface of the semiconductor substrate, which tends to be easily exposed, can be completely covered with the metal electrode, which has the effect of preventing an increase in leakage current and a decrease in breakdown voltage.
第１図（ａ）、（ｈ）は本発明の第１の実施例の平面図
及び断面図、第２図（ａ）、’（ｂ）は本発明の第２の
実施例の平面図及び断面図、第３図（ａ）、（ｂ）は従
来の半導体装置の平面図及び断面図、第４図は第３図に
示すトランジスタとダーイオードの等価回路図である。
１・・・ＰＮＰトランジスタ、２・・・ダイオード、３
゜５．６・・・Ｐ型拡散層、４．７・・・Ｎ型拡散層、
８゜１０．１２，１３．１５．１８・・・コンタクト、
９・・・コレクタ電極、１１・・・エミッタ電極、１４
・・・短絡電極、１６・・−ＰＮ接合の表面露出部、１
７，２３・・・Ｎ＋型型数散層１９．２０・・・ＰＮ接
合、２１・・・絶縁膜、２２・・・誘電体層、２４・・
・四角錐、２５・・・支持体。
（−１ｅＦＩＡ ＊］ｌＬ−１”ｌ ＪＰＣ４稟 Ｉ
ＴＲ
築 ２ｍ
第 ３ 回
茅 ４ 図1(a) and 1(h) are a plan view and a sectional view of a first embodiment of the present invention, and FIGS. 2(a) and 2(b) are a plan view and a sectional view of a second embodiment of the present invention. 3(a) and 3(b) are a plan view and a sectional view of a conventional semiconductor device, and FIG. 4 is an equivalent circuit diagram of the transistor and diode shown in FIG. 3. 1...PNP transistor, 2...diode, 3
゜5.6...P type diffusion layer, 4.7...N type diffusion layer,
8゜10.12, 13.15.18...Contact,
9...Collector electrode, 11...Emitter electrode, 14
...Short-circuit electrode, 16...-Surface exposed part of PN junction, 1
7, 23...N+ type scattering layer 19.20...PN junction, 21...insulating film, 22...dielectric layer, 24...
- Square pyramid, 25... support. (-1eFIA *]lL-1"l JPC4 approval I
TR built 2m 3rd thatch 4 fig.
Claims (2)
板上に形成された逆導電型のエミッタ領域とコレクタ領
域とからなるトランジスタと、前記半導体基板上に設け
られかつ前記トランジスタのベース領域に接続された逆
導電型のアノード領域と該アノード領域上に設けられか
つ前記トランジスタのエミッタ領域に接続された一導電
型カソード領域とからなるダイオードとを有する半導体
装置において、前記ダイオードのアノード領域を環状に
形成したことを特徴とする半導体装置。(1) A transistor including a base region of a semiconductor substrate of one conductivity type and an emitter region and a collector region of opposite conductivity type formed on the semiconductor substrate, and a transistor provided on the semiconductor substrate and connected to the base region of the transistor. A semiconductor device having a diode comprising an anode region of opposite conductivity type and a cathode region of one conductivity type provided on the anode region and connected to an emitter region of the transistor, wherein the anode region of the diode is formed into an annular shape. A semiconductor device characterized in that:
覆われている特許請求の範囲第（１）項記載の半導体装
置。(2) The semiconductor device according to claim (1), wherein the PN junction on the surface of the semiconductor substrate is covered with a metal electrode.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17070685A JPS6231164A (en) | 1985-08-02 | 1985-08-02 | Semiconductor device |
| US06/790,669 US4758872A (en) | 1984-10-25 | 1985-10-23 | Integrated circuit fabricated in a semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17070685A JPS6231164A (en) | 1985-08-02 | 1985-08-02 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6231164A true JPS6231164A (en) | 1987-02-10 |
Family
ID=15909883
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17070685A Pending JPS6231164A (en) | 1984-10-25 | 1985-08-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6231164A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP4250569A3 (en) * | 2018-05-30 | 2023-12-13 | Search For The Next Ltd | A circuit and device including a transistor and diode |
-
1985
- 1985-08-02 JP JP17070685A patent/JPS6231164A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP4250569A3 (en) * | 2018-05-30 | 2023-12-13 | Search For The Next Ltd | A circuit and device including a transistor and diode |
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