JPS62262451A - Semiconnductor integrated circuit - Google Patents

Semiconnductor integrated circuit

Info

Publication number
JPS62262451A
JPS62262451A JP10612086A JP10612086A JPS62262451A JP S62262451 A JPS62262451 A JP S62262451A JP 10612086 A JP10612086 A JP 10612086A JP 10612086 A JP10612086 A JP 10612086A JP S62262451 A JPS62262451 A JP S62262451A
Authority
JP
Japan
Prior art keywords
region
integrated circuit
diode
resistor
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10612086A
Other languages
Japanese (ja)
Inventor
Norihito Miyoshi
則仁 三好
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10612086A priority Critical patent/JPS62262451A/en
Publication of JPS62262451A publication Critical patent/JPS62262451A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To increase the integration by means of forming a protective diode close to an input resistor in an island region containing the input resistor. CONSTITUTION:A P type isolated region 8 is formed by diffusion in an N-type epitaxial layer 1 to form an island region 9a forming various elements insulation-isolated from one another. An input resistor 3 is provided in the island region 9a to form a protective junction diode 5 close to a contact 4 in the input side of resistor 3. Thus, any high static voltage put on a terminal connecting to the input resistor 3 can be bypassed to a protective diode 5 to protect the elements inside an integrated circuit. Furthermore, the protective diode 5 can be formed in the island region 9a similar to the proper integrated circuit so that the space for an insulation-isolated region to be another island region may be saved.

Description

【発明の詳細な説明】 〔概要〕 抵抗入力方式の半導体集積回路の静電気破壊防止のため
の保護素子を設ける際、抵抗と同じ島領域内で、且つこ
の抵抗に近接して保護ダイオードを形成することにより
、集積度の向上をはかる。
[Detailed Description of the Invention] [Summary] When providing a protective element for preventing electrostatic damage in a resistive input type semiconductor integrated circuit, a protective diode is formed in the same island region as the resistor and close to the resistor. By doing so, we aim to improve the degree of integration.

〔産業上の利用分野〕[Industrial application field]

本発明は抵抗入力方式の半導体集積回路の静電気破壊に
対する保護素子の構造に関する。
The present invention relates to the structure of a protection element against electrostatic damage for a resistive input type semiconductor integrated circuit.

半導体集積回路は取扱い中、入力端子に外部から予期せ
ぬ高い静電気がかかり、内部の素子を破壊することがあ
る。このため、従来例の抵抗入力式の半導体集積回路は
入力抵抗およびその他の素、子を形成する島領域とは別
の島領域を作り、ここに保護用のダイオードを形成して
いた。 別個に島領域を形成しているため、面積が大き
くなり、集積度を上げるうえで不利となり、これの改善
が望まれていた。
When semiconductor integrated circuits are handled, unexpectedly high static electricity is applied to the input terminals from the outside, which can destroy internal elements. For this reason, in conventional resistor input type semiconductor integrated circuits, an island region separate from the island region forming the input resistor and other elements and elements is formed, and a protective diode is formed in this island region. Since the island regions are formed separately, the area becomes large, which is disadvantageous in increasing the degree of integration, and improvement of this problem has been desired.

本発明はこの問題を解決しようとするものである。The present invention seeks to solve this problem.

〔従来の技術〕[Conventional technology]

第3図(a)、(b)は従来例における半導体集積回路
の静電破壊防止構造の模式図で、第3図(a)は上面図
、第3図(b)は断面図である。
3(a) and 3(b) are schematic diagrams of a conventional electrostatic breakdown prevention structure for a semiconductor integrated circuit, with FIG. 3(a) being a top view and FIG. 3(b) being a sectional view.

これら図において、1は第1の伝導型(ここではN型)
のエピタキシャル層、これに第2の伝導型(ここではP
型)の絶縁分離領域8を拡散で形成し、互いに絶縁分離
された種々の素子を形成する島領域を作る。
In these figures, 1 is the first conduction type (here N type)
epitaxial layer with a second conductivity type (here P
An insulating isolation region 8 (type) is formed by diffusion to create island regions forming various elements that are insulated from each other.

島領域9aには、N型領域にP型不純物拡散で形成した
入力抵抗3を設ける。更にこの入力抵抗3の入力側のコ
ンタクト4か゛ら入力端子に至るAlの配線7aを、エ
ピタキシャル層lの表面上に形成された絶縁膜のSin
g膜2の上に設ける。又抵抗3の他端にはMOS Tr
、あるいは旧p Tr等の半導体能動素子が接続されて
いる。
In the island region 9a, an input resistor 3 formed by diffusing P-type impurities into an N-type region is provided. Furthermore, the Al wiring 7a from the input side contact 4 of the input resistor 3 to the input terminal is connected to a sinusoidal insulating film formed on the surface of the epitaxial layer l.
Provided on the g film 2. Also, the other end of the resistor 3 is a MOS Tr.
, or a semiconductor active element such as an old pTr is connected.

9bは島領域9aとは別に設けられた保護ダイオード専
用の島領域で、この領域上のSiO□膜2に2つの開口
を作り、一方の開口のコンタクト6aにはP型の拡散を
行い、N型のエピタキシャル層との間にPN接合のダイ
オード5を形成し、他方の開口のコンタクト6bにはN
゛の拡散をおこない島領域9bの下方の埋込層N゛ 1
0と接続させる。
9b is an island region dedicated to a protection diode provided separately from the island region 9a. Two openings are made in the SiO□ film 2 on this region, and the contact 6a of one opening is made with P-type diffusion and N A PN junction diode 5 is formed between the epitaxial layer of the mold and the contact 6b of the other opening is filled with N.
The buried layer N'1 under the island region 9b performs the diffusion of
Connect it to 0.

コンタクト6aの上には配線7aが通り、接合ダイオー
ド5の正極と接続される。
A wiring 7a passes over the contact 6a and is connected to the positive electrode of the junction diode 5.

コンタクト6bにはAIの配線7bが設けられ、この半
導体集積回路に印加される最大電圧(この場合は正)で
あるVccに接続される。
The contact 6b is provided with an AI wiring 7b and connected to Vcc, which is the maximum voltage (positive in this case) applied to this semiconductor integrated circuit.

第3図(a)の右下の図は前記構造をシンボル的に表し
た回路図である。(後述の第1図、第2図においても同
様に示す) 入力端子に過大な正の静電気が入力されると、このとき
は電流は接合ダイオード5に流れバイパスされるので抵
抗3以降の素子は保護される。
The lower right diagram of FIG. 3(a) is a circuit diagram symbolically representing the structure. (The same is shown in Figures 1 and 2, which will be described later.) When excessive positive static electricity is input to the input terminal, the current flows to the junction diode 5 and is bypassed, so the elements after the resistor 3 are protected.

集積回路使用時の正常値電圧に対しては接合ダイオード
5がOFF状態となっている。
The junction diode 5 is in an OFF state for a normal value voltage when the integrated circuit is used.

このように、従来の半導体集積回路では保護用のダイオ
ードを、本来の集積回路用の島領域とは別の島領域に形
成しているので分離領域に余分のスペースをとられ、集
積度を上げる点で好ましくなかった。
In this way, in conventional semiconductor integrated circuits, the protection diode is formed in an island area separate from the island area for the original integrated circuit, so extra space is taken up in the isolation area, which increases the degree of integration. I didn't like it in that respect.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

機能的には従来例のものと同じで、保護用ダイオードを
入力抵抗を形成する本来の集積回路用の島領域と同じ島
領域内で、且つ抵抗の入力側コンタクトに近接して設け
ることにより、集積度の向上を図るものである。
Functionally, it is the same as the conventional example, and by providing the protection diode in the same island region as the island region for the original integrated circuit that forms the input resistor, and close to the input side contact of the resistor, The aim is to improve the degree of integration.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点の解決は、入力抵抗を有する半導体集積回路
において、第1の伝導型領域のエピタキシャル層(1)
に拡散により形成した第2の伝導型の抵抗(3)の入力
側のコンタクト(4)と近接し、且つ絶縁分離領域(8
)で作られる同じ島領域(9a)内に形成した保護用の
ダイオード(5)を有し、この保護ダイオード(5)を
半導体集積回路に印加される電源に接続する本発明によ
る半導体集積回路により達成することが出来る。
The solution to the above problem is that in a semiconductor integrated circuit having an input resistance, the epitaxial layer (1) of the first conduction type region is
It is close to the input side contact (4) of the second conductivity type resistor (3) formed by diffusion in the insulating isolation region (8).
), the semiconductor integrated circuit according to the present invention has a protective diode (5) formed in the same island region (9a), and connects this protective diode (5) to a power supply applied to the semiconductor integrated circuit. It can be achieved.

特に前記ダイオード(5)を第1の伝導型の領域に、第
2の伝導型の領域を拡散形成した接合型ダイオードとす
ることにより本発明は容易に実施し得る。
In particular, the present invention can be easily implemented by making the diode (5) a junction diode in which a region of the first conductivity type and a region of the second conductivity type are diffused.

更に前記保護ダイオード(5)を第1の伝導型の領域と
、この第1の伝導型の領域上の絶縁膜(2)の開口部に
被着した金属とにより形成されるショットキーバリア型
ダイオードとすることにより本発明は容易に実施するこ
とが出来る。
Furthermore, the protection diode (5) is a Schottky barrier diode formed by a region of a first conductivity type and a metal deposited on the opening of the insulating film (2) on the region of the first conductivity type. By doing so, the present invention can be easily implemented.

〔作用〕 半導体集積回路を取扱い中、入力抵抗接続の端子に大き
な静電気電圧がかかっても、保護ダイオードにバイパス
され、内部の集積回路の素子は保護される。又保護ダイ
オードは本来の集積回路と同じ島領域内に形成されるの
で、別の島領域とするときの絶縁分離領域にとられるス
ペースを節減出来、集積度向上が可能となる。
[Function] While handling a semiconductor integrated circuit, even if a large electrostatic voltage is applied to the input resistor connection terminal, it will be bypassed by the protection diode and the internal integrated circuit elements will be protected. Furthermore, since the protection diode is formed in the same island region as the original integrated circuit, the space taken up by the insulation isolation region when it is used as a separate island region can be saved, and the degree of integration can be improved.

〔実施例〕〔Example〕

第1図(a) 、(b)は本発明の実施例(1)におけ
る半導体集積回路の静電破壊防止構造の模式図で、第1
図(a)は上面図、第1図(b)は断面図である。
FIGS. 1(a) and 1(b) are schematic diagrams of an electrostatic breakdown prevention structure for a semiconductor integrated circuit in Example (1) of the present invention.
FIG. 1(a) is a top view, and FIG. 1(b) is a sectional view.

これら図において、第3図と同じ名称のものは同じ符号
で示す。
In these figures, parts with the same names as in FIG. 3 are designated by the same reference numerals.

図において、1は第1の伝導型(ここではN型)のエピ
タキシャル層で、これに第2の伝導型(ここではP型)
の分離領域8を拡散で形成し、互いに絶縁分離された、
種々の素子を形成する島領域9aを作る。
In the figure, 1 is an epitaxial layer of the first conductivity type (here, N type), which is coated with a second conductivity type (here, P type).
The isolation regions 8 are formed by diffusion, and the isolation regions 8 are insulated and isolated from each other.
An island region 9a in which various elements will be formed is created.

島領域9aには、N型領域にP型不純物拡散で形成した
入力抵抗3を設ける。更にこの入力抵抗3の入力側のコ
ンタクト4に近接して保護用の接合ダイオード5を形成
するためのP壁領域を設け、これにコンタクト6aを作
り、両コンタクト4と6aをカバーし入力端子に至るA
tの配線7をSiO□膜2上膜形上する。N型のエピタ
キシャル層1の下部にはNoの埋込層10があり、これ
がこの集積回路に印加される最も高い電圧Vccまたは
それに近い電圧の電源に接続されている。この構造の接
続図は第1図(a)の右下の図となり、これは全く第3
図(a)におけるものと同じである。
In the island region 9a, an input resistor 3 formed by diffusing P-type impurities into an N-type region is provided. Further, a P-wall region for forming a protective junction diode 5 is provided close to the contact 4 on the input side of the input resistor 3, a contact 6a is formed in this, and both contacts 4 and 6a are covered to form an input terminal. A to reach
The wiring 7 of t is formed on the SiO□ film 2. Underneath the N-type epitaxial layer 1 there is a buried layer 10 of No, which is connected to a power source at or near the highest voltage Vcc applied to the integrated circuit. The connection diagram of this structure is the lower right diagram of Figure 1(a), which is completely different from the third
This is the same as in Figure (a).

第2図(a) 、(b)は本発明の実施例(2)におけ
る半導体集積回路の静電破壊防止構造の模式図で、第2
図(a)は上面図、第2図(b)は断面図である。
FIGS. 2(a) and 2(b) are schematic diagrams of a structure for preventing electrostatic damage of a semiconductor integrated circuit in Example (2) of the present invention.
FIG. 2(a) is a top view, and FIG. 2(b) is a sectional view.

これは抵抗3のコンタクト4に近接して5i02膜2に
開口を設け、ここにAIの電極配線7を被着形成してシ
ッットキーバリアダイオード5を形成する。それ以外は
第2図のPN接合ダイオードを形成したものと全(同一
である。
In this case, an opening is provided in the 5i02 film 2 adjacent to the contact 4 of the resistor 3, and an AI electrode wiring 7 is deposited thereon to form a Schittky barrier diode 5. Everything else is the same as the PN junction diode shown in FIG.

本発明の実施例(1)、(2)で示したように静電気に
対する保護機能は全〈従来のものと同じで、面積的に小
さく出来るので集積度向上を図ることが出来る。
As shown in Embodiments (1) and (2) of the present invention, the protection function against static electricity is the same as that of the conventional device, and since the area can be reduced, the degree of integration can be improved.

又、ここでは第1伝導型としてN型、第2伝導型として
P型として示したが、これらは入れ換えて逆としてもよ
い。但しこのときはVccを集積回路に印加される負の
最も高い電圧またはそれに近い電圧とすればよい。
Further, although the first conductivity type is N type and the second conductivity type is P type, these may be reversed. However, in this case, Vcc may be set to the highest negative voltage applied to the integrated circuit or a voltage close to it.

〔発明の効果〕〔Effect of the invention〕

抵抗入力方式の半導体集積回路で、入力抵抗と同じ島領
域内で、且つこの抵抗に近接して保護ダイオードを形成
することにより、集積度を向上せしめることが出来る。
In a resistor input type semiconductor integrated circuit, the degree of integration can be improved by forming a protection diode in the same island region as the input resistor and close to the resistor.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a) 、(b)は本発明の実施例(1)におけ
る半導体集積回路の静電破壊防止構造の模式図−第2図
(a) 、(b)は本発明の実施例(2)における半導
体集積回路の静電破壊防止構造の模式図、第3図(a)
、(b)は従来例における半導体集積回路の静電破壊防
止構造の模式図である。 (a)は上面図、(b)は断面図である。 これら図において、 1はエピタキシャル層(N型)、 2は5ift膜、 3は抵抗、 4はコンタクト、 5はダイオード、 6a、6bはコンタクト、 7は配線(AI)、 8は絶縁分離領域(P壁領域)、 9aは島領域、 10は埋込層
FIGS. 1(a) and (b) are schematic diagrams of an electrostatic breakdown prevention structure for a semiconductor integrated circuit in embodiment (1) of the present invention. FIGS. Schematic diagram of the electrostatic damage prevention structure of the semiconductor integrated circuit in 2), Figure 3(a)
, (b) are schematic diagrams of a conventional electrostatic breakdown prevention structure for a semiconductor integrated circuit. (a) is a top view, and (b) is a sectional view. In these figures, 1 is an epitaxial layer (N type), 2 is a 5ift film, 3 is a resistor, 4 is a contact, 5 is a diode, 6a and 6b are contacts, 7 is a wiring (AI), and 8 is an isolation region (P wall area), 9a is an island area, 10 is a buried layer

Claims (1)

【特許請求の範囲】 〔1〕入力抵抗を有する半導体集積回路において、第1
の伝導型領域のエピタキシャル層(1)に拡散により形
成した第2の伝導型の抵抗(3)の入力側のコンタクト
(4)と近接し、且つ絶縁分離領域(8)で作られる同
じ島領域(9a)内に形成した保護用のダイオード(5
)を有し、このダイオード(5)を半導体集積回路に印
加される電源に接続する ことを特徴とする半導体集積回路。 〔2〕前記ダイオード(5)が第1の伝導型の領域に、
第2の伝導型の領域を拡散形成した接合型ダイオードで
ある ことを特徴とする特許請求の範囲第1項記載の半導体集
積回路。 〔3〕前記ダイオード(5)が第1の伝導型の領域と、
この第1の伝導型の領域上の絶縁膜(2)の開口部に被
着した金属とにより形成されるショットキーバリア型ダ
イオードである ことを特徴とする特許請求の範囲第1項記載の半導体集
積回路。
[Scope of Claims] [1] In a semiconductor integrated circuit having an input resistance, a first
the same island region adjacent to the contact (4) on the input side of the resistor (3) of the second conduction type formed by diffusion in the epitaxial layer (1) of the conduction type region and made of the isolation region (8); A protective diode (5) formed in (9a)
), and the diode (5) is connected to a power supply applied to the semiconductor integrated circuit. [2] The diode (5) is in a region of the first conductivity type,
2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is a junction diode in which a region of the second conductivity type is formed by diffusion. [3] a region in which the diode (5) is of a first conductivity type;
The semiconductor according to claim 1, characterized in that it is a Schottky barrier diode formed by metal deposited in the opening of the insulating film (2) on the region of the first conductivity type. integrated circuit.
JP10612086A 1986-05-09 1986-05-09 Semiconnductor integrated circuit Pending JPS62262451A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10612086A JPS62262451A (en) 1986-05-09 1986-05-09 Semiconnductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10612086A JPS62262451A (en) 1986-05-09 1986-05-09 Semiconnductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS62262451A true JPS62262451A (en) 1987-11-14

Family

ID=14425583

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10612086A Pending JPS62262451A (en) 1986-05-09 1986-05-09 Semiconnductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS62262451A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020170765A (en) * 2019-04-02 2020-10-15 キヤノン株式会社 Semiconductor light-emitting device, light exposure head and image formation device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020170765A (en) * 2019-04-02 2020-10-15 キヤノン株式会社 Semiconductor light-emitting device, light exposure head and image formation device

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