JPS599955A - Complementary insulated gate field effect semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enable to satisfy the prescribed protective withstand voltage even when the titled device is integrated in high density by a method wherein an oppositely conductive buried layer provided on a semiconductor substrate is connected respectively to an input bonding pad and an input gate. CONSTITUTION:The input bonding pad 21 is connected ohmically to the P type buried layer 23 through a P<+> type diffusion layer 26 provided on the layer 23. Moreover a wiring to the input gate is connected ohmically after passing through a resistor 29 formed by the layer 23 and the P<+> type diffusion layers 26. N<+> type diffusion layers 24 are provided respectively on the layer 23 and the N type semiconductor substrate, and are connected ohmically to a VCC electric power source wiring. According to said construction, the even when high voltage noise is applied to the pad 21, because the depth of the layer 23 is made deeper than the depth of the diffusion layer, the conduction due to an alloy spike between the layer 23 and the N type substrate can be prevented from generating. Moreover, by providing the layer 24 on the layer 23 to form a low withstand voltage diode 28, gate protecting function thereof can be ensured.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and particularly to an input gate protection device thereof.

In a conventional input gate protection device composed of a resistive element and a capacitive element, polysilicon containing a single conductivity type impurity, a diffusion layer, and the like are used as materials for forming the pixel element. In general, the input gate protection breakdown voltage increases as the values of the resistive element and capacitive element of the input gate protection device increase, and the area of the layout pattern also increases accordingly.

Also, in recent years. In order to achieve higher density integration and improve electrical characteristics, progress is being made in reducing layout patterns, making diffusion layers shallower in the wafer manufacturing process, and reducing polysilicon film thickness. It is not only difficult to maintain the input gate protection breakdown voltage for the resistive element and capacitive element constituting the protection device, but also increases the layout pattern area. In other words, efforts must be made to prevent aluminum from penetrating into the diffusion layer by making the diffusion layer shallower, so-called alloy spikes, and to reduce the layout pattern area in order to obtain a predetermined resistance value by reducing the polysilicon film thickness. Expansion will inevitably occur. Therefore, even with recent improvements in manufacturing processes to increase density integration and improve electrical characteristics, input gate protection devices still have to maintain a specified protection voltage.
The area of the layout pattern must also be made smaller than that of the conventional protection device.

The present invention has performance equivalent to or higher than that of conventional protection voltages, and the area occupied by the layout pattern is smaller than that of conventional protection devices, making higher density integration possible. It is.

According to the present invention, a buried layer of an opposite conductivity type provided on a semiconductor substrate of one conductivity type is ohmically connected to an input bonding pad and an input gate, and further provided in the semiconductor substrate and the buried layer. Thus, an input gate protection device having a structure in which the semiconductor substrate and the diffusion layer containing impurities of the same conductivity type are ohmically connected can be obtained.

The present invention will be explained with reference to the drawings, taking as an example an input gate protection device in a complementary MO8 structure using a P-type buried layer on an N-type semiconductor substrate and comparing it with a conventional device.

FIG. 1(a) shows an example of the layout pattern of a conventional input gate protection device, and FIG.
) and FIG. 1(c) respectively show the equivalent circuit of FIG. 1(a) and a sectional view taken along a-b in FIG. 1(a). In FIGS. 1(a), 1(b), and 1(c), an input bonding pad 11 is ohmically connected to one end of a polysilicon resistor 12 containing an N-type impurity. Next, the other end of the polysilicon resistor 12 is ohmically connected to an N-type diffusion layer 14 provided on the P-type buried layer 13 via an aluminum wiring 15, and further leads to an input gate. Next, the P-type buried layer 13 is connected to the aluminum wiring 1a1 of the GND power source via the P-type diffusion layer 16 containing a high concentration of P-type impurities.
7 and is ohmic connected. To explain the operation of this protection device, when positive noise is applied to the bonding pad 11 with respect to the GND electrode 17, the applied noise current flows through the P-type buried layer 13 through the polysilicon resistor 12. and the N-type diffusion layer 14. This noise current flows through the diode 1
8, this is a reverse current, but the withstand voltage of this diode is usually about 15V, so if noise higher than this voltage is applied, this diode becomes a sufficient current path to absorb the noise voltage and reduce the input gate voltage. fulfills a protective function. However, in such a conventional input gate protection device, if the N-type diffusion layer is made shallow, the N
Aluminum permeates into the type diffusion layer, and the N type diffusion layer and the P type buried layer become completely electrically connected. Further, reducing the value of polysilicon resistance for the purpose of high-density integration makes the above-described aluminum penetration more likely to occur.

In the present invention, attention is paid to the fact that the depth of the buried layer is deeper than that of the diffusion layer, so that aluminum penetration does not occur. Furthermore, the present invention provides an input gate protection device that can sufficiently satisfy a predetermined protection voltage even when high-density integration is achieved by omitting a polysilicon resistor.

FIG. 2(a) shows a layout pattern of an embodiment employing the present invention, and FIG. 2(b) and FIG. FIG. 2(a) shows a cross-sectional view of a/B/ in (a),
Input pad 2 in (b) and (c)
1 is ohmically connected to a P-type buried layer 23 through a P-diffusion layer 26 containing a high concentration of P-type impurity and provided on the P-type buried layer M2S. Next, the wiring to the input gate is connected to the P-type buried layer 23, which is connected geometrically by the aluminum wiring 25 after obtaining a resistor 29 formed by the P-type buried layer 23 and the P-diffusion layer 26. N-type diffusion layers 24 containing a high concentration of N-type impurities are provided on the upper and N-type semiconductor substrates, respectively, and the aluminum wiring of the Vcc power supply is provided. It is ohmic connected to 1J27. With such a structure,
Even if high voltage noise is applied to the input bonding pad, the depth of the P-type buried layer is deeper than that of the diffusion layer, preventing conduction between the P-type buried layer and the N-type substrate due to alloy spikes. can. Here, the reason why the N-type diffusion layer is provided on the P-type buried layer is that the button becomes effective when negative high voltage noise is applied to the input bonding pad. That is, the diode 30 formed between the P-type buried layer and the N-type substrate.
Since the withstand voltage of normally is about 100V, if left as it is, the first input gate will be destroyed and the gate protection function will not be fulfilled.For this reason, N containing a high concentration of impurity on the P-type buried layer is
By providing the type diffusion layer and forming the diode 28 with a low breakdown voltage, the gate protection function is ensured.

Although the embodiments of the present invention have been described using a P-type buried layer on an N-type substrate, the effects of the present invention can also be obtained when an N-type buried layer is used on a P-type substrate. It can be used as is.

[Brief explanation of the drawing]

FIG. 1(a) shows a layout pattern of a conventional input gate protection device, and FIG. 1(b) shows an equivalent circuit of FIG. 1(a). Figure 1(c) shows a-b in Figure 1(a).
FIG. FIG. 2(a) shows a layout pattern of an input gate protection device according to the present invention.
) shows the equivalent circuit of FIG. 2(a). FIG. 2(c) is a sectional view taken along line a'-b' of FIG. 2(a). In the figure, 11.21... Input bonding pad, 12... Polysilicon resistor containing N-type impurity, 13, 23°''-P-type buried layer, 14
゜24°・・・N-type diffusion layer, 15, 25, 17.2
7... Aluminum arrangement L16, 26...
P-type diffusion layer, 18, 28, 30... diode, 29... resistor. Fig. 1 (θ) Foil 1 Fig. (b) 4 Fig. 1 (C) Fig. 2 (CL) 2nd flash (C)

Claims (1)

[Claims] A buried layer of an opposite conductivity type provided on a semiconductor substrate of one conductivity type is ohmically connected to an input bonding pad and an input gate, and a buried layer provided in the semiconductor substrate and the buried layer has the same conductivity as the semiconductor substrate. 1. A complementary insulated gate field effect semiconductor integrated circuit device, characterized in that a diffusion layer containing a type of impurity is ohmically connected.