JP2821128B2 - Semiconductor input protection device - Google Patents
Semiconductor input protection deviceInfo
- Publication number
- JP2821128B2 JP2821128B2 JP63020283A JP2028388A JP2821128B2 JP 2821128 B2 JP2821128 B2 JP 2821128B2 JP 63020283 A JP63020283 A JP 63020283A JP 2028388 A JP2028388 A JP 2028388A JP 2821128 B2 JP2821128 B2 JP 2821128B2
- Authority
- JP
- Japan
- Prior art keywords
- impurity diffusion
- diffusion layer
- layer
- conductivity type
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 34
- 239000012535 impurity Substances 0.000 claims description 74
- 238000009792 diffusion process Methods 0.000 claims description 61
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 23
- 230000002159 abnormal effect Effects 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 11
- 238000002955 isolation Methods 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 97
- 229910052782 aluminium Inorganic materials 0.000 description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 6
- 239000002784 hot electron Substances 0.000 description 6
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 239000011574 phosphorus Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 206010023203 Joint destruction Diseases 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は入力端子に加えられる静電気などの外部サー
ジから装置を保護するための入力保護回路を備えた半導
体装置に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an input protection circuit for protecting a device from an external surge such as static electricity applied to an input terminal.
［従来の技術］ 半導体装置とくに絶縁ゲート型電界効果集積回路装置
（MOSIC）では、ゲート絶縁膜として厚さ200〜300Åと
非常に薄いシリコン酸化膜が使用されており摩擦により
生ずる静電気やノイズ電圧などにより容易に絶縁破壊
し、入力保護装置を設けないと実使用上支障があること
はよく知られている。また今後MOSICは高集積化、高性
能化がすすみ、ゲート絶縁膜はさらに薄膜化の方向にあ
り、問題は重大となりつつある。[Prior art] In semiconductor devices, especially insulated gate type field effect integrated circuit devices (MOSIC), a very thin silicon oxide film having a thickness of 200 to 300 mm is used as a gate insulating film. It is well known that dielectric breakdown occurs more easily, and there is a problem in practical use unless an input protection device is provided. In the future, MOSICs are becoming more highly integrated and higher in performance, and gate insulating films are becoming thinner, and the problem is becoming more serious.
第３図は、一般的に使用されている半導体保護装置の
等価回路である。この等価回路は抵抗R1,R2と、ゲート
が入力端子Ｐと抵抗R1の一端に、ドレインが抵抗R1の他
端と抵抗R2の一端に、ソースが接地に接続されたトラン
ジスタQ1と，ゲートとソースが接地にドレインが抵抗R2
の他端と、内部回路であるトランジスタQ3の入力ゲート
に接続されたトランジスタQ2により構成されている。FIG. 3 is an equivalent circuit of a generally used semiconductor protection device. This equivalent circuit includes resistors R1 and R2, a gate connected to the input terminal P and one end of the resistor R1, a drain connected to the other end of the resistor R1 and one end of the resistor R2, a transistor Q1 connected to the ground, a gate and a source. Is ground and drain is resistor R2
And the transistor Q2 connected to the input gate of the transistor Q3 which is an internal circuit.
入力端子Ｐは通常、ボンデイング用のアルミパッドに
接続されている。またトランジスタQ3は保護されるべき
トランジスタを表しており、そのゲート絶縁膜は前述の
ように厚さ200〜300Åのシリコン酸化膜が使用される。
トランジスタＱには、パンチスルートランジスタでソー
ス・ドレイン間に20V前後の異常電圧が印加されると導
通し、入力電圧をクランプする働きがある。トランジス
タQ2のゲート絶縁膜としては、トランジスタQ3と同様の
ものを用いることが普通である。トランジスタQ1はしき
い値電圧が20V程度のトランジスタ600Å程度の厚いシリ
コン酸化膜がゲート絶縁膜として用いられており、通常
いわゆるチャンネルストッパ領域と同時に形成される。
抵抗R1,R2は時定数を設けて入力パルス波形をなまら
せ、またトランジスタQ1あるいはQ2が導通状態になった
際に電流を制限する目的があり、通常半導体基板と反対
導電型の不純物拡散層あるいはリンなどの不純物を含ん
だ多結晶シリコン層で形成することが多い。The input terminal P is usually connected to a bonding aluminum pad. The transistor Q3 represents a transistor to be protected, and its gate insulating film is formed of a silicon oxide film having a thickness of 200 to 300 ° as described above.
The transistor Q conducts when an abnormal voltage of about 20 V is applied between the source and the drain of the punch-through transistor, and has a function of clamping the input voltage. As the gate insulating film of the transistor Q2, it is common to use the same one as the transistor Q3. The transistor Q1 uses a thick silicon oxide film having a threshold voltage of about 20 V and a transistor thickness of about 600 ° as a gate insulating film, and is usually formed simultaneously with a so-called channel stopper region.
The resistors R1 and R2 provide a time constant to smooth the input pulse waveform, and to limit the current when the transistor Q1 or Q2 is turned on. It is often formed of a polycrystalline silicon layer containing an impurity such as phosphorus.
第４図は第３図の等価回路を半導体上に具体化した場
合の平面図で抵抗素子R1,R2として不純物拡散層を用い
ている。FIG. 4 is a plan view when the equivalent circuit of FIG. 3 is embodied on a semiconductor, and uses impurity diffusion layers as resistance elements R1 and R2.
能動領域である不純物拡散層103,104A,104B、リンを
含む多結晶シリコン層105、コンタクト開口部113A,113
B,113C、およびボンディングパッド101とアルミ配線層1
11,ボンディング用のパッドスルーホールパターン102を
それぞれ示す。ボンディング用パッド101はアルミパタ
ーンで形成され半導体チップ表面全体を覆っているパッ
シベーション膜（図示せず）でパッケージのリード電極
（図示せず）と接続できるようになっており、これが第
３図の入力端子Ｐに相当する。そしてボンディングパッ
ド101（入力端子Ｐ）はコンタクト開口部113Aを通して
不純物拡散層103（第３図の抵抗R1に相当）と接続さ
れ、さらにこの不純物拡散層103（抵抗R1）を経てトラ
ンジスタQ1のドレイン領域に至る。またトランジスタQ1
のソースを形成する不純物拡散層104Aはコンタクト開口
部113Bを通して接地電位のアルミ配線層111に接続さ
れ、さらに抵抗R2を形成する不純物拡散層103の領域を
経てトランジスタQ2のドレイン領域（図示せず）に至
る。また接地電位に保たれた多結晶シリコン層105によ
りトランジスタQ2のゲート電極（図示せず）が形成さ
れ、一方トランジスタQ2のソース（図示せず）を形成す
る不純物拡散層104Bの領域はコンタクト開口部113Cを通
して接地電位のアルミ配線層111に接続されている。Impurity diffusion layers 103, 104A, 104B as active regions, polycrystalline silicon layer 105 containing phosphorus, contact openings 113A, 113
B, 113C, bonding pad 101 and aluminum wiring layer 1
11, a pad through hole pattern 102 for bonding is shown. The bonding pad 101 is formed of an aluminum pattern and can be connected to a lead electrode (not shown) of a package by a passivation film (not shown) covering the entire surface of the semiconductor chip. This corresponds to the terminal P. The bonding pad 101 (input terminal P) is connected to the impurity diffusion layer 103 (corresponding to the resistor R1 in FIG. 3) through the contact opening 113A, and further passes through the impurity diffusion layer 103 (resistance R1) to form the drain region of the transistor Q1. Leads to. Transistor Q1
The impurity diffusion layer 104A forming the source of the transistor Q2 is connected to the aluminum wiring layer 111 at the ground potential through the contact opening 113B, and further passes through the region of the impurity diffusion layer 103 forming the resistor R2 (not shown). Leads to. The gate electrode (not shown) of transistor Q2 is formed by polycrystalline silicon layer 105 kept at the ground potential, while the region of impurity diffusion layer 104B forming the source (not shown) of transistor Q2 is formed in a contact opening. It is connected to a ground potential aluminum wiring layer 111 through 113C.
［発明が解決しようとする問題点］ 上述した従来の入力保護回路の１素子であるMOSトラ
ンジスタ（第３図のQ1）は、ドレイン不純物拡散層（第
４図の103）とMOSトランジスタQ1のゲート酸化膜である
フィールド酸化膜107Aとが接しているため、入力端子
（ボンディングパッド）101に異常電圧が印加されると
ソース不純物拡散層104Aとドレイン不純物拡散層103と
の間の高電界によってソース不純物拡散層104Aからドレ
イン不純物拡散層103へ電子が流れ込み、大部分の電子
はドレイン不純物拡散層103へ抜けるが第６図に示すよ
うに一部十分に高いエネルギーを持った電子（ホットエ
レクトロン）がMOSトランジスタQ1のドレイン不純物拡
散層103に接するフィールド酸化膜107Aの障壁を越えて
入り込み、注入されたホットエレクトロンは、フィール
ド酸化膜107A中のトラップに捕獲され、その結果負電荷
を発生し、その負電荷によって誘導された正電荷がドレ
イン不純物拡散層103近傍の半導体基板110中に発生して
しまい、そのために第７図に示すようにドレイン不純物
拡散層103とフィールド酸化膜107Aとが接する領域で形
成される空乏層112幅が極めて小さくなりドレイン不純
物拡散層103−半導体基板110間の耐圧が下がってしまう
という欠点がある。[Problems to be Solved by the Invention] The MOS transistor (Q1 in FIG. 3) which is one element of the conventional input protection circuit described above includes a drain impurity diffusion layer (103 in FIG. 4) and a gate of the MOS transistor Q1. Since an abnormal voltage is applied to the input terminal (bonding pad) 101 due to contact with the field oxide film 107A, which is an oxide film, a source impurity is generated due to a high electric field between the source impurity diffusion layer 104A and the drain impurity diffusion layer 103. Electrons flow from the diffusion layer 104A to the drain impurity diffusion layer 103, and most of the electrons escape to the drain impurity diffusion layer 103. However, as shown in FIG. 6, some electrons (hot electrons) having sufficiently high energy are MOS. The injected hot electrons that have entered beyond the barrier of the field oxide film 107A in contact with the drain impurity diffusion layer 103 of the transistor Q1 The negative charge is generated as a result, and a positive charge induced by the negative charge is generated in the semiconductor substrate 110 near the drain impurity diffusion layer 103. As a result, as shown in FIG. There is a disadvantage that the width of the depletion layer 112 formed in the region where the drain impurity diffusion layer 103 and the field oxide film 107A are in contact with each other is extremely small, and the breakdown voltage between the drain impurity diffusion layer 103 and the semiconductor substrate 110 is reduced.
したがって、この状態で通常動作時に入力端子（ボン
ディングパッド）101に正電圧が印加されると前述のよ
うにドレイン不純物拡散層103−半導体基板110間耐圧が
低下しているため半導体基板110へ漏れ電流（it）が流
れ、半導体デバイスの信頼性低下を引き起こす。Therefore, when a positive voltage is applied to the input terminal (bonding pad) 101 during normal operation in this state, since the breakdown voltage between the drain impurity diffusion layer 103 and the semiconductor substrate 110 is reduced as described above, the leakage current flows to the semiconductor substrate 110. (It) flows and causes a decrease in the reliability of the semiconductor device.
［発明の従来技術に対する相違点］ 上述した従来の半導体入力保護装置に対し、本発明は
一導電型の半導体基板を含む半導体装置に設けられ、ボ
ンディング用パッドを含む金属製入力端子と第１のポリ
シリコン層とが第１のコンタクト孔を介して接続される
とともに、前記第１のポリシリコン層と逆導電型の第１
の不純物拡散層とが第２のコンタクト孔を介して接続さ
れ、かつ前記第１の不純物拡散層を包含する逆導電型の
第１のウェル層と、電源電位と接続された金属配線と第
２のポリシリコン層とが第３のコンタクト孔を介して接
続されるとともに、前記第２のポリシリコン層と逆導電
型の第２の不純物拡散層とが第４のコンタクト孔を介し
て接続され、かつ前記第２の不純物拡散層を包含する逆
導電型の第２のウェル層とが、前記第１、第２の不純物
拡散層間の分離領域に形成された厚い絶縁膜直下で異常
電流と略垂直な方向に等間隔で平行、かつ半導体装置の
平面において前記パッドの略一辺の流さで相対向すると
ともに、前記第１の不純物拡散層と前記第２の不純物拡
散層とは前記異常電流と略垂直な方向に等間隔で平行、
かつ半導体装置の平面において前記パッドの略一辺の長
さで延在し、前記第１、第２、第３および第４のコンタ
クト孔は前記異常電流と略垂直な方向に等間隔で互いに
平行で、かつ半導体装置の平面において夫々前記パッド
の略一辺の長さで延在するという独創的内容を有する。[Differences of the Invention from the Prior Art] In contrast to the conventional semiconductor input protection device described above, the present invention is provided in a semiconductor device including a semiconductor substrate of one conductivity type, and has a first metal input terminal including a bonding pad and a first input terminal. The first polysilicon layer is connected to the polysilicon layer through a first contact hole, and has a first conductivity type opposite to that of the first polysilicon layer.
And a first well layer of an opposite conductivity type including the first impurity diffusion layer, a metal wiring connected to a power supply potential, and a second wiring. Is connected through a third contact hole, and the second polysilicon layer and the second impurity diffusion layer of the opposite conductivity type are connected through a fourth contact hole, And a second well layer of the opposite conductivity type including the second impurity diffusion layer is substantially perpendicular to the abnormal current immediately below the thick insulating film formed in the isolation region between the first and second impurity diffusion layers. In parallel with each other at equal intervals, and in a plane of the semiconductor device, facing each other at a flow of substantially one side of the pad, and the first impurity diffusion layer and the second impurity diffusion layer are substantially perpendicular to the abnormal current. Parallel at equal intervals in different directions,
The first, second, third, and fourth contact holes extend in the plane of the semiconductor device at a length of substantially one side of the pad, and are parallel to each other at regular intervals in a direction substantially perpendicular to the abnormal current. And has an original content that each of them extends in the plane of the semiconductor device by substantially the length of one side of the pad.
［問題点を解決するための手段］ 本願発明の要旨は、一導電型の半導体基板を含む半導
体装置に設けられ、ボンディング用パッドを含む金属製
入力端子に印加される異常電圧から内部回路素子を保護
する入力保護装置において、前記入力端子と第１のポリ
シリコン層とが第１のコンタクト孔を介して接続される
とともに、前記第１のポリシリコン層と逆導電型の第１
の不純物拡散層とが第２のコンタクト孔を介して接続さ
れ、かつ前記第１の不純物拡散層を包含する逆導電型の
第１のウェル層と、電源電位と接続された金属配線と第
２のポリシリコン層とが第３のコンタクト孔を介して接
続されるとともに、前記第２のポリシリコン層と逆導電
型の第２の不純物拡散層とが第４のコンタクト孔を介し
て接続され、かつ前記第２の不純物拡散層を包含する逆
導電型の第２のウェル層とが、前記第１、第２の不純物
拡散層間の分離領域に形成された厚い絶縁膜直下で異常
電流と略垂直な方向に等間隔で平行、かつ半導体装置の
平面において前記パッドの略一辺の長さで相対向すると
ともに、前記第１の不純物拡散層と前記第２の不純物拡
散層とは前記異常電流と略垂直な方向に等間隔で平行、
かつ半導体装置の平面において前記パッドの略一辺の長
さで延在し、前記第１、第２、第３および第４のコンタ
クト孔は前記異常電流と略垂直な方向に等間隔で互いに
平行で、かつ半導体装置の平面において夫々前記パッド
の略一辺の長さで延在することである。[Means for Solving the Problems] The gist of the present invention is to provide an internal circuit element provided in a semiconductor device including a semiconductor substrate of one conductivity type from an abnormal voltage applied to a metal input terminal including a bonding pad. In the input protection device for protection, the input terminal and the first polysilicon layer are connected via a first contact hole, and the first polysilicon layer has a first conductivity type opposite to that of the first polysilicon layer.
And a first well layer of an opposite conductivity type including the first impurity diffusion layer, a metal wiring connected to a power supply potential, and a second wiring. Is connected through a third contact hole, and the second polysilicon layer and the second impurity diffusion layer of the opposite conductivity type are connected through a fourth contact hole, And a second well layer of the opposite conductivity type including the second impurity diffusion layer is substantially perpendicular to the abnormal current immediately below the thick insulating film formed in the isolation region between the first and second impurity diffusion layers. In parallel with each other at equal intervals and in a plane of the semiconductor device, facing each other at a length of one side of the pad, and the first impurity diffusion layer and the second impurity diffusion layer are substantially equal to the abnormal current. Parallel at equal intervals in the vertical direction,
The first, second, third, and fourth contact holes extend in the plane of the semiconductor device at a length of substantially one side of the pad, and are parallel to each other at regular intervals in a direction substantially perpendicular to the abnormal current. And extending in a plane of the semiconductor device with a length of substantially one side of each of the pads.
［実施例］ 次に本発明について図面を参照して説明する。Example Next, the present invention will be described with reference to the drawings.
第１図（ａ）は本発明の一実施例の平面図で、第１図
（ｂ）は第１図（ａ）のＸ−Ｙ線断面図を示し、第２図
は第１図（ｂ）の（Ｉ）の拡大図を示す。1 (a) is a plan view of one embodiment of the present invention, FIG. 1 (b) is a cross-sectional view taken along the line XY of FIG. 1 (a), and FIG. () Shows an enlarged view of (I).
本実施例ではボンディングパッド101,ボンディング用
スルーホール102は、従来例と同様であるが、ボンディ
ングパッド101はコンタクト開口部106Aを介してＮ型不
純物であるリンを含んだ低抵抗多結晶シリコン層105Aに
接続され、さらに他のコンタクト開口部104Aを介してＰ
型半導体基板110上に形成されたＮ型不純物拡散層103A
に接続され、さらにＮ型不純物拡散層103Aを包囲してＮ
型不純物拡散層103Aより深いＮ型不純物のウェル層115A
が形成されている。全く同様にＮ型不純物ウェル層115A
およびＮ型不純物拡散層103Aと平行に隣接するＮ型不純
物拡散層103BおよびＮ型不純物拡散層103Bを包囲するＮ
型不純物ウェル層115Bが形成され、Ｎ型不純物拡散層10
3Bと接地電位の金属（アルミ）配線111との接続もコン
タクト開口部104B、リンを含んだ多結晶シリコン層105
B、コンタクト開口部106Bを介して形成されている。ま
た、この装置はパッドスルーホール102の領域を除いて
厚いシリコン酸化膜116が被着されている。In this embodiment, the bonding pad 101 and the bonding through-hole 102 are the same as those in the conventional example, but the bonding pad 101 is connected to the low-resistance polycrystalline silicon layer 105A containing phosphorus as an N-type impurity through the contact opening 106A. Through another contact opening 104A.
N-type impurity diffusion layer 103A formed on semiconductor substrate 110
To the N-type impurity diffusion layer 103A.
N-type impurity well layer 115A deeper than N-type impurity diffusion layer 103A
Are formed. The N-type impurity well layer 115A
And N surrounding N-type impurity diffusion layer 103B and N-type impurity diffusion layer 103B adjacent in parallel with N-type impurity diffusion layer 103A.
N-type impurity diffusion layer 10 is formed.
The connection between 3B and the metal (aluminum) wiring 111 at the ground potential is also made in the contact opening 104B and the polycrystalline silicon layer 105 containing phosphorus.
B, formed through the contact opening 106B. In this device, a thick silicon oxide film 116 is applied except for the region of the pad through hole 102.
Ｎ型不純物拡散層103A及びＮ型不純物ウェル層115Aと
Ｎ型不純物拡散層103B及びＮ型不純物ウェル層115Bと
は、互いに平行に隣接しており、この隣接したＮ型不純
物拡散層103A、103Bに常に一様な電界が加わるようにコ
ンタクト開口部106A,104A,104B,106Bの形状や、ボンデ
ィングパッド101および金属（アルミ）配線層111の端も
前記隣接不純物拡散層103A,103Bと平行に配置されてい
る。The N-type impurity diffusion layer 103A and the N-type impurity well layer 115A and the N-type impurity diffusion layer 103B and the N-type impurity well layer 115B are adjacent to each other in parallel with each other. The shapes of the contact openings 106A, 104A, 104B, 106B and the ends of the bonding pad 101 and the metal (aluminum) wiring layer 111 are also arranged in parallel with the adjacent impurity diffusion layers 103A, 103B so that a uniform electric field is always applied. ing.
この入力保護装置は、ボンディングパッド101に異常
電圧が印加されると、ボンディングパット101に接続さ
れたＮ型不純物拡散層103A及びこれを包囲するＮ型不純
物ウェル層115Aと接地電位に接続されているＮ型不純物
拡散層102Bおよびこれを包囲するＮ型不純物ウェル層11
5Bとが極めて狭い間隙で隣接しているためパンチスルー
を起こし短絡し、ボンディングパッド101に印加された
異常電圧を直ちに接地電位に流し保護機能を果たす。In this input protection device, when an abnormal voltage is applied to the bonding pad 101, the N-type impurity diffusion layer 103A connected to the bonding pad 101 and the N-type impurity well layer 115A surrounding the same are connected to the ground potential. N-type impurity diffusion layer 102B and N-type impurity well layer 11 surrounding the same
Since 5B is adjacent to a very narrow gap, punch-through occurs to cause a short circuit, and an abnormal voltage applied to the bonding pad 101 is immediately passed to the ground potential to perform a protection function.
また本実施例においてはＮ型不純物拡散層103A,103B
より不純物領域の深いＮ型不純物ウェル層115A,115Bが
設けられているためボンディングパッド101に印加され
た異常電圧によって発生するホットエレクトロンはＰ型
半導体基板110内部を流れるためホットエレクトロンの
厚いフィールド酸化膜107A中への注入減少は起こらず異
常電圧耐圧に強い半導体デバイスを実現できる。In this embodiment, the N-type impurity diffusion layers 103A and 103B
Since the N-type impurity well layers 115A and 115B having a deeper impurity region are provided, hot electrons generated by an abnormal voltage applied to the bonding pad 101 flow inside the P-type semiconductor substrate 110, so that a thick field oxide film of hot electrons is formed. A decrease in injection into 107A does not occur, and a semiconductor device that is resistant to abnormal voltage withstand voltage can be realized.
さらにボンディングパッド101の金属（アルミ）配線
とＮ型不純物拡散層103Aとの間にリンを含んだ多結晶シ
リコン層105Aを挿入することにより異常電圧印加による
瞬時的に発生する異常電流で発熱し金属（アルミ）が溶
融し、接合破壊を防止するためである。本実施例の場
合、多結晶シリコン層105A、105Bが活性化領域（Ｎ型不
純物拡散層103A,103B領域）上に設ける際多結晶シリコ
ン層を形成する前に不純物拡散領域を形成しておく必要
がある。Further, by inserting a polycrystalline silicon layer 105A containing phosphorus between the metal (aluminum) wiring of the bonding pad 101 and the N-type impurity diffusion layer 103A, heat is generated due to an abnormal current instantaneously generated by applying an abnormal voltage. This is because (aluminum) is melted and joint destruction is prevented. In the case of this embodiment, when the polycrystalline silicon layers 105A and 105B are provided on the activation regions (the N-type impurity diffusion layers 103A and 103B regions), it is necessary to form the impurity diffusion regions before forming the polycrystalline silicon layers. There is.
［発明の効果］ 以上説明したように本発明は、入力端子に接続された
第１の不純物拡散層を包含する第１のウェル層と接地電
位に接続された第２の不純物拡散層を包含する第２のウ
ェル層とが第1,第２の不純物拡散層間の分離領域に形成
された厚い絶縁膜下で等間隔に平行に相対向することに
より、入力端子への異常電圧によって発生するホットエ
レクトロンが第1,第２のウェル層間で流れ、すなわち半
導体基板内部を流れるため、ホットエレクトロンの厚い
フィールド酸化膜中への注入現象を防止できる効果があ
る。[Effects of the Invention] As described above, the present invention includes the first well layer including the first impurity diffusion layer connected to the input terminal and the second impurity diffusion layer connected to the ground potential. Hot electrons generated by an abnormal voltage to the input terminal are caused by the second well layer and the second well layer facing each other in parallel at equal intervals under the thick insulating film formed in the separation region between the first and second impurity diffusion layers. Flows between the first and second well layers, that is, flows inside the semiconductor substrate, so that there is an effect that injection of hot electrons into the thick field oxide film can be prevented.
第１図（ａ）は本発明の半導体入力保護装置の一実施例
の平面図、第１図（ｂ）は第１図（ａ）のＸ−Ｙ線断面
図、第２図は第１図（ｂ）の（Ｉ）の拡大図、第３図は
従来の半導体入力保護装置の等価回路図、第４図は第３
図の従来例の平面図、第５図は第４図のＸ′−Ｙ′線断
面図、第６図，第７図はそれぞれ第５図の拡大図であ
り、それぞれ入力端子に異常電圧印加時、印加後の状態
を示す。 101……入力端子（ボンディングパッド）、 102……パッドスルーホール、 103A……入力端子に接続されたＮ型不純物拡散層、 103B……接地電位に接続されたＮ型不純物拡散層、 104A,104B……Ｎ型不純物拡散層と多結晶シリコン層と
を接続するコンタクト、 105A,105B……Ｎ型不純物のリンを含む多結晶シリコン
層、 106A,106B……多結晶シリコン層と金属（アルミ）配線
層とを接続するコンタクト、 107,107A……フィールド酸化膜、 108……MOSゲート酸化膜、 109……層間絶縁膜、 110……Ｐ型半導体基板、 111……接地電位に接続された金属（アルミ）配線層、 112……空乏層、 113A,113B,113C……金属（アルミ）配線層とＮ型不純物
拡散層を接続するコンタクト、 114……チャンネルストッパ用不純物領域、 115A,115B……Ｎ型不純物ウェル層、 Ｐ……入力端子（ボンディングパッド）、 R1,R2……Ｎ型不純物拡散層の抵抗、 Q1,Q2,Q3……MOSトランジスタ。1 (a) is a plan view of one embodiment of the semiconductor input protection device of the present invention, FIG. 1 (b) is a sectional view taken along the line XY of FIG. 1 (a), and FIG. 2 is FIG. FIG. 3B is an enlarged view of (I), FIG. 3 is an equivalent circuit diagram of a conventional semiconductor input protection device, and FIG.
FIG. 5 is a plan view of a conventional example, FIG. 5 is a sectional view taken along the line X'-Y 'of FIG. 4, and FIGS. 6 and 7 are enlarged views of FIG. 5, respectively. Time, shows the state after application. 101: Input terminal (bonding pad), 102: Pad through hole, 103A: N-type impurity diffusion layer connected to input terminal, 103B: N-type impurity diffusion layer connected to ground potential, 104A, 104B ... Contact for connecting N-type impurity diffusion layer and polycrystalline silicon layer, 105A, 105B... Polycrystalline silicon layer containing phosphorus of N-type impurity, 106A, 106B... Polycrystalline silicon layer and metal (aluminum) wiring Contacts connecting layers, 107, 107A: field oxide film, 108: MOS gate oxide film, 109: interlayer insulating film, 110: P-type semiconductor substrate, 111: metal (aluminum) connected to ground potential ) Wiring layer, 112: depletion layer, 113A, 113B, 113C: Contact connecting metal (aluminum) wiring layer and N-type impurity diffusion layer, 114: Impurity region for channel stopper, 115A, 115B: N-type Impurity well layer, P ... Input terminal (bon Padding), R1, R2 ... N-type impurity diffusion layer resistance, Q1, Q2, Q3 ... MOS transistors.
Claims (1)
設けられ、ボンディング用パッドを含む金属製入力端子
に印加される異常電圧から内部回路素子を保護する入力
保護装置において、 前記入力端子と第１のポリシリコン層とが第１のコンタ
クト孔を介して接続されるとともに、前記第１のポリシ
リコン層と逆導電型の第１の不純物拡散層とが第２のコ
ンタクト孔を介して接続され、かつ前記第１の不純物拡
散層を包含する逆導電型の第１のウェル層と、電源電位
と接続された金属配線と第２のポリシリコン層とが第３
のコンタクト孔を介して接続されるとともに、前記第２
のポリシリコン層と逆導電型の第２の不純物拡散層とが
第４のコンタクト孔を介して接続され、かつ前記第２の
不純物拡散層を包含する逆導電型の第２のウェル層と
が、前記第１、第２の不純物拡散層間の分離領域に形成
された厚い絶縁膜直下で異常電流と略垂直な方向に等間
隔で平行、かつ半導体装置の平面において前記パッドの
略一辺の長さで相対向するとともに、 前記第１の不純物拡散層と前記第２の不純物拡散層とは
前記異常電流と略垂直な方向に等間隔で平行、かつ半導
体装置の平面において前記パッドの略一辺の長さで延在
し、 前記第１、第２、第３および第４のコンタクト孔は前記
異常電流と略垂直な方向に等間隔で互いに平行で、かつ
半導体装置の平面において夫々前記パッドの略一辺の長
さで延在することを特徴とする半導体入力保護装置。1. An input protection device provided on a semiconductor device including a semiconductor substrate of one conductivity type and protecting an internal circuit element from an abnormal voltage applied to a metal input terminal including a bonding pad, wherein The first polysilicon layer is connected through a first contact hole, and the first polysilicon layer and the first impurity diffusion layer of the opposite conductivity type are connected through a second contact hole. And a first well layer of the opposite conductivity type including the first impurity diffusion layer, a metal wiring connected to a power supply potential, and a second polysilicon layer are formed by a third
And the second connection hole.
A polysilicon layer and a second impurity diffusion layer of the opposite conductivity type are connected via a fourth contact hole, and a second well layer of the opposite conductivity type including the second impurity diffusion layer is formed. A length of substantially one side of the pad in a plane substantially parallel to the abnormal current at equal intervals immediately below a thick insulating film formed in the isolation region between the first and second impurity diffusion layers, and in a plane of the semiconductor device; And the first impurity diffusion layer and the second impurity diffusion layer are parallel at regular intervals in a direction substantially perpendicular to the abnormal current, and have a length of substantially one side of the pad in the plane of the semiconductor device. The first, second, third, and fourth contact holes are parallel to each other at regular intervals in a direction substantially perpendicular to the abnormal current, and are substantially one side of the pad in the plane of the semiconductor device. Characterized in that it extends for a length of Conductor input protection device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63020283A JP2821128B2 (en) | 1988-01-29 | 1988-01-29 | Semiconductor input protection device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63020283A JP2821128B2 (en) | 1988-01-29 | 1988-01-29 | Semiconductor input protection device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01194474A JPH01194474A (en) | 1989-08-04 |
| JP2821128B2 true JP2821128B2 (en) | 1998-11-05 |
Family
ID=12022842
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63020283A Expired - Fee Related JP2821128B2 (en) | 1988-01-29 | 1988-01-29 | Semiconductor input protection device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2821128B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2626229B2 (en) * | 1989-10-12 | 1997-07-02 | 日本電気株式会社 | Semiconductor input protection device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57153473A (en) * | 1981-03-17 | 1982-09-22 | Toshiba Corp | Semiconductor device with input and output protective circuit and its manufacturing method |
| JPS61144857A (en) * | 1984-12-19 | 1986-07-02 | Nec Ic Microcomput Syst Ltd | Mos type integrated circuit device |
-
1988
- 1988-01-29 JP JP63020283A patent/JP2821128B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01194474A (en) | 1989-08-04 |
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|---|---|---|---|
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