JPS61255055A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS61255055A JPS61255055A JP9710985A JP9710985A JPS61255055A JP S61255055 A JPS61255055 A JP S61255055A JP 9710985 A JP9710985 A JP 9710985A JP 9710985 A JP9710985 A JP 9710985A JP S61255055 A JPS61255055 A JP S61255055A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- type diffusion
- fet
- integrated circuit
- contact hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000009792 diffusion process Methods 0.000 claims abstract description 42
- 230000003071 parasitic effect Effects 0.000 claims abstract description 16
- 230000005669 field effect Effects 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 230000015556 catabolic process Effects 0.000 abstract description 7
- 239000000956 alloy Substances 0.000 abstract description 4
- 229910045601 alloy Inorganic materials 0.000 abstract description 4
- 239000012535 impurity Substances 0.000 abstract description 4
- 230000001419 dependent effect Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 31
- 230000002159 abnormal effect Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 238000013459 approach Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置に関し、特に、絶縁ゲート
型電界効果トランジスタを、静電気等の異常入力電圧か
ら保護するための入力保護回路を有する半導体集積回路
装置に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and in particular to a semiconductor integrated circuit device having an input protection circuit for protecting an insulated gate field effect transistor from abnormal input voltages such as static electricity. The present invention relates to integrated circuit devices.
従来、半導体集積回路装置の入力保護回路は、静電気等
の異常電圧が直接、絶縁ゲート型電界効果トランジスタ
のゲート絶縁膜に印加されないようにするために、入力
端子としてのポンディングパッドと絶縁ゲート型電界効
果トランジスタのゲート電極との間に、基板とは逆導電
型の拡散層を具備した構造になっていた。なお以下の説
明では絶縁ゲート電界効果トランジスタについてはＭＯ
８型電界効果トランジスタ（以下ＭＯ８ＦＥＴと記す）
を例にして説明する。第２図伽）及び第２図Φ）は、各
々、従来の入力保護回路の等価回路図及び模式的平面図
で、第２図（Ｃ）は第２図Ｑ））のＹ−Ｙ’線における
断面図である。即ち、従来は、第２図（ａ）に示される
様に、入力端子１とゲート電極２との間に、拡散層で形
成された抵抗几１が入っておシ、かつ基板４との間には
、ＰＮ接合ダイオードＤ１が形成された構成になってい
た。この拡散層は、第２図（６）及び第２図（ｅ）に示
される様に、拡散層３自身の抵抗ｋＬ１とＰＮ接合ダイ
オードＤ１のブレイクダウン作用により、入力端子１鴫
印加される異常電圧を、ゲート電極２に近づくにつれて
除々に低下させる役割を果たしていた。尚、図中４はＰ
ｆｉシリコン基板、５は高ａ度Ｐ型不純物層、６はフィ
ールド酸化膜、３はＮ型拡散層、７は眉間絶縁膜、Ｒ２
はＰ型シリコン基板４の広がり抵抗である。Conventionally, input protection circuits for semiconductor integrated circuit devices have been designed to prevent abnormal voltages such as static electricity from being directly applied to the gate insulating film of an insulated gate field effect transistor by connecting a bonding pad as an input terminal and an insulated gate field effect transistor. It had a structure in which a diffusion layer of a conductivity type opposite to that of the substrate was provided between the field-effect transistor and the gate electrode. In the following explanation, MO is used for insulated gate field effect transistors.
Type 8 field effect transistor (hereinafter referred to as MO8FET)
This will be explained using an example. Fig. 2 (G) and Fig. 2 (Φ) are respectively an equivalent circuit diagram and a schematic plan view of a conventional input protection circuit, and Fig. 2 (C) is the Y-Y' line of Fig. 2 Q)). FIG. That is, conventionally, as shown in FIG. 2(a), a resistor 1 formed of a diffusion layer is inserted between an input terminal 1 and a gate electrode 2, and a resistor 1 formed of a diffusion layer is inserted between an input terminal 1 and a gate electrode 2. had a configuration in which a PN junction diode D1 was formed. As shown in FIG. 2(6) and FIG. 2(e), this diffusion layer is affected by the abnormal voltage applied to the input terminal 1 due to the breakdown effect of the resistance kL1 of the diffusion layer 3 itself and the PN junction diode D1. It played the role of gradually lowering the voltage as it approaches the gate electrode 2. In addition, 4 in the figure is P
fi silicon substrate, 5 is a high-a-degree P-type impurity layer, 6 is a field oxide film, 3 is an N-type diffusion layer, 7 is an insulating film between the eyebrows, R2
is the spreading resistance of the P-type silicon substrate 4.
しかしながら、上述した従来の入力保護回路は、入力端
子１と拡散層３とは、コンタクト孔Ｃ１を介して直接、
接続されているために１コンタクト孔Ｃ１近傍では、入
力端子１に印加される異常電圧が、高電圧のまま拡散層
３に加わることになる。However, in the conventional input protection circuit described above, the input terminal 1 and the diffusion layer 3 are connected directly through the contact hole C1.
Because of the connection, the abnormal voltage applied to the input terminal 1 is applied to the diffusion layer 3 as a high voltage in the vicinity of the first contact hole C1.
そして、コンタクトＣ１近傍の拡散層３とシリコン基板
４との間で瞬間的に、ＰＮ接合ダイオードＤ１のブレイ
クダウンによる大電流が流れることになる。このとき、
従来の構造では、コンタクト孔ＣＩ近傍の拡散層３０Ｐ
Ｎ接合ダイオードＤ１の電流シンク能力が不十分なため
に、この部分のＰＮ接合ダイオードＤ１自身の破壊を招
いたシ、アロイスパイクによる入力端子１とシリコン基
板４とのシｌ−トを招いたシして、入力保護回路自身の
信頼性に問題があった。Then, a large current momentarily flows between the diffusion layer 3 near the contact C1 and the silicon substrate 4 due to the breakdown of the PN junction diode D1. At this time,
In the conventional structure, the diffusion layer 30P near the contact hole CI
Due to the insufficient current sink ability of the N-junction diode D1, the PN junction diode D1 itself was destroyed in this part, and the alloy spike caused a shield between the input terminal 1 and the silicon substrate 4. However, there was a problem with the reliability of the input protection circuit itself.
本発明は上記欠点を除去し、入力保護回路の電流シンク
能力を増して、保護回路としての効果を高め、信頼性の
優れた入力保護回路を有する半導体集積回路装置を提供
することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device having an input protection circuit that eliminates the above-mentioned drawbacks, increases the current sink capability of the input protection circuit, enhances the effectiveness of the protection circuit, and has excellent reliability. .
本発明の半導体集積回路装置は、入力端子と内部回路の
ゲート電極との間にＰ型シリコン基板とは逆導電型の第
一のＮ型拡散層よりなる保護抵抗を具備した保護回路を
有する半導体集積回路装置において、前記入力端子と前
記第一のＮ型拡散層を接続するコンタクト孔の近傍の前
記第一のＮ型拡散層に存生絶縁ゲート型電界効果トラン
ジスタが接続され、該寄生絶縁ゲート型電界効果トラン
ジスタは前記第一のＮ型拡散層を取シ囲むように１かつ
該第一のＮ型拡散層より深く形成された第二のＮ型拡散
層（Ｎウェル）よりなるソース電極を有し、また前記コ
ンタクト孔の直下にも第二のＮ型拡散層（Ｎウェル）を
有することにより構成される。The semiconductor integrated circuit device of the present invention is a semiconductor device having a protective circuit including a protective resistor formed of a first N-type diffusion layer having a conductivity type opposite to that of a P-type silicon substrate between an input terminal and a gate electrode of an internal circuit. In the integrated circuit device, a parasitic insulated gate field effect transistor is connected to the first N-type diffusion layer near a contact hole connecting the input terminal and the first N-type diffusion layer, and the parasitic insulated gate The type field effect transistor has a source electrode formed of a second N-type diffusion layer (N-well) that surrounds the first N-type diffusion layer and is formed deeper than the first N-type diffusion layer. In addition, a second N-type diffusion layer (N well) is also provided directly under the contact hole.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）及び第１図中）は各々、本発明の一実施例
の等価回路図及び模式的平面図でおり、第１図（Ｃ）は
第１図中）のｘ−ｘ’線における断面図でおる。FIG. 1(a) and FIG. 1 inside) are an equivalent circuit diagram and a schematic plan view of an embodiment of the present invention, respectively, and FIG. 1(C) is xx' in FIG. 1 inside). This is a cross-sectional view along the line.
本発明による入力保護回路を有する半導体集積回路装置
は、第１図（ａ）の等価回路図に示すように、入力端子
１と拡散層で形成された抵抗几１との間に寄生ＭＯ８Ｆ
ＥＴＴｇが付加されている。この寄生Ｍ０８ＦＥＴＴ２
は、第１図幹）の平面図に示すように、入力端子１と拡
散層３を接続するコンタクト孔Ｃ１の近傍における拡散
層３を取）囲むように形成されている。ｔた、コンタク
ト孔Ｃ１の直下には、アロイ−スパイク対策として、拡
散層３内に、拡散層３よりも深く形成されたＮ型不純物
層（Ｎウェル）８が設けられている。As shown in the equivalent circuit diagram of FIG. 1(a), a semiconductor integrated circuit device having an input protection circuit according to the present invention has parasitic MO8F between an input terminal 1 and a resistor 1 formed of a diffusion layer.
ETTg is added. This parasitic M08FET T2
As shown in the plan view of FIG. In addition, an N-type impurity layer (N well) 8 formed deeper than the diffusion layer 3 in the diffusion layer 3 is provided directly under the contact hole C1 as a countermeasure against alloy spikes.
上記畜生Ｍ０８ＦＥＴＴｚの構造は、第１図（Ｃ） ｒ
こ示すように、ソース電極１０がＮウェル８によって形
成されていることｔ−％徴とする。The structure of the above damn M08FETTz is shown in Figure 1 (C) r
As shown, it is assumed that the source electrode 10 is formed by the N well 8 at t-%.
この構造により、寄生ＭＯ８ＦＥＴＴ２のソース・ドレ
イン間隔りを任意に選ぶことが可能になり、間隔Ｌ１に
短くすることで、Ｔ２のスレッシ曹−ルド電圧（７丁２
）を、ＰＮ接合ダイオードのブレイクダウン電圧と同程
度か、或いはそれ以下の値に設定することが可能である
。仮に、寄生ＭＯ８ＦＥＴのソース電極としてＮウェル
８を形成せずに拡散層９だけで形成したものは、通常、
スレッシ冒−ルド電圧（Ｖｔｚ）がＰＮ接合ダイオード
のブレイクダウン電圧よりも高いため、電流シンクとし
ての能力はほとんど期待できない。従って、本発明によ
る構造は、入力端子１に異常電圧が印加されたとき、寄
生ＭＯ８ＦＥＴＴｚがオンして大電流を吸収するため、
入力保護回路の電流シンク能力を飛躍的に高めることが
可能で、従来のような大電流によるＰＮ接合ダイオード
の破壊を防ぐことが可能でおる。This structure makes it possible to arbitrarily select the source-drain spacing of the parasitic MO8FET T2, and by shortening the spacing to L1, the threshold voltage of T2 (7 to 2
) can be set to a value comparable to or lower than the breakdown voltage of the PN junction diode. If the source electrode of a parasitic MO8FET is formed only with the diffusion layer 9 without forming the N well 8, normally,
Since the threshold voltage (Vtz) is higher than the breakdown voltage of the PN junction diode, its ability as a current sink can hardly be expected. Therefore, in the structure according to the present invention, when an abnormal voltage is applied to the input terminal 1, the parasitic MO8FET Tz turns on and absorbs a large current.
It is possible to dramatically increase the current sink capability of the input protection circuit, and it is possible to prevent the destruction of the PN junction diode due to a large current as in the conventional case.
なお、第１図軸）、伽）、 （ｃ）に於て第２図（ａ）
、Φ）。In addition, Fig. 2 (a) in Fig. 1 axis), 载), (c)
,Φ).
（Ｃ）と同一符号は同一部分をあられすので説明を省略
した。The same reference numerals as in (C) refer to the same parts, so the explanation is omitted.
また、上記実施例はＭＯＳＦＥＴを例に説明したが絶縁
ゲート型電界効果トランジスタ全般で同様実施できるこ
とは説明するまでもない。Further, although the above embodiments have been described using MOSFET as an example, it goes without saying that the same can be implemented with any insulated gate field effect transistor.
以上、詳細に説明したように、本発明による入力保護回
路は、静電気等の異常電圧が、入力端子に印加されたと
き、入力端子と保護抵抗としての拡散層とを接続するコ
ンタクト孔の近傍の拡散層を取り囲むように、寄生ＭＯ
８ＦＥＴが接続されておシ、かつ寄生ＭＯ８ＦＥＴのス
レッショールド電圧が、ＰＮ接合ダイオードのブレイク
ダウン電圧と同程度か、或いはそれ以下の値に設定され
ているため、寄生ＭＯ８ＦＥＴがオンして大電流を吸収
する。As described above in detail, the input protection circuit according to the present invention is capable of protecting the input terminal near the contact hole connecting the input terminal and the diffusion layer serving as a protective resistor when abnormal voltage such as static electricity is applied to the input terminal. A parasitic MO surrounds the diffusion layer.
8FET is connected, and the threshold voltage of the parasitic MO8FET is set to a value similar to or lower than the breakdown voltage of the PN junction diode, so the parasitic MO8FET turns on and generates a large current. absorb.
従って、入力保護回路の電流シンク能力が飛躍的に高ま
ると同時に、入力端子と拡散層とを接続するコンタクト
孔の直下に、アロイスパイク防止対策がなされているた
め、信頼性の優れた入力保護回路を実現でき、その効果
は大きい。Therefore, the current sink capability of the input protection circuit is dramatically increased, and measures to prevent alloy spikes are taken directly under the contact hole that connects the input terminal and the diffusion layer, making the input protection circuit highly reliable. can be achieved, and the effect is great.
第１図に）、Φ）、 （Ｃ）はそれぞれ本発明の一実施
例の等価回路図、模式的平面図及び第１図Φ）のＸ−Ｘ
′線における断面図、第２図（屹（ｂ）、 （Ｃ）はそ
れぞれ従来の半導体集積回路装置の一例の等価回路図、
模式的平面図及び第２図り）のＹ−Ｙ’線における断面
図である。
ｌ・・・・・・入力端子、２・・・・・・ゲート電極、
３・・・・・・Ｎ型拡散層、４・・・・・・Ｐ型シリコ
ン基板、５・・・・・・高濃度Ｐ型不純物層、６・・・
・・・フィールド酸化膜、７・・・・・・層間絶縁膜、
８・・・・・・Ｎウェル、９・・・・・・Ｎ型拡散層、
１０・・・・・・ソース電極、Ｒ１・・・・・・拡散層
抵抗、几２・・・・・・基板４の広がり抵抗、Ｄｌ・・
・・・・ＰＮ接合ダイオード、Ｔｌ・・・・・・ＭＯＳ
ＦＥＴ、Ｔ２・・・・・・寄生ＭＯ８ＰＥＴ％Ｃ１・・
・・・・コンタクト孔、Ｌ・・・・・・寄生ＭＯ８ＦＥ
Ｔのソース・ドレイン間隔。
≦散層枦ｑだ
＄ｌＷＪ1), Φ), and (C) are an equivalent circuit diagram and a schematic plan view of an embodiment of the present invention, and X-X of FIG. 1 Φ), respectively.
2 (b) and (C) are equivalent circuit diagrams of an example of a conventional semiconductor integrated circuit device, respectively.
It is a sectional view taken on the YY' line of a typical plan view and a second figure. l...Input terminal, 2...Gate electrode,
3...N-type diffusion layer, 4...P-type silicon substrate, 5...High concentration P-type impurity layer, 6...
...Field oxide film, 7...Interlayer insulating film,
8...N well, 9...N type diffusion layer,
10... Source electrode, R1... Diffusion layer resistance, 几2... Substrate 4 spreading resistance, Dl...
...PN junction diode, Tl...MOS
FET, T2... Parasitic MO8PET%C1...
... Contact hole, L ... Parasitic MO8FE
Source-drain spacing of T. ≦Scattered layer qda $lWJ
Claims (1)
基板とは逆導電型の第一のＮ型拡散層よりなる保護抵抗
を具備した保護回路を有する半導体集積回路装置におい
て、前記入力端子と前記第一のＮ型拡散層を接続するコ
ンタクト孔の近傍の前記第一のＮ型拡散層に寄生絶縁ゲ
ート型電界効果トランジスタが接続され、該寄生絶縁ゲ
ート型電界効果トランジスタは前記第一のＮ型拡散層を
取り囲むように、かつ該第一のＮ型拡散層より深く形成
された第二のＮ型拡散層（Ｎウェル）よりなるソース電
極を有し、また前記コンタクト孔の直下にも第二のＮ型
拡散層（Ｎウェル）を有することを特徴とする半導体集
積回路装置。In a semiconductor integrated circuit device having a protection circuit including a protection resistor formed of a first N-type diffusion layer having a conductivity type opposite to that of a P-type silicon substrate between an input terminal and a gate electrode of an internal circuit, the input terminal and A parasitic insulated gate field effect transistor is connected to the first N type diffusion layer near the contact hole connecting the first N type diffusion layer, and the parasitic insulated gate field effect transistor is connected to the first N type diffusion layer. It has a source electrode made of a second N-type diffusion layer (N-well) formed to surround the type diffusion layer and deeper than the first N-type diffusion layer, and also has a second N-type diffusion layer formed directly below the contact hole. A semiconductor integrated circuit device comprising two N-type diffusion layers (N-wells).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9710985A JPS61255055A (en) | 1985-05-08 | 1985-05-08 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9710985A JPS61255055A (en) | 1985-05-08 | 1985-05-08 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61255055A true JPS61255055A (en) | 1986-11-12 |
Family
ID=14183418
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9710985A Pending JPS61255055A (en) | 1985-05-08 | 1985-05-08 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61255055A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0413590A2 (en) * | 1989-08-18 | 1991-02-20 | Fujitsu Limited | Wafer scale integrated circuit device |
| US5276350A (en) * | 1991-02-07 | 1994-01-04 | National Semiconductor Corporation | Low reverse junction breakdown voltage zener diode for electrostatic discharge protection of integrated circuits |
-
1985
- 1985-05-08 JP JP9710985A patent/JPS61255055A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0413590A2 (en) * | 1989-08-18 | 1991-02-20 | Fujitsu Limited | Wafer scale integrated circuit device |
| US5276350A (en) * | 1991-02-07 | 1994-01-04 | National Semiconductor Corporation | Low reverse junction breakdown voltage zener diode for electrostatic discharge protection of integrated circuits |
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