JPH01194474A - Semiconductor input protecting device - Google Patents
Semiconductor input protecting deviceInfo
- Publication number
- JPH01194474A JPH01194474A JP63020283A JP2028388A JPH01194474A JP H01194474 A JPH01194474 A JP H01194474A JP 63020283 A JP63020283 A JP 63020283A JP 2028388 A JP2028388 A JP 2028388A JP H01194474 A JPH01194474 A JP H01194474A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- impurity diffusion
- type impurity
- diffusion layer
- well layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 239000012535 impurity Substances 0.000 claims abstract description 79
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000009792 diffusion process Methods 0.000 claims description 57
- 238000000926 separation method Methods 0.000 claims description 2
- 230000002159 abnormal effect Effects 0.000 abstract description 13
- 239000002784 hot electron Substances 0.000 abstract description 9
- 238000002513 implantation Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 77
- 229910052782 aluminium Inorganic materials 0.000 description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 5
- 239000011574 phosphorus Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 241000220317 Rosa Species 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野コ
本発明は入力端子に加えられる静電気などの外部サージ
から装置を保護するための入力保護回路を備えた半導体
装置に間する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor device equipped with an input protection circuit for protecting the device from external surges such as static electricity applied to input terminals.
［従来の技術］
半導体装置とくに絶縁ゲート型電界効果集積回路装置（
ＭＯＳＩＣ）では、ゲート絶縁膜として厚さ２００〜３
００Ａと非常に薄いシリコン酸化膜が使用されており摩
擦により生ずる静電気やノイズ電圧などにより容易に絶
縁破壊し、入力保護装置を設けないと実使用上支障があ
ることはよく知られている。また今後ＭＯ５ＩＣは高集
積化、高性能化がすすみ、ゲート絶縁膜はさらに薄膜化
の方向にあり、問題は重大となりつつある。[Prior art] Semiconductor devices, especially insulated gate field effect integrated circuit devices (
MOSIC), the gate insulating film has a thickness of 200 to 3
It is well known that since a very thin silicon oxide film of 00A is used, it easily breaks down due to static electricity caused by friction, noise voltage, etc., and that there is a problem in practical use unless an input protection device is provided. Furthermore, as MO5ICs become more highly integrated and performant, gate insulating films tend to become thinner, and the problem is becoming more serious.
第３図は、−船釣に使用されている半導体保護装置の等
価回路である。この等価回路は抵抗Ｒ１゜Ｒ２と、ゲー
トが入力端子Ｐと抵抗Ｒ１の一端に、ドレインが抵抗Ｒ
１の他端と抵抗Ｒ２の一端に、ソースが接地に接続され
たトランジスタＱ１と。FIG. 3 is an equivalent circuit of a semiconductor protection device used for boat fishing. This equivalent circuit consists of a resistor R1゜R2, a gate connected to the input terminal P and one end of the resistor R1, and a drain connected to the resistor R1.
1 and one end of the resistor R2, a transistor Q1 whose source is connected to ground.
ゲートとソースが接地にトレインが抵抗Ｒ２の他端と、
内部回路であるトランジスタＱ３の入カゲ−トに接続さ
れたトランジスタＱ２により構成されている。The gate and source are grounded, and the train is connected to the other end of resistor R2,
It consists of a transistor Q2 connected to the input gate of a transistor Q3 which is an internal circuit.
入力端子Ｐは通常、ボンディング用のアルミバットに接
続されている。またトランジスタＱ３は保護されるべき
トランジスタを表しており、そのゲート絶縁膜は前述の
ように厚さ２００〜３００Ａのシリコン酸化膜が使用さ
れる。トランジスタＱには、パンチスルートランジスタ
でソース・ドレイン間に２０Ｖ前後の異常電圧が印加さ
れると導通し、入力端子をクランプする働きがある。ト
ランジスタＱ２のゲート絶縁膜としては、トランジスタ
Ｑ３と同様のものを用いることが普通である。トランジ
スタＱ１はしきい値電圧が２０Ｖ程度のトランジスタ６
０００Ａ程度の厚いシリコン酸化膜がゲート絶縁膜とし
て用いられており、通常いわゆるチャンネルストッパ領
域と同時に形成される。抵抗Ｒ１，Ｒ２は時定数を設け
て入カバルス波形をなまらせ、またトランジスタＱ１あ
るいはＱ２が導通状態になった際に電流を制限する目的
があり、通常半導体基板と反対導電型の不純物拡散層あ
るいはリンなどの不純物を含んだ多結晶シリコン層で形
成することが多い。The input terminal P is normally connected to an aluminum butt for bonding. Further, the transistor Q3 represents a transistor to be protected, and its gate insulating film is a silicon oxide film having a thickness of 200 to 300 Å as described above. Transistor Q is a punch-through transistor, and when an abnormal voltage of around 20V is applied between the source and drain, it becomes conductive and has the function of clamping the input terminal. As the gate insulating film of the transistor Q2, the same one as that of the transistor Q3 is usually used. Transistor Q1 is transistor 6 with a threshold voltage of about 20V.
A silicon oxide film as thick as approximately 0.000A is used as a gate insulating film, and is usually formed at the same time as a so-called channel stopper region. The resistors R1 and R2 have the purpose of providing a time constant to blunt the input cavitation waveform and to limit the current when the transistor Q1 or Q2 becomes conductive. It is often formed from a polycrystalline silicon layer containing impurities such as phosphorus.
第４図は第３図の等何回路を半導体上に具体化した場合
の平面図て抵抗素子Ｒ１，Ｒ２として不純物拡散層を用
いている。FIG. 4 is a plan view of the circuit shown in FIG. 3 implemented on a semiconductor, in which impurity diffusion layers are used as resistance elements R1 and R2.
能動領域である不純物拡散層１０３，１０４Ａ。Impurity diffusion layers 103 and 104A are active regions.
１０４Ｂ、リンを含む多結晶シリコン層１０５、コンタ
クト開口部１１３Ａ、 １１３Ｂ、 １１３Ｃ１お
よびボンディングバット１０１とアルミ配線層１１１、
ボンディング用のパッドスルーホールパターン１０２を
それぞれ示す。ボンディング用パッド１０１はアルミパ
ターンで形成され半導体チップ表面全体を覆っているパ
ッシベーション膜（図示せず）でパッケージのり−ト電
極（図示せず）と接続できるようになっており、これが
第３図の入力端子Ｐに相当する。そしてポンディングパ
ッド１０１（入力端子Ｐ）はコンタクト開口部１１３Ａ
を通して不純物拡散層１０３（第３図の抵抗Ｒ１に相当
）と接続され、さらにこの不純物拡散層１０３（抵抗Ｒ
１）を経てトランジスタＱ１のトレイン領域に至る。ま
たトランジスタＱ１のソースを形成する不純物拡散層１
０４Ａはコンタクト開口部１１３Ｂを通して接地電位の
アルミ配線Ｎ１１１に接続され、さらに抵抗Ｒ２を形成
する不純物拡散層１０３の領域を経てトランジスタＱ２
のトレイン領域（図示せず）に至る。また接地電位に保
たれた多結晶シリコン層１０５によりトランジスタＱ２
のゲート電極（図示せず）が形成され、一方トランジス
タＱ２のソース（図示せず）を形成する不純物拡散層１
０４Ｂの領域はコンタクト開口部１１３Ｃを通して接地
電位のアルミ配線層１１１に接続されている。104B, polycrystalline silicon layer 105 containing phosphorus, contact openings 113A, 113B, 113C1, bonding bat 101 and aluminum wiring layer 111,
Pad through-hole patterns 102 for bonding are shown. The bonding pad 101 is formed of an aluminum pattern and can be connected to a package glue electrode (not shown) through a passivation film (not shown) covering the entire surface of the semiconductor chip, as shown in FIG. Corresponds to input terminal P. The bonding pad 101 (input terminal P) is connected to the contact opening 113A.
is connected to the impurity diffusion layer 103 (corresponding to the resistor R1 in FIG. 3) through the impurity diffusion layer 103 (corresponding to the resistor R1 in FIG.
1) and reaches the train region of transistor Q1. Also, the impurity diffusion layer 1 forming the source of the transistor Q1
04A is connected to the aluminum wiring N111 at ground potential through the contact opening 113B, and further connected to the transistor Q2 through the region of the impurity diffusion layer 103 forming the resistor R2.
to the train region (not shown). In addition, the polycrystalline silicon layer 105 kept at the ground potential causes the transistor Q2 to
A gate electrode (not shown) is formed, and an impurity diffusion layer 1 forms a source (not shown) of the transistor Q2.
The region 04B is connected to the aluminum wiring layer 111 at the ground potential through the contact opening 113C.
［発明が解決しようとする問題点コ
上述した従来の入力保護回路の１素子であるＭＯＳ）ラ
ンジスタ（第３図のＱｌ）は、トレイン不純物拡散層（
第４図の１０３）とＭＯＳ）ランジスタＱ１のゲートｗ
化膜であるフィールド酸化膜１０７Ａとが接しているた
め、入力端子（ボンディングバット’）１０１に異常電
圧が印加されるとソース不純物拡散層１０４Ａとトレイ
ン不純物拡散層１０３との間の高電界によってソース不
純物拡散層１０４Ａからトレイン不純物拡散層１０３へ
電子が流れ込み、大部分の電子はトレイン不純物拡散層
１０３へ抜けるが第６図に示すようここ一部十分に高い
エネルギーを持った電子（ホットエレクトロン）がＭ
ＯＳ ）ランジスタＱ１のトしイン不純物拡散Ｎ１０３
に接するフィールド酸化膜１０７への障壁を越えて入り
込み、注入されたホットエレクトロンは、フィールトド
酸化■莫１０７Ａ中のトラップに捕獲され、その結果負
電荷を発生し、その負電荷によって誘導された正電荷か
トレイン不純物拡散層１０３近傍の半導体基板１１０中
に発生してしまい、そのために第７図に示すようにトレ
イン不純物拡散層１０３とフィールド酸化膜１０７Ａと
が接する領域で形成される空乏層１１２幅が極めて小さ
くなりトレイン不純物拡散層１０３−半導体基板１１０
間の耐圧か下かってしまうという欠点がある。[Problems to be Solved by the Invention] The MOS transistor (Ql in FIG. 3), which is one element of the conventional input protection circuit described above, has a train impurity diffusion layer (
103) and MOS) gate w of transistor Q1 in Fig. 4
Since the field oxide film 107A is in contact with the field oxide film 107A, when an abnormal voltage is applied to the input terminal (bonding butt') 101, a high electric field between the source impurity diffusion layer 104A and the train impurity diffusion layer 103 Electrons flow from the impurity diffusion layer 104A to the train impurity diffusion layer 103, and most of the electrons escape to the train impurity diffusion layer 103, but as shown in FIG. 6, some electrons with sufficiently high energy (hot electrons) M
OS) Input impurity diffusion N103 of transistor Q1
The injected hot electrons enter across the barrier into the field oxide film 107 that is in contact with the field oxide film 107A, and are captured by the traps in the field oxide film 107A, thereby generating negative charges, and the positive charges induced by the negative charges. Therefore, as shown in FIG. 7, the width of the depletion layer 112 formed in the region where the train impurity diffusion layer 103 and the field oxide film 107A are in contact with each other increases. The train impurity diffusion layer 103-semiconductor substrate 110 becomes extremely small.
The disadvantage is that the withstand pressure between the two ends is reduced.
したがって、この状態で通常動作時に入力端子（ポンデ
ィングパッド）１０１に正電圧が印加されると前述のよ
うにトレイン不純物拡散層１０３−半導体基板１１０間
耐圧が低下しているため半導体基板１１０へ漏れ電流（
ｉｔ）が流れ、半導体デバイスの信頼性低下を引き起こ
す。Therefore, in this state, if a positive voltage is applied to the input terminal (ponding pad) 101 during normal operation, the withstand voltage between the train impurity diffusion layer 103 and the semiconductor substrate 110 has decreased as described above, so that it leaks to the semiconductor substrate 110. Current (
(it) flows, causing a decrease in the reliability of semiconductor devices.
［発明の従来技術に対する相違点コ。[Differences between the invention and the prior art]
上述した従来の半導体入力保護装置に対し、本発明は入
力端子に接続された第１の不純物拡散層を包含する第１
のウェル層と接地電位に接続された第２の不純物拡散層
を包含する第２のウェル層とが前記第１．第２の不純物
拡散層間の分離領域に形成された厚い絶縁膜下で等間隔
に平行に相対向する独創的内容を有する。In contrast to the conventional semiconductor input protection device described above, the present invention provides a first impurity diffusion layer connected to an input terminal.
A second well layer including a well layer and a second impurity diffusion layer connected to the ground potential is connected to the first well layer. It has an original content in which they face each other in parallel at equal intervals under a thick insulating film formed in the isolation region between the second impurity diffusion layers.
Ｅ問題点を解決するための手段］
本発明の半導体入力保護装置は、入力端子に接続された
一導電型の半導体基板に対して逆導電型の第１の不純物
拡散層を包含する前記第１の不純物拡散層と同導電型の
第１のウェル層と、接地電位に接続された前記第１の不
純物拡散層と同導電型の第２の不純物拡散層を包含する
前記第１のウェル層と同導電型の第２のウェル層とが、
前記第１、第２の不純物拡散層間の分離領域に形成され
た厚い絶縁膜下て等間隔に平行に相対向することを有し
ている。Means for Solving Problem E] The semiconductor input protection device of the present invention includes a first impurity diffusion layer of an opposite conductivity type to a semiconductor substrate of one conductivity type connected to an input terminal. a first well layer having the same conductivity type as the impurity diffusion layer; and a second impurity diffusion layer connected to a ground potential and having the same conductivity type as the first impurity diffusion layer; a second well layer of the same conductivity type,
The first and second impurity diffusion layers are arranged to face each other in parallel at regular intervals under a thick insulating film formed in a separation region between the first and second impurity diffusion layers.
［実施例］ 次に本発明について図面を参照して説明する。[Example] Next, the present invention will be explained with reference to the drawings.
第１図（ａ）は本発明の一実施例の平面図で、第１図（
ｂ）は第１図（ａ）のＸ−Ｙ線断面図を示し、第２図は
第１図（ｂ）の（１）の拡大図を示す。FIG. 1(a) is a plan view of one embodiment of the present invention.
b) shows a sectional view taken along the line X-Y in FIG. 1(a), and FIG. 2 shows an enlarged view of (1) in FIG. 1(b).
本実施例ではボンディングバラ）”１０１． ボンディ
ング用スルーホール１０２は、従来例と同様であるが、
ボンディングバット１０１はコンタクト開口部１０６Ａ
を介してＮ型不純物であるリンを含んだ低抵抗多結晶シ
リコン層１０５Ａに接続され、さらに他のコンタクト開
口部１０４Ａを介してＰ型半導体基板１１０上に形成さ
れたＮ型不純物拡散Ｎ１０３Ａに接続され、さらにＮ型
不純物拡散層１０３Ａを包囲してＮ型不純物拡散Ｎ１０
３Ａより深いＮ型不純物のウェルＪ’ｉｉ！１１５Ａが
形成されている。全く同様にＮ型不純物ウェル層１１５
ＡおよびＮ型不純物拡散Ｆ’１０３Ａと平行に隣接する
Ｎ型不純物拡散層１０３ＢおよびＮ型不純物拡散層１０
３Ｂを包囲するＮ型不純物ウェル層１１５Ｂが形感され
、Ｎ型不純物拡散Ｎ１０３Ｂと接地電位の金属（アルミ
）、配線１１１との接続もコンタクト開口部１０４Ｂ、
リンを含んだ多結晶シリコンＦ！１０５Ｂ、 コンタ
クト開口部１０６Ｂを介して形成されている。また、こ
の装置はバットスルーホール１０２の領域を除いて厚い
シリコン酸化膜１１６が被着されている。In this embodiment, the bonding rose) 101. The bonding through hole 102 is the same as the conventional example, but
The bonding butt 101 has a contact opening 106A.
is connected to a low resistance polycrystalline silicon layer 105A containing phosphorus, which is an N-type impurity, and further connected to an N-type impurity diffusion N103A formed on a P-type semiconductor substrate 110 via another contact opening 104A. Further, N-type impurity diffusion N10 surrounds the N-type impurity diffusion layer 103A.
N-type impurity well J'ii deeper than 3A! 115A is formed. In exactly the same way, the N-type impurity well layer 115
N-type impurity diffusion layer 103B and N-type impurity diffusion layer 10 adjacent in parallel to A and N-type impurity diffusion F'103A
The N-type impurity well layer 115B surrounding the N-type impurity well layer 115B is clearly visible, and the connection between the N-type impurity diffusion N103B and the ground potential metal (aluminum) and the wiring 111 is also formed through the contact opening 104B.
Polycrystalline silicon F containing phosphorus! 105B, formed through contact opening 106B. Further, in this device, a thick silicon oxide film 116 is deposited except for the area of the butt through hole 102.
Ｎ型不純物拡散層１０３Ａ及びＮ型不純物つェルｊ！１
１５ＡとＮ型不純物拡散層１０３Ｂ及びＮ型不純物つェ
ル＃１１５Ｂとは、互いに平行に隣接しており、この隣
接したＮ型不純物拡散層】０３Ａ、１０３Ｂに常に−様
な電界が加わるようにコンタクト開口部１０６Ａ、１０
４Ａ、１０４Ｂ。N-type impurity diffusion layer 103A and N-type impurity layer j! 1
15A, N-type impurity diffusion layer 103B, and N-type impurity well #115B are adjacent to each other in parallel, and a --like electric field is always applied to these adjacent N-type impurity diffusion layers 03A and 103B Contact openings 106A, 10
4A, 104B.
１０６Ｂの形状や、ボンデインクパッド１０１および金
属（アルミ）配線層１１１の端も前記隣接不純物拡散層
１０３Ａ、１０３Ｂと平行に配置されている。The shape of the bonding ink pad 101 and the ends of the metal (aluminum) wiring layer 111 are also arranged parallel to the adjacent impurity diffusion layers 103A and 103B.
この入力保護装置は、ポンディングパッド１０１に異常
電圧が印加されると、ボンディングバット１０１に接続
されたＮ型不純物拡散層１０３Ａ及びこれを包囲するＮ
型不純物つェルＪｉｌ１５Ａと接地電位に接続されてい
るＮ型不純物拡散層１０３Ｂおよびこれを包囲するＮ型
不純物ウェル層１１５Ｂとが極めて狭い間隙で隣接して
いるためパンチスルーを起こし短絡し、ボンディングパ
ラ１” １０１に印加された異常電圧を直ちに接地電位
に流し保護機能を果たす。In this input protection device, when an abnormal voltage is applied to the bonding pad 101, the N-type impurity diffusion layer 103A connected to the bonding pad 101 and the N-type impurity diffusion layer 103A surrounding this
Since the type impurity well layer 15A and the N-type impurity diffusion layer 103B connected to the ground potential and the N-type impurity well layer 115B surrounding it are adjacent to each other with an extremely narrow gap, punch-through occurs, causing a short circuit and bonding. The abnormal voltage applied to Para 1'' 101 is immediately passed to the ground potential to fulfill the protection function.
また本実施例においてはＮ型不純物拡散層１０３Ａ、１
０３Ｂより不純物領域の深いＮ型不純物つェルＪ”１１
５Ａ、１１５Ｂが設けられているためポンディングパッ
ド１０１に印加された異常電圧によって発生するホット
エレクトロンはＰ型半導体基板１１０内部を流れるため
ホットエレクトロンの厚いフィールド酸化膜１０７Ａ中
への注入減少は起こらず異常電圧耐圧に強い半導体デバ
イスを実現できる。Furthermore, in this embodiment, the N-type impurity diffusion layers 103A, 1
N-type impurity well J”11 with a deeper impurity region than 03B
5A and 115B are provided, the hot electrons generated by the abnormal voltage applied to the bonding pad 101 flow inside the P-type semiconductor substrate 110, so the injection of hot electrons into the thick field oxide film 107A does not decrease. It is possible to realize semiconductor devices that are resistant to abnormal voltages.
さらにポンディングパッド１０１の金属（アルミ）配線
とＮ型不純物拡散層１０３Ａとの間にリンを含んだ多結
晶シリコン１１０５Ａを挿入することにより異常電圧印
加による瞬時的に発生する異常電流で発熱し金属（アル
ミ）が溶融し、接合破壊を防止するためである。本実施
例の場合、多結晶シリコン層１０５Ａ、１０５Ｂが活性
化領域（Ｎ型不純物拡散１１０３Ａ、１０３Ｂ領域）上
に設ける際多結晶シリコン層を形成する前に不純物拡散
領域を形成しておく必要がある。Furthermore, by inserting polycrystalline silicon 1105A containing phosphorus between the metal (aluminum) wiring of the bonding pad 101 and the N-type impurity diffusion layer 103A, the abnormal current generated instantaneously due to the application of an abnormal voltage causes the metal to generate heat. This is to prevent the (aluminum) from melting and breaking the bond. In the case of this embodiment, when the polycrystalline silicon layers 105A and 105B are provided on the active regions (N-type impurity diffusion regions 1103A and 103B), it is necessary to form the impurity diffusion regions before forming the polycrystalline silicon layers. be.
［発明の効果コ
以上説明したように本発明は、入力端子に接続された第
１の不純物拡散層を包含する第１のウェル層と接地電位
に接続された第２の不純物拡散層を包含する第２のウェ
ル層とが第１．第２の不純物拡散層間の分離領域に形成
された厚い絶縁膜下て等間隔に平行に相対向することに
より、入力端子への異常電圧によって発生するホットエ
レクトロンが第１．第２のウェル層間で流れ、すなわち
半導体基板内部を流れるため、ホットエレクトロンの厚
いフィールド酸化膜中への注入現象を防止できる効果が
ある。[Effects of the Invention] As explained above, the present invention includes a first well layer including a first impurity diffusion layer connected to an input terminal and a second impurity diffusion layer connected to a ground potential. the second well layer; Hot electrons generated by an abnormal voltage applied to the input terminal are transferred to the first impurity diffusion layer by facing each other in parallel at regular intervals under the thick insulating film formed in the isolation region between the second impurity diffusion layers. Since it flows between the second well layers, that is, it flows inside the semiconductor substrate, it has the effect of preventing hot electron injection into the thick field oxide film.
第１図（ａ）は本発明の半導体入力保護装置の一実施例
の平面図、第１図（ｂ）は第１図（ａ）のＸ−Ｙ線断面
図、第２図は第１図（ｂ）の（Ｉ）の拡大図、第３図は
従来の半導体入力保護装置の等価回路図、第４図は第３
図の従来例の平面図、第５図は第４図のＸ’−Ｙ’線断
面図、第６図。
第７図はそれぞれ第５図の拡大図であり、それぞれ入力
端子に異常電圧印加時、印加後の状態を示す。
１０１・・・入力端子（ホンディングバット）、１０２
・・・パッドスルーホール、
１０３Ａ・・・入力端子に接続されたＮ型不純物拡散層
、
１０３Ｂ・・・接地電位に接続されたＮ型不純物拡散層
、
１０４Ａ、１０４Ｂ・・・Ｎ型不純物拡散層と多結晶シ
リコン層とを接
続するコンタクト、
１０５Ａ、１０５Ｂ・・・Ｎ型不純物のリンを含む多結
晶シリコン層、
１０６Ａ、１０６Ｂ・・・多結晶シリコン層と金属（ア
ルミ）配線層と
を接続するコンタクト、
１０７、 １０７Ａ・・・・フィールド酸化膜、１０８
・・・・・・・ＭＯＳゲート酸化膜、１０９・・・・・
・・層間絶縁膜、
１１０・・・・・・・Ｐ型半導体基板、１１１・・・・
・・・接地電位に接続された金属（アルミ）配線層、
１１２・・・・・・・空乏層、
１１３Ａ、１１３Ｂ、１１３Ｃ・・・・・・・・・・・
金属（アルミ）配線層とＮ型不純物拡散層を接続するコ
ンタクト、
１１４・・・・チャンネルストッパ用不純物領域、１１
５、Ａ、１１５Ｂ・・・・Ｎ型不純物ウェル層、Ｐ・・
・・・・入力端子（ボンデインクバット）、Ｒ１，Ｒ２
・・・・・Ｎ型不純物拡散層の抵抗、Ｑｌ、Ｑ２．Ｑ３
・・・・ＭＯＳ）ランジスタ。
特許出願人 日本電気株式会社
代理人 弁理士 桑 井 清 −
第２図
第５図
第６図
第７図FIG. 1(a) is a plan view of an embodiment of the semiconductor input protection device of the present invention, FIG. 1(b) is a sectional view taken along the X-Y line of FIG. 1(a), and FIG. An enlarged view of (I) in (b), Figure 3 is an equivalent circuit diagram of a conventional semiconductor input protection device, and Figure 4 is an equivalent circuit diagram of a conventional semiconductor input protection device.
FIG. 5 is a plan view of the conventional example shown in the figure, and FIG. 6 is a sectional view taken along the line X'-Y' of FIG. 4. FIG. 7 is an enlarged view of FIG. 5, and shows the state when and after the abnormal voltage is applied to the input terminal, respectively. 101... Input terminal (honding bat), 102
...Pad through hole, 103A...N type impurity diffusion layer connected to the input terminal, 103B...N type impurity diffusion layer connected to ground potential, 104A, 104B...N type impurity diffusion layer 105A, 105B...Polycrystalline silicon layer containing phosphorous as an N-type impurity; 106A, 106B...Contacts that connect the polycrystalline silicon layer and the metal (aluminum) wiring layer. Contact, 107, 107A...Field oxide film, 108
・・・・・・MOS gate oxide film, 109・・・・・・
...Interlayer insulating film, 110...P-type semiconductor substrate, 111...
...Metal (aluminum) wiring layer connected to ground potential, 112... Depletion layer, 113A, 113B, 113C...
Contact for connecting metal (aluminum) wiring layer and N-type impurity diffusion layer, 114... Impurity region for channel stopper, 11
5, A, 115B...N-type impurity well layer, P...
...Input terminal (bond ink butt), R1, R2
...Resistance of N-type impurity diffusion layer, Ql, Q2. Q3
...MOS) transistor. Patent applicant Kiyoshi Kuwai, agent for NEC Corporation, patent attorney - Figure 2 Figure 5 Figure 6 Figure 7
Claims (1)
端子に接続された一導電型の半導体基板に対して逆導電
型の第１の不純物拡散層を包含する前記第１の不純物拡
散層と同導電型の第１のウェル層と、 接地電位に接続された前記第１の不純物拡散層と同導電
型の第２の不純物拡散層を包含する前記第１のウェル層
と同導電型の第２のウェル層とが前記第１、第２の不純
物拡散層間の分離領域に形成された厚い絶縁膜直下で等
間隔に平行に相対向することを特徴とする半導体入力保
護装置。[Claims] In an input protection device provided in a semiconductor device, the first impurity layer includes a first impurity diffusion layer of an opposite conductivity type to a semiconductor substrate of one conductivity type connected to an input terminal. a first well layer having the same conductivity type as the diffusion layer; and a second impurity diffusion layer connected to the ground potential and having the same conductivity type as the first well layer. A semiconductor input protection device characterized in that the second well layer of the mold faces in parallel at regular intervals directly under a thick insulating film formed in a separation region between the first and second impurity diffusion layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63020283A JP2821128B2 (en) | 1988-01-29 | 1988-01-29 | Semiconductor input protection device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63020283A JP2821128B2 (en) | 1988-01-29 | 1988-01-29 | Semiconductor input protection device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01194474A true JPH01194474A (en) | 1989-08-04 |
| JP2821128B2 JP2821128B2 (en) | 1998-11-05 |
Family
ID=12022842
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63020283A Expired - Fee Related JP2821128B2 (en) | 1988-01-29 | 1988-01-29 | Semiconductor input protection device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2821128B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0422676A2 (en) * | 1989-10-12 | 1991-04-17 | Nec Corporation | Semiconductor input protection device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57153473A (en) * | 1981-03-17 | 1982-09-22 | Toshiba Corp | Semiconductor device with input and output protective circuit and its manufacturing method |
| JPS61144857A (en) * | 1984-12-19 | 1986-07-02 | Nec Ic Microcomput Syst Ltd | Mos type integrated circuit device |
-
1988
- 1988-01-29 JP JP63020283A patent/JP2821128B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57153473A (en) * | 1981-03-17 | 1982-09-22 | Toshiba Corp | Semiconductor device with input and output protective circuit and its manufacturing method |
| JPS61144857A (en) * | 1984-12-19 | 1986-07-02 | Nec Ic Microcomput Syst Ltd | Mos type integrated circuit device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0422676A2 (en) * | 1989-10-12 | 1991-04-17 | Nec Corporation | Semiconductor input protection device |
| EP0422676A3 (en) * | 1989-10-12 | 1991-08-07 | Nec Corporation | Semiconductor input protection device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2821128B2 (en) | 1998-11-05 |
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