JPH0775261B2 - Semiconductor input protection device - Google Patents

Description

The present invention relates to a semiconductor input protection device suitable for protecting an internal circuit, which is a main functional part, from an external surge such as static electricity applied to an input terminal.

[Prior Art] FIG. 3 shows an equivalent circuit diagram of a conventional semiconductor input protection device, and FIG. 4 shows a plan view of an example of the equivalent circuit.

In both figures, the semiconductor input protection circuit is composed of a resistor 1 made of polycrystalline silicon or an impurity diffusion layer, and a MOS transistor TR1.

The input wire passing through the through hole 6 is bonded to the input bonding pad 5a, and the resistor 1
The input bonding pad 5a is connected to one end of the one via a contact 3a.

In addition, the other end of the resistor 1 is connected to the MO via the contact 3b.
The drain 8 of the S transistor TR1 and the gate of the input transistor TR of the internal circuit are connected.

Furthermore, the polycrystalline silicon gate 2 of the MOS transistor TR1
Is connected to the metal wiring layer 5c at the ground potential via the contact 4 and the source 7 of the MOS transistor TR1.
Is connected to the metal wiring layer 5c.

Then, the parasitic capacitance Cs existing at the node A (metal wiring layer 5b)
Time constant τ determined by t and the resistance value R of the impurity diffusion layer resistor 1
= Cst · R lowers the peak voltage of the external surge applied from the input terminal, and the punch-through of the MOS transistor TR1 is used to release the charge of the surge.
By lowering the voltage at the gate of the input transistor TR (device body), the electric field strength applied between the gate and the substrate is reduced to prevent destruction of the gate oxide film.

Incidentally, the resistor 1, for example, when formed on a P-type substrate with N-type impurity diffusion layer is inevitably formed by N ⁺ -type impurity diffusion region of the resistor 1 and the P-type substrate N ⁺ P The diode breaks down due to the external surge voltage from the input terminal, and the breakdown current flows to the substrate due to the reverse characteristic of the N ⁺ P diode. As a result, the input surge applied to the resistor 1 is reduced.

[Problems to be Solved by the Invention] A MOS which is one element of the conventional semiconductor input protection device described above.
In the transistor (denoted by TR1 in FIG. 3 and denoted by reference numeral 2 in FIGS. 5 and 6), a boundary P1, between the active region and the field oxide film 10 formed by the known LOCOS formation method, is used.
At the P2 portion, as shown in FIG. 6, the drain impurity diffusion layer 8
Since the field oxide film 10 and the field oxide film 10 are in contact with each other, when an abnormal voltage such as static electricity is applied to the input terminal (bonding pad) 5a in FIG. 4, the source impurity diffusion layer 7 and the drain impurity diffusion layer 8 are separated from each other. A high electric field is generated, and electrons flow from the source impurity diffusion layer 7 into the drain impurity diffusion layer 8.

At that time, most of the electrons flow to the drain impurity diffusion layer 8, but as shown in FIG. 6, some of the electrons become electrons having sufficiently high energy (hot electrons), and the drain impurity diffusion of the MOS transistor TR1 is performed. It penetrates beyond the barrier of field oxide 10 in contact with layer 8.

Then, the injected hot electrons are captured by the trap levels in the field oxide film 10, and as a result, positive charges induced by the negative charges trapped in the field oxide film 10 are generated in the vicinity of the drain impurity diffusion layer 8. It occurs in the semiconductor substrate 13.

Therefore, as shown in FIG. 6, the depletion layer 14 formed in the regions P1 and P2 in which the drain impurity diffusion layer 8 and the field oxide film 10 are in contact with each other becomes extremely small, so that the drain impurity diffusion layer 8-the semiconductor substrate 13 The withstand voltage of is lowered.

Therefore, if a positive voltage is applied to the input terminal (bonding pad 5a) during normal operation in this state, the withstand voltage between the drain impurity diffusion layer 8 and the semiconductor substrate 13 is lowered as described above, so that the semiconductor substrate 13 is Leakage current flows, which causes a decrease in reliability as a semiconductor device.

An object of the present invention is to provide a semiconductor input protection device capable of maintaining the reliability of a semiconductor device at a high level.

[Differences from the Prior Art of the Invention] In contrast to the conventional semiconductor input protection device described above, the present invention is
In a MOS transistor, which is composed of a drain impurity diffusion layer connected to the input terminal, a source impurity diffusion layer connected to the ground potential, and a gate electrode, and constitutes one element for input protection, a field oxide film and an activation region are provided. In a spherical region within a radius of 1 μm centering on a contact formed in the activation region as a drain and source impurity diffusion layer, the drain and the source. The difference is that an impurity diffusion layer to be an impurity diffusion layer is not formed.

[Means for Solving Problems] A main functional part of a semiconductor device, which is connectable to an input terminal of a device body to be protected and is provided in an activation region of a substrate made of one conductivity type semiconductor. The drain impurity diffusion layer formed, the source impurity diffusion layer formed in the activation region of the substrate connected to the ground potential and separated from the drain impurity diffusion layer, and surrounding the activation region of the substrate, A field f oxide film formed on the substrate, a gate insulating film covering at least an activation region between the drain impurity diffusion layer and the source impurity diffusion layer, and connected to a ground potential formed on the gate insulating film And a drain impurity diffusion layer portion and a source impurity diffusion layer portion adjacent to both sides of the gate electrode are separated from the field oxide film by a predetermined distance. A semiconductor input protection device characterized by being formed as follows.

EXAMPLES Next, the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of an embodiment of the present invention, and FIG. 2 is a sectional view taken along line II-II in FIG.

In FIGS. 1 and 2, the same parts as those in FIGS. 3 to 6 showing the conventional example are designated by the same reference numerals and the description thereof will be omitted.

According to the present invention, the impurity (for example, N-type impurity; As) implantation region 16 is formed into the shape shown in FIG. 1, so that the polycrystalline silicon layer 2 of the gate electrode of the MOS transistor TR1 which is one element of the input protection circuit and the field. Oxide film 10 and activation region 15
Boundary P1 and P2 with (at least a radius of 1 μm)
The impurity diffusion layer is not formed in.

That is, in that region, the impurity diffusion layer (which becomes the drain or the source) is formed with a desired gap with respect to the field oxide film 10.

It should be noted that the manufacturing method can be realized by a known manufacturing process in today's semiconductor devices in which CMOS (complementary MOS) transistors are becoming mainstream. Specifically, when forming the N-channel side, Further, it may be formed in the shape shown in FIG.

When an abnormal voltage is applied to the input bonding pad 5a having the semiconductor input protection device according to the present invention, the MOS
An abnormal voltage is transmitted to the drain impurity diffusion layer 8 of the transistor TR1, and a high electric field is applied between the drain impurity diffusion layer 8-source impurity diffusion layer 7 and the source impurity diffusion layer 7
Electrons flow from the metal (aluminum) wiring layer 5c of ground potential connected to the source impurity diffusion layer 7 to the drain impurity diffusion layer 8.

At this time, as shown in FIGS. 1 and 2, the boundary region between the field oxide film 10 and the activation region 15 formed with LOCOS and the MOS.
Since the impurity diffusion layers are not formed in the boundary regions P1 and P2 where the polycrystalline silicon layer 2 which is the gate electrode of the transistor TR1 intersects, the boundary regions P1 and P2 have extremely high resistance, and as described above, Electrons flowing from the source impurity diffusion layer 7 into the drain impurity diffusion layer 8 cannot pass through the boundary regions P1 and P2.

Therefore, an abnormal voltage is applied to the input bonding pad 5a, and hot electrons generated by the high electric field applied between the drain 8 and the source 7 of the MOS transistor TR1 pass through the boundary regions P1 and P2 between the field oxide film 10 and the activation region 15. Since it cannot flow, hot electrons are not injected into the field oxide film 10, and no leakage current from the drain impurity diffusion layer 8 to the semiconductor substrate 13 occurs.

Therefore, the main functional portion (apparatus body) as a semiconductor device is surely protected, so that the reliability is maintained at a high level.

[Effects of the Invention] As described above, the present invention provides a one-input protection element including a drain impurity diffusion layer connected to an input terminal, a source impurity diffusion layer connected to a ground potential, a gate electrode, and the like. Since the impurity diffusion layer is not formed in a part of the activation region serving as the drain-source region in the vicinity of the region where the boundary region between the field oxide film and the activation region intersects with the gate electrode. , The hot electrons generated between the drain and the source due to the abnormal voltage applied to the input terminal are not injected into the field oxide film, and as a result, the leakage current from the drain impurity diffusion layer to the semiconductor substrate does not occur. The breakdown voltage can be improved.

Therefore, it becomes possible to maintain the reliability of the apparatus main body at a high level.

[Brief description of drawings]

1 is a plan view showing an embodiment of a semiconductor input protection circuit device of the present invention, FIG. 2 is a sectional view taken along line II-II in FIG.
FIG. 3 is an equivalent circuit diagram of a conventional semiconductor input protection circuit, and FIG.
The figure is a plan view of an example of the equivalent circuit shown in FIG.
FIG. 5 is an enlarged view of the MOS transistor shown in FIG.
FIG. 6 is a sectional view taken along line VI-VI in FIG. 1 ... Resistor, 2 ... Polycrystalline silicon layer gate, 3a, 3b, 3c ... Contact between metal wiring (aluminum) layer and impurity diffusion layer, 4 ... Metal wiring (aluminum) layer and polycrystalline silicon layer Contact with, 5a, 5b, 5c …… Metal wiring (aluminum) layer, 6 …… Through hole, 7 …… Source impurity diffusion layer, 8 …… Drain impurity diffusion layer, 9 …… Interlayer insulation film, 10 …… Field oxide film, 11 ... Gate oxide film, 12 ... Impurity diffusion layer for channel stopper, 13 ... Semiconductor substrate, 14 ... Depletion layer, 15 ... Activation region, 16 ... Impurity implantation region.

Claims (1)

[Claims] 1. A drain impurity which is a main functional part of a semiconductor device and which can be connected to an input terminal of a device body to be protected and which is formed in an activation region of a substrate made of a semiconductor of one conductivity type. A diffusion layer, a source impurity diffusion layer formed in an activation region of the substrate, which is connected to a ground potential and separated from the drain impurity diffusion layer, and an activation region of the substrate, and formed in the substrate. A field oxide film, a gate insulating film covering an activation region between at least the drain impurity diffusion layer and the source impurity diffusion layer, and a gate electrode formed on the gate insulating film and connectable to a ground potential And a drain impurity diffusion layer portion and a source impurity diffusion layer portion which are adjacent to both sides of the activation region below the gate electrode. The semiconductor input protection device, characterized in that the de-oxidation film by a predetermined distance apart.