JPS6196757A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6196757A JPS6196757A JP21771184A JP21771184A JPS6196757A JP S6196757 A JPS6196757 A JP S6196757A JP 21771184 A JP21771184 A JP 21771184A JP 21771184 A JP21771184 A JP 21771184A JP S6196757 A JPS6196757 A JP S6196757A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- type
- layer region
- substrate
- type diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 230000015556 catabolic process Effects 0.000 claims abstract description 25
- 230000002265 prevention Effects 0.000 claims description 24
- 239000012535 impurity Substances 0.000 claims description 8
- 238000009792 diffusion process Methods 0.000 abstract description 36
- 238000000034 method Methods 0.000 abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 11
- 229910052710 silicon Inorganic materials 0.000 abstract description 11
- 239000010703 silicon Substances 0.000 abstract description 11
- 238000007599 discharging Methods 0.000 abstract description 4
- 230000003405 preventing effect Effects 0.000 abstract description 4
- 230000003068 static effect Effects 0.000 abstract description 4
- 238000007796 conventional method Methods 0.000 abstract 1
- 230000006378 damage Effects 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 150000002894 organic compounds Chemical class 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 210000003128 head Anatomy 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 210000003141 lower extremity Anatomy 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
(技術分野)
本発明は半導体集積回路装置の静電破壊防止素子に関す
る。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an electrostatic breakdown prevention element for a semiconductor integrated circuit device.
(従来技術)
半導体集積回路装置の静電破壊防止対策の為の一般的方
法の1つとして、従来は、集積回路における端子(ポン
ディングパッド)と内部回路との間に直列に抵抗を挿入
したりダイオードを設けることが行なわれてきた。(Prior Art) One of the general methods for preventing electrostatic damage in semiconductor integrated circuit devices is to insert a resistor in series between the terminal (ponding pad) of the integrated circuit and the internal circuit. It has been practiced to provide a diode.
即ち、第1図に示すように、静電破壊防止素子は端子(
A)と内部回路(B)との間に配置され、例えばP型半
導体基板11の表面にN+型拡散層領域14を形成した
本ので、咳N 型拡散層領域14上にコンタクト開口部
16.17を形成し、端子側(A)と内部回路側(B)
とにそれぞれアルミ配線層18.19で接続させている
。第2図は第1図において一点鎖線で示した(A) −
(B)間の断面図を示すもので、12はフィールド酸化
膜下部に形成されたチャンネルストッパの為のP+型拡
散層領域13は周知の選択酸化法で形成されたフィール
ド酸化膜、15は眉間絶縁の為の気相成長法によるシリ
コン酸化膜で、その他は第1図に対応している。上述し
た静電破壊防止素子の等価回路は、第3図に示すとおり
N 型拡散層領域14から成る抵抗Rと、該N 型拡散
層・領域14とP型半導体基板11とから成るダイオー
ドDで構成されている。That is, as shown in Fig. 1, the electrostatic breakdown prevention element has a terminal (
A) and the internal circuit (B), for example, since the N+ type diffusion layer region 14 is formed on the surface of the P type semiconductor substrate 11, the contact opening 16. 17, terminal side (A) and internal circuit side (B)
These are connected to each other by aluminum wiring layers 18 and 19, respectively. Figure 2 shows (A) − indicated by the dashed line in Figure 1.
(B) shows a cross-sectional view between 12 and 12, where 12 is a P+ type diffusion layer region 13 for a channel stopper formed under the field oxide film, and 15 is a field oxide film formed by a well-known selective oxidation method; 15 is between the eyebrows. This is a silicon oxide film grown using a vapor phase growth method for insulation, and the rest corresponds to that shown in FIG. As shown in FIG. 3, the equivalent circuit of the electrostatic breakdown prevention element described above includes a resistor R consisting of an N type diffusion layer region 14, and a diode D consisting of the N type diffusion layer/region 14 and a P type semiconductor substrate 11. It is configured.
上記静電7壊防止素子の動作については、端子(A)に
マイナスパルス(→が入った場合、N+型型数散層頭載
14とP型半導体基板11とから成るダイオードDが順
バイアスされ基板11より電流を吸い込む。この場合、
電流直は、ダイオードDの順方向抵抗、コンタクト抵抗
、ダイオードの順方向電流の放流能力等で決定される。Regarding the operation of the electrostatic discharge prevention device, when a negative pulse (→) is applied to the terminal (A), the diode D consisting of the N+ type scattering layer head 14 and the P type semiconductor substrate 11 is forward biased. A current is sucked from the substrate 11. In this case,
The current directivity is determined by the forward resistance of the diode D, the contact resistance, the forward current discharge ability of the diode, etc.
通常、コンタクト抵抗は、コンタクトサイズを大きくす
る事ヶ により十分に小さくされており、又
、ダイオードの順方向電流の放流能力も通常は十分に大
きいので、内部回路は靜゛ζ破壊から免れる。Normally, the contact resistance is made sufficiently small by increasing the contact size, and the diode's forward current discharging ability is usually sufficiently large, so the internal circuit is protected from static damage.
一方、正の#電パルス(+)が端子に入った場合N+を
拡散、層領域14とP型半導体基板11から成るダイオ
ードは逆バイアスされ、ダイオードの逆方向ブレークダ
ウン4圧を越えると電流は該基板11へ流れ込む。なお
一般にMO8q半導体集積回路装置の場合、内部回路へ
の入力はゲートとなっており、ゲート絶縁耐圧以上の電
圧が内部回路へ入力きれるとゲートの破壊を招くのだが
、この場合、前記逆方向ブレークダウン五圧はゲート絶
縁耐圧に比べ十分に低い1直に設定されておりゲートの
壊壊を防止している。しかしながらこの場合、通常のN
MO8型半導体装置では、フィールド酸化膜下部にチャ
ンネルストッパの為の基板の不純物濃度より濃度の尚い
P 型拡散層領域12が形成されており、ダイオードの
逆方向ブレークダウンは、空乏層の広がりの最も少ない
前記P+型拡散層領域12とN+型型数散層領域14の
接合部分で起こることになり、静電パルス印加時初期に
流れる瞬時大を流は、この部分に集中し、この部分の電
流放流能力が不十分だと、静電破壊防止素子としてのこ
の部分のP”N+ダイオード自身の破壊を招くことにな
る。従って従来の半導体装置構造では、上記破壊を防止
する為に上記接合部分の面積を増加する為のN 型拡散
層領域14の面積を十分に大きくすること、および上記
接合部分に流れる電流値を制限する為に抵抗素子を付は
加えたりすることが必要となり、静電破壊防止素子領域
の面積の増加を招いていた。On the other hand, when a positive # electric pulse (+) enters the terminal, the diode consisting of the layer region 14 and the P-type semiconductor substrate 11 is reverse biased by diffusing N+, and when the reverse breakdown of the diode exceeds 4 voltage, the current decreases. The liquid flows into the substrate 11. Generally, in the case of MO8q semiconductor integrated circuit devices, the input to the internal circuit is the gate, and if a voltage higher than the gate dielectric breakdown voltage is input to the internal circuit, the gate will be destroyed, but in this case, the reverse break The down voltage is set to 1 voltage, which is sufficiently lower than the gate dielectric strength voltage, to prevent the gate from being destroyed. However, in this case, the normal N
In the MO8 type semiconductor device, a P-type diffusion layer region 12 with a concentration lower than that of the substrate for the channel stopper is formed under the field oxide film, and the reverse breakdown of the diode is caused by the expansion of the depletion layer. This occurs at the junction between the P+ type diffused layer region 12 and the N+ type diffused layer region 14, which is the smallest in number, and the instantaneous flow that flows at the beginning when an electrostatic pulse is applied is concentrated in this part, and the flow in this part is If the current discharging ability is insufficient, the P''N+ diode itself in this part, which acts as an electrostatic damage prevention element, will be destroyed. Therefore, in the conventional semiconductor device structure, in order to prevent the above-mentioned destruction, the junction part It is necessary to make the area of the N-type diffusion layer region 14 sufficiently large to increase the area of This resulted in an increase in the area of the destruction prevention element region.
(発明の目的)
本発明の目的は、上述した従来の半導体装置における静
電破壊防止素子の改善にあり、静電破壊防止素子に要す
るパターン面積を増加させることなく、静電破壊防止素
子の一部として使用されるダイオードの電流放流能力を
増加させて、静電破壊防止素子としての効果を増す半導
体装置構造を提供することにある。(Objective of the Invention) An object of the present invention is to improve the electrostatic breakdown prevention element in the conventional semiconductor device described above, and to improve the electrostatic breakdown prevention element without increasing the pattern area required for the electrostatic breakdown prevention element. It is an object of the present invention to provide a semiconductor device structure that increases the current discharge capability of a diode used as a component, thereby increasing its effectiveness as an electrostatic breakdown prevention element.
(発明の構成)
本発明の半導体装置は、端子と内部回路との間に、少な
くとも、第1導電型の半導体基板内部に埋め込まれて上
面および底面が該半導体基板と接する第2導電型の半導
体領域から成る抵抗と、前記第1導電型の半導体基板と
前記第2導電型の半導体領域とから形成されるダイオー
ドとを含む静電破壊防止素子を有することを特徴とする
ものである。(Structure of the Invention) The semiconductor device of the present invention includes at least a semiconductor of a second conductivity type that is embedded inside a semiconductor substrate of a first conductivity type and whose top surface and bottom surface are in contact with the semiconductor substrate, between a terminal and an internal circuit. The device is characterized in that it has an electrostatic breakdown prevention element including a resistor formed of a region, and a diode formed from the semiconductor substrate of the first conductivity type and the semiconductor region of the second conductivity type.
(実施例) 以下、本発明を図面に従って説明する。(Example) The present invention will be explained below with reference to the drawings.
第4図は、本発明の一実施例を示す半導体装置における
静電破壊防止素子部分を示す平面図で、(A)は端子側
(B′)は内部回路側となりている。第4図において、
21はP型シリコン基板、22は綜基板内部に埋め込ま
れたN 型拡散層領域、25゜26は該基板表面から該
N 型拡散層領域22の上面に接するまでの深さを有す
るN 型拡散層領域、28.29はコンタクト開口部、
30.31は、該コンタクト開口部28.29を介して
、前記N+型型数散層領域5 、26と接続され、それ
ぞれ内部回路側および端子側に延長されているアルミ配
線層である。第5図は、第4図において一点鎖線で示し
だ(A’) −(B’)間の断面図を示すもので、21
はP型シリコン基板、22は該基板内部に埋め込まれ九
N 型拡散層領域、23はフィールド領域下部に形成さ
れたP 型拡散層から成るチャンネルストッパ領域、2
4は選択酸化法により形成されたフィールド酸化膜、2
5.26はN 型拡散層領域で、その底部は前記基板内
部に埋め込まれたNfi拡散層22と接続されている。FIG. 4 is a plan view showing an electrostatic breakdown prevention element portion in a semiconductor device according to an embodiment of the present invention, in which (A) the terminal side (B') is the internal circuit side. In Figure 4,
21 is a P-type silicon substrate, 22 is an N-type diffusion layer region buried inside the helical substrate, and 25°26 is an N-type diffusion layer having a depth from the substrate surface to contact with the upper surface of the N-type diffusion layer region 22. layer region, 28.29 is a contact opening;
Reference numerals 30 and 31 denote aluminum wiring layers connected to the N+ type scattered layer regions 5 and 26 through the contact openings 28 and 29, and extended toward the internal circuit side and the terminal side, respectively. FIG. 5 shows a cross-sectional view between (A') and (B') indicated by the dashed line in FIG.
2 is a P-type silicon substrate, 22 is a N-type diffusion layer region buried in the substrate, 23 is a channel stopper region formed under a field region and is composed of a P-type diffusion layer;
4 is a field oxide film formed by a selective oxidation method, 2
5.26 is an N type diffusion layer region, the bottom of which is connected to the Nfi diffusion layer 22 buried inside the substrate.
−27は気相。-27 is gas phase.
成長法により形成されたシリコン酸化膜、28 、29
は該シリコン酸化膜27に選択的に設けられたコンタク
ト開口部、30.31はアルミ配線層で、それぞれ内部
回路および端子に接続されている。Silicon oxide film formed by growth method, 28, 29
30 and 31 are contact openings selectively provided in the silicon oxide film 27, and aluminum wiring layers 30 and 31 are connected to internal circuits and terminals, respectively.
本構造において重要なことは、端子(ポンディングパッ
ド)と内部回路とは、シリコン基板内部に埋め込まれた
該基板とは逆導電型の拡散層領域を介して接続されてい
るということであり、静電破壊防止素子としての端子と
内部回路との間のパターン面積を増すことなく、P型シ
リコン基板21とN 型拡散層領域22とから成るダイ
オードの実効面積が増加する。また、該ダイオードの逆
方向ブレークダウンは、P 型拡散層領域から成るチャ
ンネルストッパ23とNu拡散層領域22との接触部分
で生ずるが、本発明構造ではこの部分の接触面積もN
型拡散層領域22の上面部の分だけ従来より大きくなる
ので、電流放流能力の増加が実現できるものである。従
って、静電破壊防止素子としての効果が大きくなるので
ある。What is important in this structure is that the terminals (ponding pads) and internal circuits are connected through a diffusion layer region of the opposite conductivity type to that of the silicon substrate, which is embedded inside the silicon substrate. The effective area of the diode consisting of the P-type silicon substrate 21 and the N-type diffusion layer region 22 is increased without increasing the pattern area between the terminal as an electrostatic breakdown prevention element and the internal circuit. Further, the reverse breakdown of the diode occurs at the contact area between the channel stopper 23 made of the P type diffusion layer region and the Nu diffusion layer region 22, but in the structure of the present invention, the contact area of this portion is also N
Since the upper surface portion of the type diffusion layer region 22 is larger than the conventional one, an increase in current discharge capability can be realized. Therefore, the effect as an electrostatic damage prevention element is increased.
次に、本発明における構造の作製方法を、内部回路部分
を含め第6図(a)〜第6図(e)を用いて説明する。Next, a method for manufacturing the structure according to the present invention will be explained using FIGS. 6(a) to 6(e) including the internal circuit portion.
まず、第6図(JL)に示すように、P型シリコン基板
101の主面側に熱酸化法でシリコン酸化膜102を形
成し、フォトレジスト103を塗布して周知のフォトエ
ツチング法によりバターニングする。First, as shown in FIG. 6 (JL), a silicon oxide film 102 is formed on the main surface side of a P-type silicon substrate 101 by a thermal oxidation method, a photoresist 103 is applied, and buttering is performed by a well-known photoetching method. do.
次に第6図(b)に示すように、フォトレジスト103
を除去し、全面に砒素入りの有機化合物溶液を塗布し6
00℃はどの低温で焼き固めた後、1100℃はどの高
温で熱拡散法により選択的にN+型型数散層領域104
形成し、その後、前記有機化合物溶液、シリコン酸化膜
を全面除去する。なおこの塗布の際の有機化合物溶液の
砒素の濃度は、N+型型数散層領域104形成後不純物
濃度が、この後肢N 型拡散層領域104上に接続して
形成されるN+型型数散層領域不純物濃度と同程度とな
るように設定する。Next, as shown in FIG. 6(b), the photoresist 103
was removed and an organic compound solution containing arsenic was applied to the entire surface.
After baking and hardening at a low temperature of 00℃ and a high temperature of 1100℃, the N+ type scattered layer region 104 is selectively formed using a thermal diffusion method.
After that, the organic compound solution and silicon oxide film are completely removed. Note that the concentration of arsenic in the organic compound solution during this coating is such that the impurity concentration after the formation of the N+ type diffused layer region 104 is the same as that of the N+ type diffused layer formed by connecting to this hind limb N type diffused layer region 104. The impurity concentration is set to be approximately the same as the layer region impurity concentration.
次に第6図(C)に示すように、全面に基板と同程度の
不純物濃度を有するP型シリコン層105をエピタキシ
ャル成長法により被着する。このときN fM拡散層
領域104はエピタキシャルシリコン層105にも拡散
される。Next, as shown in FIG. 6C, a P-type silicon layer 105 having an impurity concentration comparable to that of the substrate is deposited over the entire surface by epitaxial growth. At this time, the N fM diffusion layer region 104 is also diffused into the epitaxial silicon layer 105 .
次に第6図(d)に示すように、通常のMO8型半導体
集積回路装置の製法に従い、選択酸化法によりフィール
ド酸化膜106を形成するとともに、チャンネルストッ
パ用のP 型拡散層領域107をフィールド酸化膜下部
に形成し、次いで、ゲート酸化膜108を熱酸化法によ
り形成し、その後多結晶シリコン層を気相成長法により
形成し、周知のフォトエツチング法により多結晶シリコ
ンゲート電極109を形成し、その後、前記フィールド
酸化膜106および多結晶シリコンゲート電極1^0ル
岬ツhLIイ 良禽もノ↓・1片11 ・立当な熱処
理を施して前記N 型拡散層領域104に接続するほど
の深さを有するN 型拡散層領域110.111,11
2を形成する。Next, as shown in FIG. 6(d), a field oxide film 106 is formed by a selective oxidation method according to the usual manufacturing method for MO8 type semiconductor integrated circuit devices, and a P type diffusion layer region 107 for a channel stopper is formed in the field. Next, a gate oxide film 108 is formed by a thermal oxidation method, a polycrystalline silicon layer is formed by a vapor phase epitaxy method, and a polycrystalline silicon gate electrode 109 is formed by a well-known photoetching method. , After that, the field oxide film 106 and the polycrystalline silicon gate electrode 1^0 are connected to the N type diffusion layer region 104 by performing appropriate heat treatment. N type diffusion layer regions 110, 111, 11 with a depth of
form 2.
次に第6図(e)に示すように、全面に気相成長法によ
りシリコン酸化膜113を形成し、周知のフォトエツチ
ング法によりコンタクト開口部114゜115.116
を形成し、その後アルミ配線/W117゜118を形成
した。なおアルミ配線層117は内部回路である多結晶
シリコンゲート電極109へ接続され、アルミ配線層1
18は端子(ポンディングパッド)部へ延長されており
、両方のアルミ配線層は、コンタクト開口部115,1
16およびN+型型数散層領域111104,112を
介して接続される。Next, as shown in FIG. 6(e), a silicon oxide film 113 is formed on the entire surface by vapor phase growth, and contact openings 114, 115, 116 are formed by a well-known photoetching method.
was formed, and then aluminum wiring /W117°118 was formed. Note that the aluminum wiring layer 117 is connected to the polycrystalline silicon gate electrode 109 which is an internal circuit, and the aluminum wiring layer 1
18 is extended to the terminal (ponding pad) part, and both aluminum wiring layers are connected to the contact opening 115,1.
16 and N+ type scattering layer regions 111104 and 112.
(発明のまとめ)
以上のようにして得られたMO8型半導体装置は、端子
と内部回路との間に、靜1破壊防止素子として半導体基
板内部に埋め込まれた基板とは逆導電型の拡散層領域が
存在して、抵抗およびダイオードとして動作するので、
従来、L−仕べて靜雷破壊防止素子の為の面積を増すこ
となく、静電破壊防止素子としてのダイオードの電流放
流能力を増すことができ、静電破壊防止効果が犬きくな
るものである。。(Summary of the Invention) The MO8 type semiconductor device obtained as described above has a diffusion layer of a conductivity type opposite to that of the substrate embedded in the semiconductor substrate as a destruction prevention element between the terminal and the internal circuit. Since a region exists and acts as a resistor and a diode,
Conventionally, the current discharging capacity of the diode as an electrostatic breakdown prevention element can be increased without increasing the area for the electrostatic breakdown prevention element, and the electrostatic breakdown prevention effect is even greater. be. .
なお、上記実施例ではP型半導体基板を用いた場合を示
したが、N型半導体基板に対しても適用可能である。ま
たN型拡散層領域を得る為の不純物として砒素を用いた
が、他の不純物を用いることも可能である。さらに、上
記実施例では静電破壊防止素子として、拡散層抵抗およ
びダイオードのみの場合を示したが、静電破壊防止効果
をさらに増す為に、トランジスタや多結晶シリコン層か
ら成る抵抗等を付は加えても良い。Note that although the above embodiment shows a case in which a P-type semiconductor substrate is used, the present invention is also applicable to an N-type semiconductor substrate. Furthermore, although arsenic was used as an impurity to obtain the N-type diffusion layer region, other impurities may also be used. Furthermore, in the above embodiment, only a diffused layer resistor and a diode were used as the electrostatic damage prevention element, but in order to further increase the electrostatic damage prevention effect, it is possible to add a resistor made of a transistor or a polycrystalline silicon layer. You can also add it.
第1図は、従来の半導体装置における端子と内部回路と
の間に設けられる静電破壊防止素子としての拡散層抵抗
とダイオードのパターンを示す平面図。第2図は第1図
における(A) −(B)部分の断面図。第3図は第1
図における静電破壊防止素子を示す回路図。第4図は本
発明の半導体装置における端子と内部回路との間に存在
する静電破壊防止素子としての拡散層抵抗とダイオード
のパターンを示す平面図。第5図は第4図における(A
′)−(B’)部分の断面図。第6図(a)〜第6図(
e)は本発明の実施例の構造を得る為の製造工程順を示
す断面図。
21・・・・・・P型シリコン基板、22・・・・・・
基板内部に埋め込まれたN+型型数散層領域23・・・
・・・チャンネルストッパとなるP 型拡散層領域、2
4・・・・・・フィールド酸化膜、25.26・・・・
・・N+型型数散層領域28.29・・・・・・コンタ
クト開口部、30.31・・・・・・アルミニウム配線
層である。
第3図
L ++ J
作図14
第6図(cl’)
弗6図(b)
停6図(C)
第6図(d)
第6図(e”1FIG. 1 is a plan view showing a pattern of a diffusion layer resistor and a diode as an electrostatic breakdown prevention element provided between a terminal and an internal circuit in a conventional semiconductor device. FIG. 2 is a sectional view of the (A)-(B) portion in FIG. 1. Figure 3 is the first
FIG. 3 is a circuit diagram showing the electrostatic breakdown prevention element shown in the figure. FIG. 4 is a plan view showing a pattern of a diffusion layer resistor and a diode as an electrostatic breakdown prevention element existing between a terminal and an internal circuit in the semiconductor device of the present invention. Figure 5 shows (A) in Figure 4.
')-(B') cross-sectional view. Figures 6(a) to 6(
e) is a sectional view showing the order of manufacturing steps for obtaining the structure of the embodiment of the present invention. 21...P-type silicon substrate, 22...
N+ type scattered layer region 23 embedded inside the substrate...
...P-type diffusion layer region that becomes a channel stopper, 2
4...Field oxide film, 25.26...
. . . N+ type scattering layer region 28.29 . . . contact opening, 30.31 . . . aluminum wiring layer. Figure 3 L ++ J Drawing 14 Figure 6 (cl') Figure 6 (b) Figure 6 (C) Figure 6 (d) Figure 6 (e”1
Claims (2)
型の半導体基板内部に埋め込まれて上面および底面が該
半導体基板と接する第2導電型の半導体領域から成る抵
抗部と、前記第1導電型の半導体基板と前記第2導電型
の半導体領域とから形成されるダイオードとを含む静電
破壊防止素子を有することを特徴とする半導体装置。(1) between the terminal and the internal circuit, a resistor section consisting of at least a second conductivity type semiconductor region that is embedded inside the first conductivity type semiconductor substrate and whose top and bottom surfaces are in contact with the semiconductor substrate; A semiconductor device comprising an electrostatic breakdown prevention element including a diode formed from a semiconductor substrate of one conductivity type and a semiconductor region of the second conductivity type.
導電型の半導体領域が該基板と接する領域のうち、少な
くとも、上面部分の該基板側の不純物密度は、底面部分
の該基板側の不純物密度よりも高いことを特徴とする特
許請求の範囲第(1)項記載の半導体装置。(2) A second conductive type embedded inside the semiconductor substrate of the first conductivity type.
Among the regions where the conductive type semiconductor region is in contact with the substrate, at least the impurity density in the upper surface portion on the substrate side is higher than the impurity density in the bottom surface portion on the substrate side. 1) The semiconductor device described in item 1).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21771184A JPS6196757A (en) | 1984-10-17 | 1984-10-17 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21771184A JPS6196757A (en) | 1984-10-17 | 1984-10-17 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6196757A true JPS6196757A (en) | 1986-05-15 |
Family
ID=16708536
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21771184A Pending JPS6196757A (en) | 1984-10-17 | 1984-10-17 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6196757A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63285963A (en) * | 1987-05-02 | 1988-11-22 | テレフンケン・エレクトロニク・ゲゼルシヤフト・ミツト・ベシユレンクテル・ハフツング | Integrated circuit device |
JP2021044434A (en) * | 2019-09-12 | 2021-03-18 | 株式会社東芝 | Semiconductor device |
-
1984
- 1984-10-17 JP JP21771184A patent/JPS6196757A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63285963A (en) * | 1987-05-02 | 1988-11-22 | テレフンケン・エレクトロニク・ゲゼルシヤフト・ミツト・ベシユレンクテル・ハフツング | Integrated circuit device |
JP2021044434A (en) * | 2019-09-12 | 2021-03-18 | 株式会社東芝 | Semiconductor device |
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