JPS6196757A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the static breakdown preventing effect by a method wherein a diffusion layer region, equipped with conductivity opposite in type to the semiconductor substrate and buried as a static breakdown preventing element in said semiconductor substrate, is provided between a terminal and internal circuit and serves as a resistor as well as a diode. CONSTITUTION:The bottoms of N<+> type diffusion layer regions 25, 26 are connected to an N<+> type diffusion layer 22 built within a silicon substrate 21. A terminal and an internal circuit are connected with the intermediary of the diffusion layer regions 25, 26 opposite in the type of conductivity to the substrate 21 and buried therein. In a device designed as such, the effective area increases of the diode consisting of the P type silicon substrate 21 and N<+> type diffusion layer region 22, without an increase of the pattern area between the terminal serving as a static breakdown preventing element and the inner circuit. The backward breakdown of the diode is to take place at the area of contact between a channel stopper 23 that is a P<+> type diffusion layer region and the N<+> type diffusion layer region 22. The current discharging capability may be enhanced because the area of contact is larger than in the conventional technique by the size of the upper surface of the N<+> type diffusion layer region 22.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an electrostatic breakdown prevention element for a semiconductor integrated circuit device.

(Prior Art) One of the general methods for preventing electrostatic damage in semiconductor integrated circuit devices is to insert a resistor in series between the terminal (ponding pad) of the integrated circuit and the internal circuit. It has been practiced to provide a diode.

That is, as shown in Fig. 1, the electrostatic breakdown prevention element has a terminal (
A) and the internal circuit (B), for example, since the N+ type diffusion layer region 14 is formed on the surface of the P type semiconductor substrate 11, the contact opening 16. 17, terminal side (A) and internal circuit side (B)
These are connected to each other by aluminum wiring layers 18 and 19, respectively. Figure 2 shows (A) − indicated by the dashed line in Figure 1.
(B) shows a cross-sectional view between 12 and 12, where 12 is a P+ type diffusion layer region 13 for a channel stopper formed under the field oxide film, and 15 is a field oxide film formed by a well-known selective oxidation method; 15 is between the eyebrows. This is a silicon oxide film grown using a vapor phase growth method for insulation, and the rest corresponds to that shown in FIG. As shown in FIG. 3, the equivalent circuit of the electrostatic breakdown prevention element described above includes a resistor R consisting of an N type diffusion layer region 14, and a diode D consisting of the N type diffusion layer/region 14 and a P type semiconductor substrate 11. It is configured.

Regarding the operation of the electrostatic discharge prevention device, when a negative pulse (→) is applied to the terminal (A), the diode D consisting of the N+ type scattering layer head 14 and the P type semiconductor substrate 11 is forward biased. A current is sucked from the substrate 11. In this case,
The current directivity is determined by the forward resistance of the diode D, the contact resistance, the forward current discharge ability of the diode, etc.

Normally, the contact resistance is made sufficiently small by increasing the contact size, and the diode's forward current discharging ability is usually sufficiently large, so the internal circuit is protected from static damage.

On the other hand, when a positive # electric pulse (+) enters the terminal, the diode consisting of the layer region 14 and the P-type semiconductor substrate 11 is reverse biased by diffusing N+, and when the reverse breakdown of the diode exceeds 4 voltage, the current decreases. The liquid flows into the substrate 11. Generally, in the case of MO8q semiconductor integrated circuit devices, the input to the internal circuit is the gate, and if a voltage higher than the gate dielectric breakdown voltage is input to the internal circuit, the gate will be destroyed, but in this case, the reverse break The down voltage is set to 1 voltage, which is sufficiently lower than the gate dielectric strength voltage, to prevent the gate from being destroyed. However, in this case, the normal N
In the MO8 type semiconductor device, a P-type diffusion layer region 12 with a concentration lower than that of the substrate for the channel stopper is formed under the field oxide film, and the reverse breakdown of the diode is caused by the expansion of the depletion layer. This occurs at the junction between the P+ type diffused layer region 12 and the N+ type diffused layer region 14, which is the smallest in number, and the instantaneous flow that flows at the beginning when an electrostatic pulse is applied is concentrated in this part, and the flow in this part is If the current discharging ability is insufficient, the P''N+ diode itself in this part, which acts as an electrostatic damage prevention element, will be destroyed. Therefore, in the conventional semiconductor device structure, in order to prevent the above-mentioned destruction, the junction part It is necessary to make the area of the N-type diffusion layer region 14 sufficiently large to increase the area of This resulted in an increase in the area of the destruction prevention element region.

(Objective of the Invention) An object of the present invention is to improve the electrostatic breakdown prevention element in the conventional semiconductor device described above, and to improve the electrostatic breakdown prevention element without increasing the pattern area required for the electrostatic breakdown prevention element. It is an object of the present invention to provide a semiconductor device structure that increases the current discharge capability of a diode used as a component, thereby increasing its effectiveness as an electrostatic breakdown prevention element.

(Structure of the Invention) The semiconductor device of the present invention includes at least a semiconductor of a second conductivity type that is embedded inside a semiconductor substrate of a first conductivity type and whose top surface and bottom surface are in contact with the semiconductor substrate, between a terminal and an internal circuit. The device is characterized in that it has an electrostatic breakdown prevention element including a resistor formed of a region, and a diode formed from the semiconductor substrate of the first conductivity type and the semiconductor region of the second conductivity type.

(Example) The present invention will be explained below with reference to the drawings.

FIG. 4 is a plan view showing an electrostatic breakdown prevention element portion in a semiconductor device according to an embodiment of the present invention, in which (A) the terminal side (B') is the internal circuit side. In Figure 4,
21 is a P-type silicon substrate, 22 is an N-type diffusion layer region buried inside the helical substrate, and 25°26 is an N-type diffusion layer having a depth from the substrate surface to contact with the upper surface of the N-type diffusion layer region 22. layer region, 28.29 is a contact opening;
Reference numerals 30 and 31 denote aluminum wiring layers connected to the N+ type scattered layer regions 5 and 26 through the contact openings 28 and 29, and extended toward the internal circuit side and the terminal side, respectively. FIG. 5 shows a cross-sectional view between (A') and (B') indicated by the dashed line in FIG.
2 is a P-type silicon substrate, 22 is a N-type diffusion layer region buried in the substrate, 23 is a channel stopper region formed under a field region and is composed of a P-type diffusion layer;
4 is a field oxide film formed by a selective oxidation method, 2
5.26 is an N type diffusion layer region, the bottom of which is connected to the Nfi diffusion layer 22 buried inside the substrate.

-27 is gas phase.

Silicon oxide film formed by growth method, 28, 29
30 and 31 are contact openings selectively provided in the silicon oxide film 27, and aluminum wiring layers 30 and 31 are connected to internal circuits and terminals, respectively.

What is important in this structure is that the terminals (ponding pads) and internal circuits are connected through a diffusion layer region of the opposite conductivity type to that of the silicon substrate, which is embedded inside the silicon substrate. The effective area of the diode consisting of the P-type silicon substrate 21 and the N-type diffusion layer region 22 is increased without increasing the pattern area between the terminal as an electrostatic breakdown prevention element and the internal circuit. Further, the reverse breakdown of the diode occurs at the contact area between the channel stopper 23 made of the P type diffusion layer region and the Nu diffusion layer region 22, but in the structure of the present invention, the contact area of this portion is also N
Since the upper surface portion of the type diffusion layer region 22 is larger than the conventional one, an increase in current discharge capability can be realized. Therefore, the effect as an electrostatic damage prevention element is increased.

Next, a method for manufacturing the structure according to the present invention will be explained using FIGS. 6(a) to 6(e) including the internal circuit portion.

First, as shown in FIG. 6 (JL), a silicon oxide film 102 is formed on the main surface side of a P-type silicon substrate 101 by a thermal oxidation method, a photoresist 103 is applied, and buttering is performed by a well-known photoetching method. do.

Next, as shown in FIG. 6(b), the photoresist 103
was removed and an organic compound solution containing arsenic was applied to the entire surface.
After baking and hardening at a low temperature of 00℃ and a high temperature of 1100℃, the N+ type scattered layer region 104 is selectively formed using a thermal diffusion method.
After that, the organic compound solution and silicon oxide film are completely removed. Note that the concentration of arsenic in the organic compound solution during this coating is such that the impurity concentration after the formation of the N+ type diffused layer region 104 is the same as that of the N+ type diffused layer formed by connecting to this hind limb N type diffused layer region 104. The impurity concentration is set to be approximately the same as the layer region impurity concentration.

Next, as shown in FIG. 6C, a P-type silicon layer 105 having an impurity concentration comparable to that of the substrate is deposited over the entire surface by epitaxial growth. At this time, the N fM diffusion layer region 104 is also diffused into the epitaxial silicon layer 105 .

Next, as shown in FIG. 6(d), a field oxide film 106 is formed by a selective oxidation method according to the usual manufacturing method for MO8 type semiconductor integrated circuit devices, and a P type diffusion layer region 107 for a channel stopper is formed in the field. Next, a gate oxide film 108 is formed by a thermal oxidation method, a polycrystalline silicon layer is formed by a vapor phase epitaxy method, and a polycrystalline silicon gate electrode 109 is formed by a well-known photoetching method. , After that, the field oxide film 106 and the polycrystalline silicon gate electrode 1^0 are connected to the N type diffusion layer region 104 by performing appropriate heat treatment. N type diffusion layer regions 110, 111, 11 with a depth of
form 2.

Next, as shown in FIG. 6(e), a silicon oxide film 113 is formed on the entire surface by vapor phase growth, and contact openings 114, 115, 116 are formed by a well-known photoetching method.
was formed, and then aluminum wiring /W117°118 was formed. Note that the aluminum wiring layer 117 is connected to the polycrystalline silicon gate electrode 109 which is an internal circuit, and the aluminum wiring layer 1
18 is extended to the terminal (ponding pad) part, and both aluminum wiring layers are connected to the contact opening 115,1.
16 and N+ type scattering layer regions 111104 and 112.

(Summary of the Invention) The MO8 type semiconductor device obtained as described above has a diffusion layer of a conductivity type opposite to that of the substrate embedded in the semiconductor substrate as a destruction prevention element between the terminal and the internal circuit. Since a region exists and acts as a resistor and a diode,
Conventionally, the current discharging capacity of the diode as an electrostatic breakdown prevention element can be increased without increasing the area for the electrostatic breakdown prevention element, and the electrostatic breakdown prevention effect is even greater. be. .

Note that although the above embodiment shows a case in which a P-type semiconductor substrate is used, the present invention is also applicable to an N-type semiconductor substrate. Furthermore, although arsenic was used as an impurity to obtain the N-type diffusion layer region, other impurities may also be used. Furthermore, in the above embodiment, only a diffused layer resistor and a diode were used as the electrostatic damage prevention element, but in order to further increase the electrostatic damage prevention effect, it is possible to add a resistor made of a transistor or a polycrystalline silicon layer. You can also add it.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a pattern of a diffusion layer resistor and a diode as an electrostatic breakdown prevention element provided between a terminal and an internal circuit in a conventional semiconductor device. FIG. 2 is a sectional view of the (A)-(B) portion in FIG. 1. Figure 3 is the first
FIG. 3 is a circuit diagram showing the electrostatic breakdown prevention element shown in the figure. FIG. 4 is a plan view showing a pattern of a diffusion layer resistor and a diode as an electrostatic breakdown prevention element existing between a terminal and an internal circuit in the semiconductor device of the present invention. Figure 5 shows (A) in Figure 4.
')-(B') cross-sectional view. Figures 6(a) to 6(
e) is a sectional view showing the order of manufacturing steps for obtaining the structure of the embodiment of the present invention. 21...P-type silicon substrate, 22...
N+ type scattered layer region 23 embedded inside the substrate...
...P-type diffusion layer region that becomes a channel stopper, 2
4...Field oxide film, 25.26...
. . . N+ type scattering layer region 28.29 . . . contact opening, 30.31 . . . aluminum wiring layer. Figure 3 L ++ J Drawing 14 Figure 6 (cl') Figure 6 (b) Figure 6 (C) Figure 6 (d) Figure 6 (e”1

Claims (2)

[Claims] (1) between the terminal and the internal circuit, a resistor section consisting of at least a second conductivity type semiconductor region that is embedded inside the first conductivity type semiconductor substrate and whose top and bottom surfaces are in contact with the semiconductor substrate; A semiconductor device comprising an electrostatic breakdown prevention element including a diode formed from a semiconductor substrate of one conductivity type and a semiconductor region of the second conductivity type. (2) A second conductive type embedded inside the semiconductor substrate of the first conductivity type.
Among the regions where the conductive type semiconductor region is in contact with the substrate, at least the impurity density in the upper surface portion on the substrate side is higher than the impurity density in the bottom surface portion on the substrate side. 1) The semiconductor device described in item 1).