JPH07114280B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH07114280B2 JPH07114280B2 JP1242224A JP24222489A JPH07114280B2 JP H07114280 B2 JPH07114280 B2 JP H07114280B2 JP 1242224 A JP1242224 A JP 1242224A JP 24222489 A JP24222489 A JP 24222489A JP H07114280 B2 JPH07114280 B2 JP H07114280B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- insulated gate
- film
- source
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 230000002093 peripheral effect Effects 0.000 claims description 14
- 239000012535 impurity Substances 0.000 claims description 13
- 238000009792 diffusion process Methods 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 4
- 239000012212 insulator Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、絶縁ゲートを有する半導体装置に係り、特に
破壊耐量の優れた構造に関する。Description: TECHNICAL FIELD The present invention relates to a semiconductor device having an insulated gate, and more particularly to a structure having excellent breakdown resistance.
従来の装置の一例として、基板11がＰ＋型の不純物をも
つIGBTについて第４図により説明する。ドレイン電極41
をもつＰ＋基板11の上には、ｎ−層12が形成され、ｎ−
層内に幾何的にＰ層13が分離して形成されている。さら
にＰ層13内にはｎ＋層15が特願昭62−208123にも記載の
ように、絶縁ゲート31の両側面下の全てに形成されてい
る。このｎ＋層は絶縁ゲートの側面の不純物を含む部材
24から拡散により自己整合的に形成されたものである。
絶縁ゲート31は、絶縁膜21を介して、間にｎ−層12をも
つように隣りのｎ＋層にまたがつて形成されている。各
ｎ＋層15はＰ層13とソース電極42で電気的に短絡されて
いる。この時、ソース電極42は絶縁膜24で絶縁ゲート31
と絶縁分離されている。周辺領域Ｂの最も領域Ａに近い
部分には、高電圧を阻止するのに必要な厚いＰ＋層14が
形成され、このＰ＋層14とｎ−層12の接合により伸びる
空乏層を止めるために、例えばＰ＋層14′が周辺に形成
されている。以上のように、この装置は絶縁ゲート31を
中心としたユニツトセルが繰り返し成形された領域
と、それ以外の周辺領域に分けられる。IGBTは、Ｐ＋
層11,n−層12、Ｐ層13,n＋層15の４層構造となつている
ため、寄生サイリスタをもち、こが一旦動作し始めると
ゲート31で制御できなくなり、電流が暴走し、破壊する
ラツチアツプを起こす。As an example of a conventional device, an IGBT in which the substrate 11 has a P + type impurity will be described with reference to FIG. Drain electrode 41
N− layer 12 is formed on the P + substrate 11 having
Geometrically separated P layers 13 are formed in the layers. Further, in the P layer 13, an n + layer 15 is formed under both side surfaces of the insulated gate 31 as described in Japanese Patent Application No. 62-208123. This n + layer is a member containing impurities on the side surface of the insulated gate
It is formed from 24 by self-alignment by diffusion.
The insulated gate 31 is formed across the adjacent n + layer so as to have the n− layer 12 between them via the insulating film 21. Each n + layer 15 is electrically short-circuited with the P layer 13 and the source electrode 42. At this time, the source electrode 42 is formed of the insulating film 24, and the insulated gate 31 is formed.
It is insulated and isolated. A thick P + layer 14 necessary for blocking a high voltage is formed in a portion of the peripheral region B closest to the region A, and in order to stop the depletion layer extending due to the junction between the P + layer 14 and the n− layer 12, For example, a P + layer 14 'is formed on the periphery. As described above, this device is divided into a region in which the unit cell centered around the insulated gate 31 is repeatedly formed and a peripheral region other than the region. IGBT is P +
Since it has a four-layer structure consisting of layers 11, n− layer 12, P layer 13, and n + layer 15, it has a parasitic thyristor and once it starts operating, it cannot be controlled by the gate 31 and the current runs away, causing destruction. Raise the ratcheap to be done.
上記従来技術では、第４図に示すように最も周辺領域Ｂ
側にあるｎ−層15下に注入した、ホール電流が集中
し、ラツチアツプ破壊しやすいという問題があつた。In the above-mentioned conventional technique, as shown in FIG.
There was a problem that the hole current, which was injected under the n-layer 15 on the side, was concentrated and was susceptible to ratchet breakdown.
本発明は、ラツチアツプによる破壊を阻止する構造を提
供することを目的とする。It is an object of the present invention to provide a structure that prevents destruction by ratchet.
上記目的を達成するために、絶縁ゲート31の側面に不純
物を含む絶縁膜24を有するIGBTやパワーMOSFETに関し、
周辺領域に近い部分において、不純物拡散のストツパ
ーとなる膜、例えばSiO2を設けることにより、ｎ＋層15
の形成を阻止する領域を設けたものである。To achieve the above object, the present invention relates to an IGBT or power MOSFET having an insulating film 24 containing impurities on the side surface of the insulated gate 31,
By providing a film that serves as a stopper for impurity diffusion, for example, SiO 2 , in the portion near the peripheral region, the n + layer 15
Is provided to prevent the formation of the.
周辺領域に近い領域において、ｎ＋ソース層15を形成
しない部分を設けることにより、ｎ＋ソース層15下のホ
ール＋電流の集中を防止する。By providing a portion where the n + source layer 15 is not formed in a region near the peripheral region, concentration of holes + current under the n + source layer 15 is prevented.
これにより、周辺領域に寄生サイリスタが動作するこ
となく、破壊耐量の大きな装置を実現できる。As a result, it is possible to realize a device having a large breakdown resistance without the parasitic thyristor operating in the peripheral region.
以下、本発明の一実施例を第１図により説明する。第１
図のIGBTまたはパワーMOSFETが第４図の従来構造と異な
る点は、周辺領域に近い部分に不純物の拡散を阻止す
る部材を設けることにある。これにより、上記部材を設
けた部分には、ｎ＋ソース層が形成されず、周辺領域
のｎ−層12に注入されたホールのｎ＋層15下での集中
を防止し、周辺領域に寄生サイリスタがないため、破
壊耐量の大きなIGBTまたはパワーMOSFETを得ることがで
きる。また、本実施例においては、周辺領域のＰ層13に
おいて、周辺側ではｎ＋ソース層が形成されないが、内
側では形成されている。このため、半導体装置に流せる
電流が低下することはない。An embodiment of the present invention will be described below with reference to FIG. First
The IGBT or power MOSFET in the figure is different from the conventional structure in FIG. 4 in that a member for preventing diffusion of impurities is provided in a portion near the peripheral region. As a result, the n + source layer is not formed in the portion where the above member is provided, the concentration of holes injected into the n− layer 12 in the peripheral region under the n + layer 15 is prevented, and a parasitic thyristor is formed in the peripheral region. Therefore, it is possible to obtain an IGBT or power MOSFET having a large breakdown resistance. Further, in the present embodiment, in the P layer 13 in the peripheral region, the n + source layer is not formed on the peripheral side, but is formed on the inner side. Therefore, the current that can flow in the semiconductor device does not decrease.
第２図は、本発明の製造方法の一実施例を示す。（ａ）
ｎ＋層12上にゲート酸化膜21、ゲート電極31、絶縁膜22
を順次形成し、ゲート酸化膜21を残した状態で３層膜を
加工する。その後、ゲート領域をマスクとして、取り除
かれた部分にＰ型不純物、例えばＢ（ボロン）をイオン
注入し、拡散することにより、Ｐ層13を形成する。
（ｂ）部分的にゲート酸化膜21を残すように加工する。
（ｃ）上面全面に絶縁物、例えばPSG膜24を堆積する。
（ｄ）側壁にのみPSG膜24が残るように、ドライエツチ
ングにより加工する。（ｅ）その後、熱処理することに
より、PSG24中のＰ（リン）をＰ層13中に拡散し、ｎ＋
層15を形成する。ここで、PSG膜の下部にゲート酸化膜2
1を有する領域は、ｎ＋層15が形成されない。（ｆ）上
方よりソース電極42を堆積することにより完成する。FIG. 2 shows an embodiment of the manufacturing method of the present invention. (A)
Gate oxide film 21, gate electrode 31, insulating film 22 on the n + layer 12
Are sequentially formed, and the three-layer film is processed with the gate oxide film 21 left. Then, using the gate region as a mask, P-type impurities such as B (boron) are ion-implanted into the removed portion and diffused to form the P layer 13.
(B) Processing is performed so that the gate oxide film 21 is partially left.
(C) Deposit an insulator, such as a PSG film 24, on the entire upper surface.
(D) Processing is performed by dry etching so that the PSG film 24 remains only on the side wall. (E) After that, by heat treatment, P (phosphorus) in PSG24 is diffused in P layer 13, and n +
Form layer 15. Here, the gate oxide film 2 is formed under the PSG film.
The n + layer 15 is not formed in the region having 1. (F) Completed by depositing the source electrode 42 from above.
第３図は、表面に本発明の半導体装置を形成した変形例
を示す。絶縁ゲートの側面に絶縁膜25（例えばSiO2,Si
N）を設け、さらにその上に一方導電型の不純物を含む
部材26を成形する。部材26は、絶縁物であるPSGでも良
く、また、導電性のポリシリコンでも良い。この部材26
は、絶縁物25で確実に絶縁されている。また、導電性の
部材26を用いると、ｎ＋ソース層15の引出し電極とし
て、部材26を用いることができ、ｎ＋ソース層15とソー
ス電極42の接触面積を広くとれ、接触抵抗を下げること
ができる。FIG. 3 shows a modification in which the semiconductor device of the present invention is formed on the surface. Insulating film 25 (eg SiO 2 , Si
N) is provided, and a member 26 containing impurities of one conductivity type is further formed thereon. The member 26 may be PSG, which is an insulator, or conductive polysilicon. This member 26
Is securely insulated by an insulator 25. When the conductive member 26 is used, the member 26 can be used as the extraction electrode of the n + source layer 15, the contact area between the n + source layer 15 and the source electrode 42 can be widened, and the contact resistance can be reduced. .
本発明によれば、IGBTやパワーMOSFETの周辺領域近傍に
おけるホール電流の集中による寄生サイリスタ効果を防
止でき、電流容量を損ねることなく破壊耐量の大きな素
子が可能となる。According to the present invention, it is possible to prevent the parasitic thyristor effect due to the concentration of the hole current in the vicinity of the peripheral region of the IGBT or power MOSFET, and it is possible to realize an element having a large breakdown resistance without impairing the current capacity.
第１図は本発明の一実施例の断面図、第２図（ａ）から
（ｆ）は本発明の製造方法の説明図、第３図は本発明の
変形例を示す図、第４図は従来例の断面図である。 １…半導体装置、11…半導体基板、12…ｎ−層、41…ド
レイン電極、42…ソース電極、31…ゲート電極、24…PS
G膜。FIG. 1 is a sectional view of an embodiment of the present invention, FIGS. 2 (a) to (f) are explanatory views of the manufacturing method of the present invention, FIG. 3 is a view showing a modified example of the present invention, and FIG. [FIG. 6] is a cross-sectional view of a conventional example. DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 11 ... Semiconductor substrate, 12 ... N-layer, 41 ... Drain electrode, 42 ... Source electrode, 31 ... Gate electrode, 24 ... PS
G membrane.
Claims (1)
絶縁ゲートと、 絶縁ゲートの側面間において半導体層内に設けられ、他
方導電型で半導体層より高不純物濃度を有する複数のウ
ェル層と、 絶縁ゲートの側面に設けられる一方導電型の不純物を含
む膜と、 ウェル層内に設けられ、前記膜から拡散される不純物を
含む、一方導電型でウェル層より高不純物濃度のソース
層と、 上記側面間においてウェル層及びソース層に接触するソ
ース電極と、 を有し、 半導体層の周辺領域に設けられる１ウェル層において、 周辺側に位置する絶縁ゲートの側面に設けられる前記膜
とウェル層表面とは、該膜からの不純物の拡散を阻止す
る部材により隔離されるとともに、 内側に位置する絶縁ゲートの側面に隣接するウェル層内
には、該側面に設けられる前記膜から拡散される不純物
を含む前記ソース層が設けられ、 かつ、前記周辺側に位置する絶縁ゲートの側面と前記内
側に位置する絶縁ゲートの側面との間においては、前記
ソース電極が設けられることを特徴とする半導体装置。1. An insulated gate provided on the surface of a semiconductor layer of one conductivity type, and a plurality of well layers provided in the semiconductor layer between side surfaces of the insulated gate and having a higher impurity concentration than the semiconductor layer of the other conductivity type. A film containing impurities of one conductivity type provided on the side surface of the insulated gate; and a source layer provided in the well layer and containing impurities diffused from the film, and a source layer of one conductivity type having a higher impurity concentration than the well layer, A well layer and a source electrode in contact with the source layer between the side surfaces, and a well layer provided on a side surface of an insulated gate located on a peripheral side in a well layer provided in a peripheral region of a semiconductor layer. The surface is isolated by a member that prevents diffusion of impurities from the film, and is provided on the side surface in the well layer adjacent to the side surface of the insulating gate located inside. Is provided with the source layer containing impurities diffused from the film, and the source electrode is provided between the side surface of the insulated gate located on the peripheral side and the side surface of the insulated gate located on the inner side. A semiconductor device characterized by being provided.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1242224A JPH07114280B2 (en) | 1989-09-20 | 1989-09-20 | Semiconductor device |
| KR1019900008598A KR0173778B1 (en) | 1989-06-12 | 1990-06-12 | Semiconductor device and method of manufacturing the same |
| US07/762,793 US5208471A (en) | 1989-06-12 | 1991-09-19 | Semiconductor device and manufacturing method therefor |
| US08/017,420 US5262339A (en) | 1989-06-12 | 1993-02-10 | Method of manufacturing a power semiconductor device using implants and solid diffusion source |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1242224A JPH07114280B2 (en) | 1989-09-20 | 1989-09-20 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03105980A JPH03105980A (en) | 1991-05-02 |
| JPH07114280B2 true JPH07114280B2 (en) | 1995-12-06 |
Family
ID=17086080
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1242224A Expired - Lifetime JPH07114280B2 (en) | 1989-06-12 | 1989-09-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07114280B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08139319A (en) * | 1994-11-11 | 1996-05-31 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5987828A (en) * | 1982-11-12 | 1984-05-21 | Hitachi Ltd | Semiconductor device |
| JPS62235785A (en) * | 1986-04-07 | 1987-10-15 | Nec Corp | Veritical field-effect transistor |
| JPH0766966B2 (en) * | 1987-04-06 | 1995-07-19 | 株式会社日立製作所 | Semiconductor device |
| JPS6464258A (en) * | 1987-09-03 | 1989-03-10 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1989
- 1989-09-20 JP JP1242224A patent/JPH07114280B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03105980A (en) | 1991-05-02 |
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