JPS61251083A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61251083A JPS61251083A JP9167585A JP9167585A JPS61251083A JP S61251083 A JPS61251083 A JP S61251083A JP 9167585 A JP9167585 A JP 9167585A JP 9167585 A JP9167585 A JP 9167585A JP S61251083 A JPS61251083 A JP S61251083A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- guard ring
- impurity layer
- type
- diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 239000012535 impurity Substances 0.000 claims abstract description 34
- 238000009792 diffusion process Methods 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 abstract description 8
- 230000010354 integration Effects 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 238000007796 conventional method Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8611—Planar PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
主ｌ上皇料里分！
この発明は、プレーナ形高耐圧のダイオードおよびトラ
ンジスタ等の半導体装置に係り、特に高集積化或いはチ
ップ面積の縮小化を図る場合に有利な半導体装置に関す
る。[Detailed Description of the Invention] Lord Retirement Emperor Ryobun! The present invention relates to semiconductor devices such as planar high-voltage diodes and transistors, and particularly to semiconductor devices that are advantageous for achieving high integration or reducing chip area.
従来夏狡丑
従来、ブレーナ形のダイオードおよびトランジスタ等の
半導体装置を高耐圧とするために、その不純物層の回り
を前記不純物層と同一導電型のガードリング層で取り囲
んだものが特公昭４０−１２７３９号に見られる。これ
によれば、前記ガードリング層と前記不純物層との拡散
深さが同一になされている。Traditionally, in order to make semiconductor devices such as Brenna-type diodes and transistors have a high breakdown voltage, an impurity layer was surrounded by a guard ring layer of the same conductivity type as the impurity layer. Seen in No. 12739. According to this, the diffusion depths of the guard ring layer and the impurity layer are made the same.
（シよ゛と る− 占
一般に、不純物を拡散するときには、その拡散深さと比
例して横方向への拡がりを伴うという特性がある。つま
り、ガードリング層と不純物層との拡散深さを同一にし
た従来の方式では、ガードリング層の表面面積の増大を
余儀なくされるという欠点がある。このことに基づき、
チップサイズの縮小化或いは集積回路の高集積化を図る
には非常に不利となる。(Based on this) In general, when impurities are diffused, there is a characteristic that they spread in the lateral direction in proportion to the diffusion depth.In other words, if the diffusion depths of the guard ring layer and the impurity layer are the same, The conventional method in which the guard ring layer is formed has the disadvantage that the surface area of the guard ring layer has to be increased.Based on this,
This is extremely disadvantageous in reducing the chip size or increasing the degree of integration of integrated circuits.
この発明は上記事情に鑑みて創案されたもので、ガード
リング層の表面面積を比較的小さくし、チップサイズの
縮小化或いは集積回路の高集積化等において有利にせし
める半導体装置を提供することを目的としている。This invention was devised in view of the above circumstances, and aims to provide a semiconductor device in which the surface area of the guard ring layer is made relatively small, which is advantageous in reducing chip size or increasing the degree of integration of integrated circuits. The purpose is
・占 ”の
このためこの発明は、不純物層の廻りを、前記不純物層
と同一導電型で且つ前記不純物層の拡散深さよりも浅い
ガードリング層で取り囲んだ。Therefore, in this invention, the impurity layer is surrounded by a guard ring layer having the same conductivity type as the impurity layer and having a shallower diffusion depth than the impurity layer.
皿
即ち、不純物層とガードリング層とを別々に拡散形成す
ることで、前記不純物層の拡散深さよりも前記ガードリ
ング層の拡散深さを浅くした。In other words, by separately forming the impurity layer and the guard ring layer by diffusion, the diffusion depth of the guard ring layer is made shallower than that of the impurity layer.
１蓋！
以下、図面を参照してこの発明の一実施例を詳細に説明
する０本実施例では第１図に示すプレーナ形高耐圧ダイ
オード１を例として説明する。1 lid! DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.In this embodiment, a planar type high voltage diode 1 shown in FIG. 1 will be explained as an example.
即ち、プレーナ形高耐圧ダイオード１は、Ｎ型のシリコ
ンからなる半導体基板１０の表面を覆うシリコン酸化膜
からなる絶縁＠２０と、前記半導体基板１０の所定位置
に拡散形成されたＰ型の不純物層４０と、この不純物層
４０の廻りを取り囲むＰ型のガードリングＪｉｔ５０と
、Ｐ型電極６０と、Ｎ型電極７０とを具備している。但
し、前記ガードリング層５０は、不純物ｒＥｉ！４０の
拡散深さよりも浅く拡散形成されている。なお、図中破
線で示す部分は空乏層を示している。That is, the planar type high voltage diode 1 includes an insulation@20 made of a silicon oxide film covering the surface of a semiconductor substrate 10 made of N-type silicon, and a P-type impurity layer diffused and formed in a predetermined position of the semiconductor substrate 10. 40, a P-type guard ring Jit50 surrounding the impurity layer 40, a P-type electrode 60, and an N-type electrode 70. However, the guard ring layer 50 contains impurities rEi! The diffusion depth is shallower than the diffusion depth of 40. Note that the portion indicated by a broken line in the figure indicates a depletion layer.
しかして、上記プレーナ形高耐圧ダイオード１の製造方
法の一例を第２図に従って以下説明する。An example of a method for manufacturing the planar high voltage diode 1 will be described below with reference to FIG.
■ 半導体基板１０の表面に絶縁膜２０を成長させ、こ
の絶縁膜２０の表面にホトレジスト３０を塗布し、不純
物層を形成すべき部分に相当する前記ホトレジスト３０
を除去する。このホトレジスト３０をマスクとしてＰ型
の不純物をイオン打込みする（第２図（ａ）参照）。(2) An insulating film 20 is grown on the surface of the semiconductor substrate 10, a photoresist 30 is applied to the surface of the insulating film 20, and the photoresist 30 is applied to the portion where the impurity layer is to be formed.
remove. Using this photoresist 30 as a mask, P-type impurity ions are implanted (see FIG. 2(a)).
■ 前記ホトレジスト３０を剥離した後、前記イオン打
込みされた半導体基板１０を熱処理することにより、前
記不純物を拡散させて不純物層４０を形成する（第２図
山）参照）。(2) After peeling off the photoresist 30, the ion-implanted semiconductor substrate 10 is heat-treated to diffuse the impurities and form an impurity layer 40 (see the top of FIG. 2).
■ 前記絶縁膜２０の表面に再度ホトレジスト３１を塗
布し、ガードリング層を形成すべき部分に相当する前記
ホトレジスト３１を除去する。このホトレジスト３１を
マスクとしてＰ型の不純物をイオン打込みする（第２図
（Ｃ）参照）。(2) A photoresist 31 is applied again to the surface of the insulating film 20, and the photoresist 31 corresponding to the portion where the guard ring layer is to be formed is removed. P-type impurity ions are implanted using this photoresist 31 as a mask (see FIG. 2(C)).
■ 前記ホトレジスト３１を剥離した後、前記イオン打
込みされた半導体基板１０を適宜に熱処理する′ことに
より、前記不純物を前記不純物層４０よりも浅く拡散さ
せてガードリング層５０を形成する（第２図（ｄ）参照
）。なお、前記ガードリング層５０の拡散時における横
方向の拡がりは拡散深さに比例することに基づき、その
表面面積が比較的小さくなりている。(2) After peeling off the photoresist 31, the ion-implanted semiconductor substrate 10 is appropriately heat-treated to diffuse the impurity to a depth shallower than the impurity layer 40 and form a guard ring layer 50 (see FIG. 2). (see (d)). Note that the surface area of the guard ring layer 50 is relatively small because the lateral expansion of the guard ring layer 50 during diffusion is proportional to the diffusion depth.
上記工程において、不純物層４０、ガードリング層５０
は、固相拡散、液相拡散および気相拡散等でもって拡散
形成されるも可能である。In the above steps, the impurity layer 40, the guard ring layer 50
can also be formed by diffusion by solid phase diffusion, liquid phase diffusion, gas phase diffusion, etc.
なお、上記実施例において、前記不純物層４０の拡散深
さを１０μｍ程度に、ガードリング１ｉ５０の拡散深さ
を３〜５μｍ程度にそれぞれ設定した場合、耐圧が低下
しないことが確認された。In the above example, it was confirmed that when the diffusion depth of the impurity layer 40 was set to about 10 μm and the diffusion depth of the guard ring 1i50 was set to about 3 to 5 μm, the withstand voltage did not decrease.
また、この発明は上記実施例に限定されることはなく、
例えばパワートランジスタ等に適用できることは勿論で
ある。Furthermore, the present invention is not limited to the above embodiments,
Of course, it can be applied to power transistors, etc., for example.
発皿五処果
以上詳説したようにこの発明によれば、空乏層を広げる
という目的に支障を来すことなく、前記ガードリング層
の横方向の拡がりを抑えることができる。即ち、ガード
リング層の表面面積を従来と比較して小さくすることが
できるから、チップサイズの縮小化或いは集積回路の高
集積化を図る場合に有利となる。特に、前記ガードリン
グ層を不純物層の外周に多重に配設させるような場合や
、不純物層の拡散深さが深いような構造の半導体装置（
パワー素子等）の場合において、この発明による効果が
顕著にあられれる。As described in detail above, according to the present invention, it is possible to suppress the lateral expansion of the guard ring layer without impeding the purpose of expanding the depletion layer. That is, the surface area of the guard ring layer can be made smaller than that of the conventional method, which is advantageous in reducing the chip size or increasing the degree of integration of the integrated circuit. In particular, in cases where the guard ring layers are arranged in multiple layers around the outer periphery of the impurity layer, or in a semiconductor device with a structure in which the impurity layer has a deep diffusion depth (
(power devices, etc.), the effects of the present invention are noticeable.
第１図はこの発明に係る半導体装置の一実施例を示す断
面説明図、第２図は第１図のブレーナ形高耐圧ダイオー
ドの製造方法を示す断面説明図である。
１・・・プレーナ形高耐圧ダイオード、１０・・・半導
体基板、２０・・・絶縁膜、４０・・・不純物層、５０
・・・ガードリング層。FIG. 1 is an explanatory cross-sectional view showing an embodiment of a semiconductor device according to the present invention, and FIG. 2 is an explanatory cross-sectional view showing a method for manufacturing the Brehner type high voltage diode shown in FIG. DESCRIPTION OF SYMBOLS 1... Planar type high voltage diode, 10... Semiconductor substrate, 20... Insulating film, 40... Impurity layer, 50
...Guard ring layer.
Claims (1)
一導電型のガードリング層で取り囲んだ半導体装置にお
いて、前記ガードリング層は、前記不純物層の拡散深さ
よりも浅く拡散形成されていることを特徴とする半導体
装置。(1) In a semiconductor device in which an impurity layer of one conductivity type is surrounded by a guard ring layer of the same conductivity type as the impurity layer, the guard ring layer is formed by diffusion to a depth shallower than the diffusion depth of the impurity layer. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9167585A JPS61251083A (en) | 1985-04-26 | 1985-04-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9167585A JPS61251083A (en) | 1985-04-26 | 1985-04-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61251083A true JPS61251083A (en) | 1986-11-08 |
Family
ID=14033062
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9167585A Pending JPS61251083A (en) | 1985-04-26 | 1985-04-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61251083A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006156936A (en) * | 2004-10-25 | 2006-06-15 | Matsushita Electric Ind Co Ltd | Voltage regulating diode and its manufacturing method |
| JP2006332127A (en) * | 2005-05-23 | 2006-12-07 | Toshiba Corp | Semiconductor device for power |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5552257A (en) * | 1978-10-10 | 1980-04-16 | Bbc Brown Boveri & Cie | Power semiconductor element having band guardring |
| JPS5660055A (en) * | 1979-10-20 | 1981-05-23 | Nec Home Electronics Ltd | Manufacture of semiconductor device |
-
1985
- 1985-04-26 JP JP9167585A patent/JPS61251083A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5552257A (en) * | 1978-10-10 | 1980-04-16 | Bbc Brown Boveri & Cie | Power semiconductor element having band guardring |
| JPS5660055A (en) * | 1979-10-20 | 1981-05-23 | Nec Home Electronics Ltd | Manufacture of semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006156936A (en) * | 2004-10-25 | 2006-06-15 | Matsushita Electric Ind Co Ltd | Voltage regulating diode and its manufacturing method |
| JP2006332127A (en) * | 2005-05-23 | 2006-12-07 | Toshiba Corp | Semiconductor device for power |
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