JPS6292452A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6292452A JPS6292452A JP23137185A JP23137185A JPS6292452A JP S6292452 A JPS6292452 A JP S6292452A JP 23137185 A JP23137185 A JP 23137185A JP 23137185 A JP23137185 A JP 23137185A JP S6292452 A JPS6292452 A JP S6292452A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- oxide film
- thick oxide
- substrate
- amorphous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 24
- 150000001793 charged compounds Chemical class 0.000 claims abstract description 8
- 230000003647 oxidation Effects 0.000 claims description 19
- 238000007254 oxidation reaction Methods 0.000 claims description 19
- 238000002955 isolation Methods 0.000 claims description 17
- 238000005468 ion implantation Methods 0.000 claims description 7
- 239000012535 impurity Substances 0.000 abstract description 10
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 6
- 230000001590 oxidative effect Effects 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 abstract description 4
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 4
- 239000012212 insulator Substances 0.000 abstract 2
- 238000009413 insulation Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 3
- -1 BF2' Chemical class 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 2
- 238000005280 amorphization Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に素子間を絶
縁分離するための厚い酸化膜からなる絶縁分離領域を有
する半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having an insulating isolation region made of a thick oxide film for insulating and isolating elements.
一般に、バイポーラトランジスタを素子とする半導体集
積回路袋!では、各素子間を絶縁分離するためにPN接
合を用いている。しかし、このPN接合では、接合を形
成するためにP型不純物をN型エピタキシャル層の表面
からP型基板にまで拡散させる必要があり、高温長時間
の熱処理を必要とする。このため、この熱処理によって
基板中に既に形成した高濃度不純物層からなる埋込み層
からエピタキシャル層への不純物の拡散が生じ1、エピ
タキシャル層が薄い半導体集積回路装置では耐圧の低下
を招くという問題がある。また、P型不純物の等方拡散
によって平面方向の拡散も進み、分離領域の専有面積が
大きくなって半導体集積回路装置の集積度の低下を招く
ことにもなる。In general, semiconductor integrated circuit bags that use bipolar transistors as elements! In this case, a PN junction is used to insulate and separate each element. However, in this PN junction, it is necessary to diffuse the P-type impurity from the surface of the N-type epitaxial layer to the P-type substrate in order to form the junction, which requires heat treatment at high temperature and for a long time. For this reason, this heat treatment causes diffusion of impurities from the buried layer, which is a high-concentration impurity layer already formed in the substrate, into the epitaxial layer (1), which causes a problem of a decrease in breakdown voltage in semiconductor integrated circuit devices with thin epitaxial layers. . Further, due to the isotropic diffusion of the P-type impurity, the diffusion in the planar direction also progresses, and the exclusive area of the isolation region increases, resulting in a decrease in the degree of integration of the semiconductor integrated circuit device.
このため、近年の半導体集積回路装置では、半導体基板
の表面を選択的に厚く酸化する方法、いわゆるLOCO
3法によって形成した厚い酸化膜によって絶縁分離領域
を構成する傾向にある。For this reason, recent semiconductor integrated circuit devices use a method of selectively and thickly oxidizing the surface of a semiconductor substrate, the so-called LOCO.
There is a tendency for the insulation isolation region to be formed by a thick oxide film formed by the three methods.
上述した従来のLOCO3法による厚い酸化膜の形成方
法は、半導体基板の表面を選択的にマスクした上で、露
呈されている半導体基板表面を酸化する方法であるため
、形成される厚い酸化膜は半導体基板、例えばエピタキ
シャル層の内部に向かって酸化が進行されるとともに、
これと同時に上方に向かっても酸化が進行される。通常
では上方と下方との厚さ割合は6:4となる。このため
、厚い酸化膜の部分が半導体基板表面よりも大幅に突出
して半導体基板の表面の平坦化が損なわれ、特に微細な
パターンで半導体基板上に形成する高集積度の半導体集
積回路装置の各種電極や配線の断線を生じる等、その信
幀性を低下させるおそれがある。また、この厚い酸化膜
の絶縁分離領域では、酸化膜の縁部に生じるバーズビー
クによって領域の平面専有面積が増大し、その微細化が
損なわれるという問題もある。The method for forming a thick oxide film using the conventional LOCO3 method described above is a method in which the surface of the semiconductor substrate is selectively masked and then the exposed surface of the semiconductor substrate is oxidized. As oxidation progresses toward the inside of the semiconductor substrate, for example, an epitaxial layer,
At the same time, oxidation progresses upward as well. Normally, the thickness ratio between the upper part and the lower part is 6:4. As a result, parts of the thick oxide film protrude significantly beyond the surface of the semiconductor substrate, impairing the flatness of the surface of the semiconductor substrate, which is particularly important for various types of highly integrated semiconductor integrated circuit devices that are formed on semiconductor substrates in fine patterns. There is a risk that reliability may be reduced due to disconnection of electrodes or wiring. Further, in the insulation isolation region of this thick oxide film, there is also a problem that the bird's beak generated at the edge of the oxide film increases the area occupied in the plane of the region, impairing its miniaturization.
本発明の製造方法は、半導体基板の表面の平坦化を保っ
た状態で、しかも専有面積を増大することのない厚い酸
化膜からなる絶縁分離領域を形成するものであり、半導
体基板の表面を凹設した一Lで、この四部面を非晶質化
し、かつ選択酸化を行ってこの四部箇所に厚い酸化膜を
形成する工程を含む製造方法である。また、この非晶質
化には分子状イオン注入法を用いている。The manufacturing method of the present invention forms an insulating isolation region made of a thick oxide film without increasing the occupied area while maintaining the flattening of the surface of the semiconductor substrate. This manufacturing method includes the steps of making the four surfaces amorphous and selectively oxidizing them to form a thick oxide film at the four locations. Furthermore, a molecular ion implantation method is used for this amorphization.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明方法により製造した半導体装置の断面図
であり、この実施例ではP型シリコン基板1にN型エピ
タキシャル層2を形成し、ここにチャネルストッパとし
てのP型不純物層9を形成し、その上に厚い絶縁膜から
なる絶縁分離領域8を形成している。この絶縁膜A11
I領域8はシリコン基板1の表面側よりも内側に向かっ
て酸化が進行されており、これによりシリコン基板1の
表面の平坦化が図られている。FIG. 1 is a cross-sectional view of a semiconductor device manufactured by the method of the present invention. In this example, an N-type epitaxial layer 2 is formed on a P-type silicon substrate 1, and a P-type impurity layer 9 as a channel stopper is formed here. Then, an insulating isolation region 8 made of a thick insulating film is formed thereon. This insulating film A11
In I region 8, oxidation progresses inward from the surface side of silicon substrate 1, thereby flattening the surface of silicon substrate 1.
第2図(a)〜(d)は本発明の製造方法を工程順に説
明するための断面図であり、特に絶縁膜HfiJW域の
部分のみを図示したものである。FIGS. 2(a) to 2(d) are cross-sectional views for explaining the manufacturing method of the present invention step by step, and in particular only the insulating film HfiJW region is shown.
先ず、同図<a>のようにP型シリコン基板l上に、例
えば形成する素子のコレクタ領域としてのN型エピタキ
シャル層2を形成し、その上に熱酸化法によりシリコン
酸化膜3を形成する。また、この上にLPCVD法によ
ってシリコン窒化膜4を形成する。そして、公知のフォ
トエツチング技術により所望の領域のこれらシリコン酸
化膜3とシリコン窒化膜4をエツチング除去する。First, as shown in the figure <a>, an N-type epitaxial layer 2 is formed on a P-type silicon substrate l, for example, as a collector region of an element to be formed, and a silicon oxide film 3 is formed thereon by a thermal oxidation method. . Furthermore, a silicon nitride film 4 is formed thereon by the LPCVD method. Then, the silicon oxide film 3 and silicon nitride film 4 in desired areas are etched away using a known photo-etching technique.
次いで、同図(b)のように前記シリコン窒化膜4をマ
スクとしてエピタキシャル層2表面を酸化させ、厚い酸
化膜5を形成する。Next, as shown in FIG. 4B, the surface of the epitaxial layer 2 is oxidized using the silicon nitride film 4 as a mask to form a thick oxide film 5.
そして、同図(C)のように、この厚い酸化膜5のみを
エツチング除去し、露呈されたエピタキシャル層2の表
面に非晶質化した層6を形成する。Then, as shown in FIG. 2C, only this thick oxide film 5 is removed by etching, and an amorphous layer 6 is formed on the exposed surface of the epitaxial layer 2.
この非晶質化には、イオン注入時の飛程が前記シリコン
窒化膜4の厚さを越えない範囲のエネルギで分子状イオ
ン、例えばBF2’を高濃度にイオン注入する方法が用
いられる。ここで、分子状イオン注入法とは、通常のイ
オン注入装置のイオンソースとしてIIFa等のガスを
用いてプラズマを発生させた場合、l1lB+ 、 l
IB+ 、 19B+等の単体イオンと、BF” 、B
F2” 、BF”+等の分子状イオンが生じるが、この
分子状イオンのみを選択的に注入する方法である。更に
、イオン注入法により低濃度P型不純物層7を前記非晶
質化層6の直下及び側壁領域に形成する。For this amorphization, a method is used in which molecular ions, such as BF2', are implanted at a high concentration with an energy range that does not exceed the thickness of the silicon nitride film 4 during ion implantation. Here, the molecular ion implantation method means that when plasma is generated using a gas such as IIFa as the ion source of a normal ion implantation device, l1lB+, l
Single ions such as IB+, 19B+, BF'', B
Molecular ions such as F2'' and BF''+ are generated, and this is a method in which only these molecular ions are selectively implanted. Furthermore, a low concentration P-type impurity layer 7 is formed directly under the amorphous layer 6 and in the sidewall region by ion implantation.
しかる上で、同図(d)のように、選択酸化法によって
エピタキシャル層2表面を酸化することにより、前記非
晶質化層6は酸化速度が他の部分よりも高められるため
、酸化によって形成される厚い酸化膜8はエピタキシャ
ル層2の上側方向らりも下側方向に向かって高い速度で
酸化が進行される。これにより、上面では平lFtでか
つ下方に向かって酸化された絶縁膜11111領域8が
完成される。In addition, as shown in FIG. 2(d), by oxidizing the surface of the epitaxial layer 2 by selective oxidation, the oxidation rate of the amorphous layer 6 is higher than that of other parts, so that it is difficult to form the amorphous layer 6 by oxidation. The thick oxide film 8 is oxidized at a high rate both upwardly and downwardly of the epitaxial layer 2. As a result, an insulating film 11111 region 8 is completed which is flat lFt on the upper surface and oxidized downward.
なお、この選択酸化時におい“(前記絶縁分離領域8の
下側には、前記低濃度P型不純物層7が拡nシされたチ
ャネルストッパとしての不純物層9が形成される。During this selective oxidation, an impurity layer 9 serving as a channel stopper is formed below the insulating isolation region 8 by expanding the low concentration P-type impurity layer 7.
以下、通常の工程に従って所定の素子、例えばバイポー
ラトランジスタが形成され、半導体集積回路等の半導体
装置が完成されることになる。Thereafter, a predetermined element, for example a bipolar transistor, is formed according to normal steps, and a semiconductor device such as a semiconductor integrated circuit is completed.
したがって、この製造方法によれば、絶縁分離領域とし
ての厚い酸化膜の形成に際し、基板1の所望箇所を凹設
した上でその四部面に分子状イオンを注入して核部に非
晶質化層6を形成しているので、その後の選択酸化にお
いては基板1の内方への酸化速度を上方への酸化速度よ
りも格段に大きいものにでき、これにより基板1の表面
に凹凸を生じることなく必要な深さの厚い酸化膜8を形
成することができる。また、この製造方法は、従来の選
択酸化法による絶縁分離領域の形成工程に、酸化膜のエ
ソチング工程8分子状イオン注入工程。Therefore, according to this manufacturing method, when forming a thick oxide film as an insulating isolation region, a desired part of the substrate 1 is recessed, and molecular ions are implanted into the four surfaces of the recess to make the core part amorphous. Since the layer 6 is formed, the inward oxidation rate of the substrate 1 can be made much higher than the upward oxidation rate in the subsequent selective oxidation, which prevents unevenness from occurring on the surface of the substrate 1. The thick oxide film 8 can be formed to the required depth without any problems. In addition, this manufacturing method includes an oxide film etching step and an 8-molecular ion implantation step in addition to the step of forming an insulating isolation region using the conventional selective oxidation method.
再度の選択酸化工程を付加するのみでよく、しかも特別
な成膜工程を必要としないので絶縁分離領域の形成を容
易に行うことができる。Since it is only necessary to add another selective oxidation step and no special film formation step is required, the insulation isolation region can be easily formed.
また、この方法では、絶縁分離領域8の選択酸化時に表
面側における酸化の進行が相対的に抑制されるので、い
わゆるバーズビークの進行も抑制され、絶縁分離領域の
平面専有面積を低減して、その微細化を図り、半導体装
置の集積度の向上にも有効となる。In addition, in this method, the progress of oxidation on the surface side is relatively suppressed during selective oxidation of the insulation isolation region 8, so the progress of so-called bird's beak is also suppressed, and the planar area occupied by the insulation isolation region is reduced. It is also effective in achieving miniaturization and improving the degree of integration of semiconductor devices.
以上説明したように本発明の製造方法は、半導体基板の
表面を凹設した上で、この四部面を非晶質化し、かつ選
)J<酸化を行ってこの凹部箇所に厚い酸化膜を形成す
る工程を含んでいるので、この厚い酸化膜の酸化速度を
半導体基板の上方よりも内方に向かう側で大きくでき、
これにより所望の厚さの絶縁分離領域を半導体基板の表
面を略平坦に保った状態で製造できる。また、絶縁分離
領域の平面専有面積を低減してその微細化を図り、半導
体装置の集積度の向上を図ることもできる。As explained above, the manufacturing method of the present invention involves forming a recess on the surface of a semiconductor substrate, making the four surfaces amorphous, and performing oxidation to form a thick oxide film in the recess. Since the oxidation rate of this thick oxide film can be increased inwardly than above the semiconductor substrate,
Thereby, an insulating isolation region having a desired thickness can be manufactured while keeping the surface of the semiconductor substrate substantially flat. Furthermore, it is possible to reduce the planar area occupied by the insulating isolation region to achieve miniaturization, thereby improving the degree of integration of the semiconductor device.
第1図は本発明方法により製造した半導体装置の一部の
断面図、第2図(a)〜(d)は本発明方法を工程順に
説明するための断面図である。
1・・・シリコン基板、2・・・エピタキシャル層、3
・・・シリコン酸化膜、4・・・シリコン窒化膜、5・
・・厚い酸化膜、6・・・非晶質化層、7・・・低濃度
P型不純物層、8・・・厚い酸化膜(絶縁分離領域)、
9・・・チャネルストッパ。
第2図(a)
第2図(b)′
51、・暖うし隈FIG. 1 is a cross-sectional view of a part of a semiconductor device manufactured by the method of the present invention, and FIGS. 2(a) to 2(d) are cross-sectional views for explaining the method of the present invention in the order of steps. 1... Silicon substrate, 2... Epitaxial layer, 3
... silicon oxide film, 4... silicon nitride film, 5.
... Thick oxide film, 6... Amorphous layer, 7... Low concentration P-type impurity layer, 8... Thick oxide film (insulating isolation region),
9...Channel stopper. Figure 2 (a) Figure 2 (b)' 51, ・Tanushikuma
Claims (1)
し、これを素子間の絶縁分離領域として構成するように
した半導体装置の製造方法において、前記絶縁分離領域
を形成すべき箇所の半導体基板の表面を所要の深さに凹
設する工程と、この凹設した面を非晶質化して非晶質化
層を形成する工程と、選択酸化を行ってこの凹設箇所に
厚い酸化膜を形成する工程とを含むことを特徴とする半
導体装置の製造方法。 2、非晶質化層の形成に分子状イオン注入法を用いてな
る特許請求の範囲第1項記載の半導体装置の製造方法。[Claims] 1. A method for manufacturing a semiconductor device in which a thick insulating film is formed on a semiconductor substrate by a selective oxidation method, and this is configured as an insulating isolation region between elements, in which the insulating isolation region is formed. A process of recessing the surface of the semiconductor substrate at the desired location to the required depth, a process of amorphizing the recessed surface to form an amorphous layer, and performing selective oxidation to recess the recessed area. 1. A method of manufacturing a semiconductor device, comprising: forming a thick oxide film. 2. A method of manufacturing a semiconductor device according to claim 1, wherein a molecular ion implantation method is used to form the amorphous layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23137185A JPS6292452A (en) | 1985-10-18 | 1985-10-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23137185A JPS6292452A (en) | 1985-10-18 | 1985-10-18 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6292452A true JPS6292452A (en) | 1987-04-27 |
Family
ID=16922569
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23137185A Pending JPS6292452A (en) | 1985-10-18 | 1985-10-18 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6292452A (en) |
-
1985
- 1985-10-18 JP JP23137185A patent/JPS6292452A/en active Pending
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