JPH11283989A - Bipolar transistor and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the size of cells and manufacture a transistor rapidly and easily by allowing a collector region, to include a collector diffused region formed by diffusing impurities from channels formed in an upper face of an epitaxial layer. SOLUTION: In this bipolar transistor 10, a low resistance embedded layer 14 and an epitaxial layer 16 are formed on a semiconductor substrate 12. In the epixial layer 16, an insulating and separating wall 18 and channel 20 for element isolation are formed. By having impurities diffuse from the channel 20, a collector diffused region 20 which reaches the low resistance embedded layer 14 is formed. Above the low resistance embedded layer 14 in the epitaxial layer 16, a base-diffused region 24 and an emitter diffused region 26 are formed at the positions separated by specified distances in the transverse direction from the channel 20. On the epitaxial layer 16, an oxide film 34 having a hole 28 for communicating with the channel 20, a hole 30 for communicating with the base-diffused region 24, and a hole 32 for communicating with the emitter diffused region 26 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor and a method of manufacturing the same, and more particularly to a bipolar transistor applied to, for example, a power transistor required to have a high breakdown voltage.

[0002]

2. Description of the Related Art FIG. 8 shows the structure of a conventional bipolar transistor 1 of this type, and FIG. 9 shows an equivalent circuit thereof. The bipolar transistor 1 includes a semiconductor substrate 2,
A low resistance buried layer 3 having a high impurity concentration is formed on a semiconductor substrate 2.
Is formed, and an epitaxial layer 4 having a low impurity concentration is formed on buried layer 3. In addition, the epitaxial layer 4
Are formed insulating isolation walls 5 for element isolation, a base diffusion region 6a, an emitter diffusion region 6b, and a collector diffusion region 6c reaching the low-resistance buried layer 3. On the epitaxial layer 4, an oxide film 7 is formed. It is formed. On the oxide film 7, a metal 8a conducting to the base diffusion region 6a, a metal 8b conducting to the emitter diffusion region 6b, and a metal 8c conducting to the collector diffusion region 6c are formed.

When the breakdown voltage of the bipolar transistor 1 is increased, the extent of the depletion layer at the base / collector junction increases. And this depletion layer becomes the buried layer 3
And the collector diffusion region 6c, the electrical characteristics of the device change. Therefore, conventionally, in order to prevent this, a sufficient thickness of the epitaxial layer 4 and an interval between the base diffusion region 6a and the collector diffusion region 6c have been ensured.

[0004]

In the prior art, the distance between the base diffusion region 6a and the collector diffusion region 6c is sufficiently ensured and the collector diffusion region 6c reaching the buried layer 3 is formed.
Is formed, it is possible to prevent a change in electrical characteristics and to reduce the power loss by reducing the resistance value R _coll . However, since impurities are diffused from the upper surface of the epitaxial layer 4 to the buried layer 3, there is a problem that it takes a long time to form the collector diffusion region 6c. In addition, the collector diffusion region 6c and the buried layer 3
Must be formed so as not to come into contact with the depletion layer as described above. However, as the formation time of the collector diffusion region 6c becomes longer, the lateral spread of impurities increases, and the buried layer 3 becomes Because of the rising, there is a problem that the cell size must be increased and the thickness of the epitaxial layer 4 must be further increased. Furthermore, in order for the collector diffusion region 6c to reach the buried layer 3, it is necessary to perform heat treatment for impurity diffusion in two steps of concentration adjustment and depth adjustment, and the manufacturing process is complicated. There was a problem.

[0005] Therefore, a main object of the present invention is to provide a quick and easy manufacturing and to reduce the cell size.
It is to provide a bipolar transistor.

[0006]

SUMMARY OF THE INVENTION The present invention comprises a semiconductor substrate, a low-resistance buried layer formed on the semiconductor substrate, and an epitaxial layer formed on the low-resistance buried layer. In the bipolar transistor in which the base region and the collector region are formed, the collector region is a bipolar transistor including a collector diffusion region formed by diffusing impurities from a groove formed on the upper surface of the epitaxial layer.

[0007]

Since the collector diffusion region extending to the low resistance buried layer is formed by diffusing impurities from the trench formed on the upper part of the epitaxial layer, the depth of diffusion of the impurity in the collector diffusion region, that is, from the bottom of the trench. The distance to the low-resistance buried layer is reduced by the depth of the groove as compared with the prior art. Therefore, the collector diffusion region can reach the low-resistance buried layer in a short time by a single heat treatment (annealing).

[0008]

According to the present invention, the time required for forming the collector diffusion region can be shortened, so that the time required for manufacturing the device can be shortened. In addition, since it is not necessary to perform heat treatment (annealing) for impurity diffusion in the collector diffusion region in two separate steps, the manufacturing process can be simplified. Further, since the diffusion time of the impurity can be shortened, it is possible to prevent the impurity from spreading significantly in the lateral direction, and to prevent the low-resistance buried layer from rising, so that the cell size can be reduced.

The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of a bipolar transistor 10 according to this embodiment will be described with reference to FIG. Bipolar transistor 10 includes a semiconductor substrate 12, on which a low resistance buried layer 14 and an epitaxial layer 16 are formed. The insulating layer 18 and the groove 20 for element isolation are formed in the epitaxial layer 16 and the groove 2 is formed.
The low-resistance buried layer 1 by diffusing impurities from
4 is formed. Above the low resistance buried layer 14 in the epitaxial layer 16, a base diffusion region 24 and an emitter diffusion region 26 are formed at a position laterally spaced from the groove 20 by a predetermined distance. Then, a hole 28 communicating with the trench 20 and a hole 30 communicating with the base diffusion region 24 are formed on the epitaxial layer 16.
An oxide film 34 having a hole 32 communicating with the emitter diffusion region 26 is formed. On the oxide film 34, a metal 36 conducting to the collector diffusion region 22 through the hole 28 and the groove 20 and a base diffusion region 24 through the hole 30 are formed. Emitter diffusion region 26 through conductive metal 38 and hole 32
A metal 40 is formed which conducts with the metal 40.

In manufacturing the bipolar transistor 10, first, as shown in FIG. 2A, impurities (such as As or Sb) are doped on a semiconductor substrate 12 made of single crystal silicon (Si) at a high concentration. The N + low resistance buried layer 14 is formed by diffusion, and the N epitaxial layer 1 having a low impurity concentration is formed on the semiconductor substrate 12 and the low resistance buried layer 14.
6 is formed by a CVD method. Then, a P + insulating isolation wall 18 is formed by diffusing an impurity (B or the like) into the epitaxial layer 16, and an impurity (B or the like) is diffused at a predetermined position above the low-resistance buried layer 14 to form a P-base. The diffusion region 24 is formed, and an oxide film 34 made of silicon oxide (SiO ₂ ) is formed on the epitaxial layer 16 by a thermal oxidation method or a CVD method. Then, as shown in FIG. 2B, the oxide film 34 is masked with a patterned resist 42, holes 28 are formed in the oxide film 34 by etching, and the epitaxial layer 16 is formed by RIE (reactive ion etching).
Then, a groove 20 having a predetermined depth is formed. Subsequently, the resist 42
2C, and after pre-cleaning, as shown in FIG. 2C, impurities (P, As, S
b) is diffused at a high concentration to form the N + collector diffusion region 22.

Then, as shown in FIG. 3D, the oxide film 34 is etched by using a patterned resist 44 as a mask, and a hole 32 is formed in the oxide film 34 on the base diffusion region 24.
Is formed, and impurities (P, As, Sb, etc.) are diffused from the hole 32 into the base diffusion region 24 to form the N emitter diffusion region 26. Subsequently, after the resist 44 is peeled off, as shown in FIG. 3E, the oxide film 34 is masked with a patterned resist 46 and etched to form a hole 30 reaching the base diffusion region 24 in the oxide film 34. Then, the thermal oxide film formed on the inner surface of the groove 20 and the hole 32 is removed. . Then, after the resist 46 is stripped, as shown in FIG. 3 (F), a metal 36 conducting to the collector diffusion region 22, a metal 38 conducting to the base diffusion region 24, and the emitter diffusion region 26 are formed on the oxide film 34.
To form a metal 40 that conducts with the metal.

According to this embodiment, the epitaxial layer 1
6, a groove 20 is formed, and impurities (P, A) are formed from the groove 20.
s, Sb, etc.) to diffuse the low-resistance buried layer 1
4, the collector diffusion region 22 is formed, so that the impurity diffusion time can be reduced, and the time required for manufacturing the device can be reduced. Further, since the diffusion time of the impurity can be shortened, the collector diffusion region 22 can be prevented from greatly expanding in the lateral direction and the low resistance buried layer 14 can be prevented from rising, so that the collector diffusion region 22 and the base diffusion region 24 can be prevented.
In addition, the cell size can be reduced while the space between the insulating isolation wall 18 and the space between the base diffusion region 24 and the low-resistance buried layer 14 is sufficiently ensured, so that the degree of integration and the cost can be reduced. Further, since only one step shown in FIG. 2C is required to diffuse the impurity in the collector diffusion region 22, the manufacturing process can be simplified as compared with the conventional technique in which the heat treatment is performed twice. It is possible to avoid risks such as contamination and operational errors accompanying the attached process.

In the above-described embodiment, the emitter diffusion region 26 is formed by masking the groove 20 with the resist 44 in the step shown in FIG. 3D.
As shown in (1), the impurity may be simultaneously diffused into the collector diffusion region 22 to form the high concentration region 22a inside the collector diffusion region 22. In the above-described embodiment, the collector diffusion region 22 and the emitter diffusion region 26 are separately formed. However, for example, as shown in FIG. The diffusion region 22 and the emitter diffusion region 26 may be formed simultaneously.

When the depth of the groove 20 is increased, the coverage of the metal 36 is deteriorated, and an increase in the wiring resistance value or the possibility of disconnection occurs in the groove 20. For example, FIGS. 6A and 6B or FIG. 7A and 7B, a hole 48 is formed in the oxide film 34 in the vicinity of the groove 20, and impurities (P, As, Sb, etc.) are diffused from the hole 48 to form the collector diffusion region 22. An N + low resistance region 50 is formed, which is electrically connected to the low resistance region 50.
May be connected. In this case, metal 3
6 can be connected to the low-resistance region 50 with sufficient coverage, so that problems such as an increase in wiring resistance and disconnection do not occur.

[Brief description of the drawings]

FIG. 1 is an illustrative view showing one embodiment of the present invention;

FIG. 2 is an illustrative view showing a manufacturing method of the embodiment in FIG. 1;

FIG. 3 is an illustrative view showing a manufacturing method of the embodiment in FIG. 1;

FIG. 4 is an illustrative view showing another embodiment of the present invention;

FIG. 5 is an illustrative view showing another embodiment of the present invention;

FIG. 6 is an illustrative view showing another embodiment of the present invention;

FIG. 7 is an illustrative view showing another embodiment of the present invention;

FIG. 8 is an illustrative view showing a conventional technique;

FIG. 9 is an equivalent circuit diagram of the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Bipolar transistor 12 ... Semiconductor substrate 14 ... Low resistance buried layer 16 ... Epitaxial layer 18 ... Insulating separation wall 20 ... Groove 22 ... Collector diffusion region 24 ... Base diffusion region 26 ... Emitter diffusion region 34 ... Oxide films 36, 38, 40… Metal (for wiring)

Claims (7)

[Claims] 1. A semiconductor substrate, comprising: a low resistance buried layer formed on the semiconductor substrate; and an epitaxial layer formed on the low resistance buried layer, wherein the epitaxial layer has an emitter region, a base region, and a collector region. 2. The bipolar transistor according to claim 1, wherein the collector region includes a collector diffusion region formed by diffusing impurities from a groove formed on an upper surface of the epitaxial layer. 2. The bipolar transistor according to claim 1, wherein said collector diffusion region reaches said low resistance buried layer. 3. The semiconductor device according to claim 1, further comprising: a low-resistance region formed above said epitaxial layer in the vicinity of said trench and electrically connected to said collector diffusion region; and a metal connected to said low-resistance region. 3. The bipolar transistor according to 1 or 2. 4. A bipolar transistor for forming a low resistance buried layer on a semiconductor substrate, forming an epitaxial layer on the low resistance buried layer, and forming an emitter region, a base region, and a collector region above the epitaxial layer. In the method for manufacturing a transistor, a groove is formed on an upper surface of the epitaxial layer, and a first impurity is diffused from the groove to form a collector diffusion region that constitutes a part of the collector region. A method for manufacturing a bipolar transistor. 5. An emitter region is formed by diffusing a second impurity into an upper portion of the epitaxial layer spaced apart from the groove by a predetermined distance in the horizontal direction, and simultaneously forming the second region from the groove.
5. The method of manufacturing a bipolar transistor according to claim 4, wherein said impurity is diffused to form a high concentration region inside said collector diffusion region. 6. The first impurity is diffused from the trench to form the collector diffusion region, and at the same time, the first impurity is diffused horizontally above the epitaxial layer at a predetermined interval from the trench. 5. The method for manufacturing a bipolar transistor according to claim 4, wherein said emitter region is formed by performing said step. 7. A low resistance region electrically connected to the collector diffusion region is formed above the epitaxial layer in the vicinity of the trench, and a metal is connected to the low resistance region. 7. The method for manufacturing a bipolar transistor according to any one of 6.