JP2000299457A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JP2000299457A JP2000299457A JP11105126A JP10512699A JP2000299457A JP 2000299457 A JP2000299457 A JP 2000299457A JP 11105126 A JP11105126 A JP 11105126A JP 10512699 A JP10512699 A JP 10512699A JP 2000299457 A JP2000299457 A JP 2000299457A
- Authority
- JP
- Japan
- Prior art keywords
- type
- layer
- polysilicon layer
- type polysilicon
- concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 170
- 229920005591 polysilicon Polymers 0.000 claims abstract description 170
- 230000002457 bidirectional effect Effects 0.000 claims abstract description 52
- 238000005468 ion implantation Methods 0.000 claims abstract description 38
- 238000009792 diffusion process Methods 0.000 claims abstract description 31
- 239000010410 layer Substances 0.000 claims description 161
- 239000012535 impurity Substances 0.000 claims description 37
- 239000011229 interlayer Substances 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 20
- 239000002344 surface layer Substances 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 14
- 230000002093 peripheral effect Effects 0.000 claims description 11
- 229910052782 aluminium Inorganic materials 0.000 claims description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 5
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 21
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 239000006185 dispersion Substances 0.000 abstract 1
- -1 boron fluoride ions Chemical class 0.000 description 17
- 229910052796 boron Inorganic materials 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 5
- 239000011574 phosphorus Substances 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 229910015900 BF3 Inorganic materials 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 238000011109 contamination Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置及びそ
の製造方法に関し、特に、ゲート電極を溝内部に設けた
縦型のＰチャネル型パワーＭＯＳトランジスタと、この
ＭＯＳトランジスタを保護するポリシリコンからなる双
方向性ダイオードとを有した半導体装置及びその製造方
法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a vertical P-channel power MOS transistor having a gate electrode provided in a trench, and a polysilicon protecting the MOS transistor. The present invention relates to a semiconductor device having a bidirectional diode and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】この種の半導体装置であるパワーＭＯＳ
ＦＥＴは、チップのセル部にトランジスタ機能を有する
多数の並列接続されたユニットセルが配置され、ゲート
パッド部には外部への電気的接続のためのゲートパッド
の周りにポリシリコンからなるゲート保護のための双方
向性ダイオードが配置された構造が一般的である。この
ＭＯＳＦＥＴはチャネルが半導体本体の溝深さ方向に形
成され、チャネルが半導体本体の面方向に形成されるゲ
ートプレーナ型のＭＯＳＦＥＴに比較してユニットセル
の高集積化が可能であり、単位面積あたりのチャネル幅
を大きくとれ、素子の低オン抵抗化に非常に有効である
ことが知られている。以下、従来のＰチャネル型パワー
ＭＯＳＦＥＴについて、図５を参照して説明する。2. Description of the Related Art A power MOS which is a semiconductor device of this kind
In the FET, a number of parallel-connected unit cells having a transistor function are arranged in a cell portion of a chip, and a gate protection portion made of polysilicon is provided around a gate pad for external electrical connection in a gate pad portion. Structure in which a bidirectional diode is arranged for the purpose. In this MOSFET, the channel is formed in the depth direction of the groove of the semiconductor body, and the unit cell can be highly integrated as compared with the gate planar type MOSFET in which the channel is formed in the surface direction of the semiconductor body. It is known that a large channel width can be obtained, which is very effective in reducing the on-resistance of the device. Hereinafter, a conventional P-channel type power MOSFET will be described with reference to FIG.
【０００３】図において１は半導体本体で、高濃度Ｐ型
であるＰ+ 型半導体基板２と、この半導体基板２上に設
け、セル部Ａの表面にＵ字型溝３が格子状に形成される
と共にゲートパッド部Ｂに凹部４が形成されたエピタキ
シャル層５とを有している。まず、セル部Ａについて説
明する。エピタキシャル層５表面に形成されたＵ字型溝
３の内部にゲート酸化膜６を介してポリシリコンからな
るゲート電極７が形成されている。エピタキシャル層５
はエピタキシャル層５の初期層であり低濃度Ｐ型である
Ｐ- 型ドレイン領域８と、このドレイン領域８表面層の
Ｕ字型溝３により分離された領域にＵ字型溝３より浅く
設けたＮ型ベース領域９と、ベース領域９の表面層に設
けたＮ+ 型コンタクトベース領域９ａおよびＰ+ 型ソー
ス領域１０とを含んでいる。エピタキシャル層５上には
ゲート電極７を被覆するように層間絶縁膜１１を設け、
更にその上には層間絶縁膜１１のコンタクトホールを通
してソース領域１０およびコンタクトベース領域９ａ表
面とオーミック接触により電気的接続するアルミニウム
を主金属とするソース電極１２を設けている。ソース電
極１２はその一部を外部への電気的接続のためのソース
パッドとしている。In FIG. 1, reference numeral 1 denotes a semiconductor body, which is a P + type semiconductor substrate 2 which is a high-concentration P type, and a U-shaped groove 3 is formed on the surface of the cell portion A in a lattice shape. And an epitaxial layer 5 in which a recess 4 is formed in the gate pad portion B. First, the cell section A will be described. A gate electrode 7 made of polysilicon is formed via a gate oxide film 6 inside a U-shaped groove 3 formed on the surface of the epitaxial layer 5. Epitaxial layer 5
Is a shallow P-type drain region 8 which is an initial layer of the epitaxial layer 5 and has a low concentration P type, and a region which is separated by the U-shaped groove 3 in the surface layer of the drain region 8. It includes an N-type base region 9, an N + -type contact base region 9 a and a P + -type source region 10 provided in a surface layer of the base region 9. An interlayer insulating film 11 is provided on the epitaxial layer 5 so as to cover the gate electrode 7,
Further thereon, a source electrode 12 made of aluminum as a main metal, which is electrically connected to the source region 10 and the surface of the contact base region 9a through ohmic contact through a contact hole of the interlayer insulating film 11, is provided. Part of the source electrode 12 is used as a source pad for electrical connection to the outside.
【０００４】次に、ゲートパッド部Ｂについて説明す
る。エピタキシャル層５表面に形成された凹部４内面に
フィールド酸化膜１３を設け、このフィールド酸化膜１
３上の外周にポリシリコンからなる双方向性ダイオード
１４を設けている。双方向性ダイオード１４はＰ+ 型ポ
リシリコン層１５−Ｎ型ポリシリコン層１６−Ｐ+ 型ポ
リシリコン層１５−Ｎ型ポリシリコン層１６−Ｐ+ 型ポ
リシリコン層１５のＰ−Ｎ接合により構成されている。
この双方向性ダイオード１４を被覆するようにフィール
ド酸化膜１３および双方向性ダイオード１４上にセル部
Ａと共通の層間絶縁膜１１を設けている。層間絶縁膜１
１上には層間絶縁膜１１のコンタクトホールを通して双
方向性ダイオード１４の最外周部（図５では右端側）の
Ｐ+ 型ポリシリコン層１５と電気的接続したセル部Ａと
共通のソース電極１２と、双方向性ダイオード１４の最
内周部（図５では左端側）のＰ+ 型ポリシリコン層１５
と電気的接続した外部への電気的接続のためのゲートパ
ッド１７を設けている。ゲートパッド１７はゲート電極
７に図示しないゲート配線により接続されている。Next, the gate pad section B will be described. A field oxide film 13 is provided on the inner surface of the concave portion 4 formed on the surface of the epitaxial layer 5.
A bidirectional diode 14 made of polysilicon is provided on the outer circumference of the upper part 3. The bidirectional diode 14 is formed by a P-N junction of a P + type polysilicon layer 15-N type polysilicon layer 16-P + type polysilicon layer 15-N type polysilicon layer 16-P + type polysilicon layer 15. Have been.
An interlayer insulating film 11 common to the cell portion A is provided on the field oxide film 13 and the bidirectional diode 14 so as to cover the bidirectional diode 14. Interlayer insulating film 1
A source electrode 12 common to the cell portion A electrically connected to the P + -type polysilicon layer 15 on the outermost peripheral portion (the right end side in FIG. 5) of the bidirectional diode 14 through the contact hole of the interlayer insulating film 11 And a P + -type polysilicon layer 15 at the innermost periphery (left end in FIG. 5) of the bidirectional diode 14.
A gate pad 17 is provided for electrical connection to the outside, which is electrically connected to the gate. The gate pad 17 is connected to the gate electrode 7 by a gate wiring (not shown).
【０００５】[0005]
【発明が解決しようとする課題】ところで、上記の従来
のＰチャネル型パワーＭＯＳＦＥＴの双方向性ダイオー
ド１４は、Ｐ+ ／Ｎ／Ｐ+ ／Ｎ／Ｐ+ とＮ型ポリシリコ
ン層１６をＰ+ 型ポリシリコン層１５で挟む導電型のＰ
−Ｎ接合構造としており、その形成は、Ｎ型ポリシリコ
ン層１６をベース領域９と同時形成し、Ｐ+ 型ポリシリ
コン層１５をソース領域１０と同時形成しているため、
双方向性ダイオード１４及びセル部Ａを形成するための
不純物ドーズ量をそれぞれ独立に制御することができ
ず、Ｐ+ 型ポリシリコン層１５及びＮ型ポリシリコン層
１６を形成するための不純物ドーズ量は優先的に決定さ
れるソース領域１０及びベース領域９を形成するための
不純物ドーズ量と同一となる。ソース領域１０を形成す
るためのホウ素又は弗化ホウ素イオンのドーズ量は５×
１０１５ｃｍ−２程度に制御されるため同時形成される
Ｐ+ 型ポリシリコン層１５の不純物濃度を十分高くする
ことができない。またＰ+ ポリシリコン層１５をソース
領域１０と同時形成しており、ホウ素イオン又は弗化ホ
ウ素イオンのイオン注入後の熱拡散時間が短いため、Ｐ
+ 型ポリシリコン層１５をポリシリコンブロック内に十
分深く形成することができない。そのため、双方向性ダ
イオード１４の降伏電圧波形はソフトとなり、双方向性
ダイオード１４の動作抵抗が大きくなって、Ｐチャネル
型ＭＯＳＦＥＴの静電破壊耐量が低くなり、また双方向
性ダイオード１４の降伏電圧値の製造バラツキ及び製品
での変動が大きいという問題がある。また仮にソース領
域１０の濃度を更に高くできたとしても、Ｐ+ 型ポリシ
リコン層のホウ素がフィールド絶縁膜を突き抜ける虞が
ある。また、Ｎ型ポリシリコン層１６の不純物濃度を単
独に制御できないため、双方向性ダイオード１４の降伏
電圧値を任意に制御できないという問題がある。 従っ
て、本発明は上記の問題点を解決するためになされたも
ので、Ｐチャネル型ＭＯＳトランジスタの双方向性ダイ
オードをＰ型ポリシリコン層をＮ+ 型ポリシリコン層で
挟む導電型のＰ−Ｎ接合構造とし、Ｐ型ポリシリコン層
の不純物濃度の制御をセル部とは別工程で単独に制御す
ることにより双方向性ダイオードの降伏電圧波形をハー
ド波形とし、双方向性ダイオードの降伏電圧値の製造バ
ラツキ及び製品変動を小さく、かつ降伏電圧値を任意に
制御可能な半導体装置及びその製造方法を提供すること
を目的とする。By the way, the above-mentioned bidirectional diode 14 of the conventional P-channel type power MOSFET is composed of P + / N / P + / N / P + and N-type polysilicon layer 16 formed of P +. Of conductivity type sandwiched between the polysilicon layers 15
Since the N-type junction structure is formed, the N-type polysilicon layer 16 is formed simultaneously with the base region 9 and the P + type polysilicon layer 15 is formed simultaneously with the source region 10.
The impurity dose for forming the bidirectional diode 14 and the cell part A cannot be controlled independently, and the impurity dose for forming the P + type polysilicon layer 15 and the N type polysilicon layer 16 cannot be controlled independently. Is the same as the impurity dose for forming the source region 10 and the base region 9 which is determined preferentially. The dose of boron or boron fluoride ions for forming the source region 10 is 5 ×
Since the impurity concentration is controlled to about 10 15 cm −2, the impurity concentration of the simultaneously formed P + -type polysilicon layer 15 cannot be sufficiently increased. Further, since the P + polysilicon layer 15 is formed simultaneously with the source region 10 and the thermal diffusion time after the ion implantation of boron ions or boron fluoride ions is short,
+ Type polysilicon layer 15 cannot be formed sufficiently deep in the polysilicon block. Therefore, the breakdown voltage waveform of the bidirectional diode 14 becomes soft, the operating resistance of the bidirectional diode 14 increases, the withstand voltage of the P-channel MOSFET decreases, and the breakdown voltage of the bidirectional diode 14 decreases. There is a problem that the manufacturing variation of the value and the variation in the product are large. Even if the concentration of the source region 10 can be further increased, there is a possibility that boron of the P + type polysilicon layer may penetrate the field insulating film. Further, since the impurity concentration of the N-type polysilicon layer 16 cannot be independently controlled, there is a problem that the breakdown voltage value of the bidirectional diode 14 cannot be arbitrarily controlled. SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned problems, and has been made in consideration of the above-mentioned problems. A junction structure, the control of the impurity concentration of the P-type polysilicon layer is performed separately in a process different from that of the cell portion, so that the breakdown voltage waveform of the bidirectional diode is a hard waveform, and the breakdown voltage value of the bidirectional diode is It is an object of the present invention to provide a semiconductor device capable of reducing manufacturing variations and product fluctuations and controlling a breakdown voltage value arbitrarily, and a method of manufacturing the same.
【０００６】[0006]
【課題を解決するための手段】（１）本発明に係る半導
体装置は、溝内部に設けたゲート電極への電圧印加によ
り溝の深さ方向にチャネルが形成されるＰチャネル型パ
ワーＭＯＳトランジスタと、このＭＯＳトランジスタを
保護する双方向性ダイオードとを有する半導体装置にお
いて、前記双方向性ダイオードがＰ型ポリシリコン層と
これを挟む高濃度Ｎ型ポリシリコン層とのＰ−Ｎ接合構
造からなることを特徴とする。上記手段によれば、ポリ
シリコンの双方向性ダイオードをＰ型ポリシリコン層を
高濃度Ｎ型ポリシリコン層で挟む導電型のＰ−Ｎ接合構
造としているので、双方向性ダイオードの降伏電圧波形
はハードとなり、動作抵抗が小さくなる。また高濃度Ｎ
型ポリシリコン層の不純物濃度が高いため、層間絶縁膜
の製造工程での汚染に対しても高濃度Ｎ型ポリシリコン
層の表面層は影響されることはない。 （２）本発明に係る半導体装置の製造方法は上記（１）
項の半導体装置の製造方法であって、前記Ｐ型ポリシリ
コン層のためのＰ型不純物イオン注入層の形成は前記Ｍ
ＯＳトランジスタのためのイオン注入とは独立に行うと
ともに、前記Ｐ型不純物イオン注入層の熱拡散は前記Ｍ
ＯＳトランジスタのためのイオン注入後の熱拡散で行な
い、前記高濃度Ｎ型ポリシリコン層の形成は前記ＭＯＳ
トランジスタのためのイオン注入およびこの後の熱拡散
で行なうことを特徴とする。上記方法によれば、Ｐ型ポ
リシリコン層を形成するためのイオン注入以外に新たに
工程を追加することなく、Ｐ型ポリシリコン層の不純物
のドーズ量の制御をセル部とは独立に行え、かつ、セル
部の不純物濃度や拡散深さに影響しないように行え、高
濃度Ｎ型ポリシリコン層はＭＯＳトランジスタのための
イオン注入およびこの後の熱拡散と同時に高不純物濃度
に形成できる。 （３）本発明に係る半導体装置の製造方法は上記（２）
項において、前記Ｐ型不純物イオン注入層の形成を前記
Ｐ型およびＮ型ポリシリコン層にパターニングする前の
ポリシリコン膜の状態で行なうとともに、前記Ｐ型不純
物イオン注入層の熱拡散を前記ＭＯＳトランジスタのベ
ース領域形成のためのイオン注入後の熱拡散で行ない、
前記高濃度Ｎ型ポリシリコン層の形成は前記ＭＯＳトラ
ンジスタのコンタクトベース領域形成のためのイオン注
入およびこの後の熱拡散で行なうことを特徴とする。 （４）本発明に係る半導体装置は、セル部にＵ字型溝お
よびゲートパッド部に凹部が形成されセル部およびゲー
トパッド部に共通の低濃度Ｐ型ドレイン領域を含む半導
体本体を具備し、セル部において、前記半導体本体に含
まれ前記ドレイン領域の表面層で前記Ｕ字型溝に分離さ
れた領域に設けたＮ型ベース領域と、このベース領域の
表面層に設けた高濃度Ｐ型ソース領域と、前記Ｕ字型溝
の内面に設けたゲート酸化膜と、前記Ｕ字型溝にゲート
酸化膜を介して設けたポリシリコンからなるゲート電極
と、このゲート電極と層間絶縁膜で絶縁し前記ベース領
域およびソース領域に電気的接続したアルミニウムを主
金属とするソース電極とを具備し、ゲートパッド部にお
いて、前記凹部内に設けたフィールド酸化膜と、このフ
ィールド酸化膜上に前記層間絶縁膜を介して設けたアル
ミニウムを主金属とするゲートパッドと、前記フィール
ド酸化膜上でこのゲートパッドの周りに設け、Ｐ型ポリ
シリコン層とこれを挟む高濃度Ｎ型ポリシリコン層とか
らなる双方向性ダイオードとを具備し、前記Ｎ型ポリシ
リコン層のうち、最外周部のＮ型ポリシリコン層に前記
ソース電極を電気的接続し、最内周部のＮ型ポリシリコ
ン層に前記ゲートパッドを電気的接続している。 （５）本発明に係る半導体装置は上記（４）項におい
て、前記半導体本体が半導体基板上に形成されたエピタ
キシャル層であることを特徴とする。 （６）本発明に係る半導体装置は上記（５）項におい
て、前記半導体基板が高濃度Ｐ型であることを特徴とす
る。 （７）本発明に係る半導体装置は上記（６）項におい
て、前記半導体基板が高濃度Ｎ型であることを特徴とす
る。 （８）本発明に係る半導体装置の製造方法は、ドレイン
領域となる低濃度Ｐ型半導体層を表面側に含む半導体本
体表面のセル部に初期溝とゲートパッド部に初期凹部と
を形成する第１工程と、第１工程完了後、前記初期溝お
よび初期凹部の内面にＬＯＣＯＳ酸化膜を形成すること
より初期溝がＵ字型溝および初期凹部が凹部に形状変形
された後、半導体本体表面をポリシリコン膜で被覆し、
このポリシリコン膜にＰ型イオン注入層を形成して後、
このポリシリコン膜をパターニングして前記凹部のＬＯ
ＣＯＳ酸化膜上の外周にポリシリコンブロックを形成す
る第２工程と、第２工程完了後、前記ＬＯＣＯＳ酸化膜
をマスクにＮ型不純物をイオン注入しその後熱拡散し
て、前記半導体層の表面層の前記Ｕ字型溝に分離された
領域にＮ型ベース領域を形成し、前記熱拡散により前記
Ｐ型不純物イオン注入層を熱拡散して前記ポリシリコン
ブロックをＰ型ポリシリコン層とする第３工程と、第３
工程完了後、前記Ｐ型ポリシリコン層の少なくとも最内
周部および最外周部と前記ベース領域表面の一部とを露
出させたレジストパターンを形成し、このレジストパタ
ーンをマスクに高濃度Ｎ型不純物をイオン注入しその後
熱拡散して、前記ベース領域表面層に高濃度Ｎ型コンタ
クトベース領域と前記Ｐ型ポリシリコン層の少なくとも
最内周部および最外周部に高濃度Ｎ型ポリシリコン層と
を形成し、前記ポリシリコンブロックを双方向性ダイオ
ードとする第４工程と、第４工程完了後、前記ベース領
域およびコンタクトベース領域の表面の一部と前記ダイ
オードの表面を被覆させたレジストパターンを形成して
後、このレジストパターンと前記ＬＯＣＯＳ酸化膜とを
マスクに高濃度Ｐ型不純物をイオン注入しその後熱拡散
して、前記ベース領域の表面層に高濃度Ｐ型ソース領域
を形成する第５工程と、第５工程完了後、前記Ｕ字型溝
のＬＯＣＯＳ酸化膜を除去するとともに前記凹部のＬＯ
ＣＯＳ酸化膜をフィールド酸化膜として残す第６工程
と、第６工程完了後、Ｕ字型溝内面を含む露出した半導
体本体表面にゲート酸化膜を形成した後、その上からポ
リシリコン膜で被覆し、このポリシリコン膜をパターニ
ングして、前記ソース領域表面の一部およびＵ字型溝の
ポリシリコン膜を残してゲート電極を形成する第６工程
と、第６工程完了後、その上から層間絶縁膜で被覆し、
この層間絶縁膜をパターニングして、前記コンタクトベ
ース領域およびソース領域の表面と前記ポリシリコンブ
ロックの最内周部および最外周部の高濃度Ｎ型ポリシリ
コン層の表面とを露出する第７工程と、第７工程完了
後、その上からアルミニウム膜で被覆し、このアルミニ
ウムを主金属とする金属膜をパターニングして、前記コ
ンタクトベース領域およびソース領域と前記最外周部の
高濃度Ｎ型ポリシリコン層とに電気的接続するソース電
極を形成し、前記最内周部の高濃度Ｎ型ポリシリコン層
に電気的接続するゲートパッドを前記フィールド絶縁膜
上のダイオード内側に前記層間絶縁膜を介して形成する
第８工程とを有する。(1) A semiconductor device according to the present invention includes a P-channel power MOS transistor in which a channel is formed in a depth direction of a groove by applying a voltage to a gate electrode provided in the groove. A bidirectional diode for protecting the MOS transistor, wherein the bidirectional diode has a PN junction structure of a P-type polysilicon layer and a high-concentration N-type polysilicon layer sandwiching the P-type polysilicon layer. It is characterized by. According to the above-described means, since the polysilicon bidirectional diode has a conductive PN junction structure in which the P-type polysilicon layer is sandwiched between the high-concentration N-type polysilicon layers, the breakdown voltage waveform of the bidirectional diode is It becomes hard, and the operating resistance becomes small. In addition, high concentration N
Since the impurity concentration of the polysilicon layer is high, the surface layer of the high-concentration N-type polysilicon layer is not affected by the contamination in the manufacturing process of the interlayer insulating film. (2) The method for manufacturing a semiconductor device according to the present invention is as described in (1) above.
3. The method of manufacturing a semiconductor device according to item 1, wherein the formation of a P-type impurity ion-implanted layer for the P-type polysilicon
This is performed independently of the ion implantation for the OS transistor, and the thermal diffusion of the P-type
Thermal diffusion after ion implantation for an OS transistor is performed, and the formation of the high-concentration N-type polysilicon layer is performed by using the MOS transistor.
It is characterized in that it is performed by ion implantation for a transistor and thereafter by thermal diffusion. According to the above method, the dose of the impurity in the P-type polysilicon layer can be controlled independently of the cell portion without adding a new step other than the ion implantation for forming the P-type polysilicon layer, In addition, the operation can be performed without affecting the impurity concentration and diffusion depth of the cell portion, and the high-concentration N-type polysilicon layer can be formed with a high impurity concentration simultaneously with ion implantation for the MOS transistor and subsequent thermal diffusion. (3) The method for manufacturing a semiconductor device according to the present invention is as described in (2) above.
3. The method according to claim 1, wherein the P-type impurity ion-implanted layer is formed in a state of the polysilicon film before being patterned into the P-type and N-type polysilicon layers, and the P-type impurity ion-implanted layer is thermally diffused by the MOS transistor. Thermal diffusion after ion implantation to form a base region of
The high-concentration N-type polysilicon layer is formed by ion implantation for forming a contact base region of the MOS transistor and thereafter by thermal diffusion. (4) A semiconductor device according to the present invention includes a semiconductor body including a U-shaped groove in a cell portion and a concave portion in a gate pad portion, the semiconductor body including a low-concentration P-type drain region common to the cell portion and the gate pad portion. In the cell portion, an N-type base region provided in a region included in the semiconductor body and separated by the U-shaped groove in a surface layer of the drain region; and a high-concentration P-type source provided in a surface layer of the base region. A region, a gate oxide film provided on the inner surface of the U-shaped groove, a gate electrode made of polysilicon provided in the U-shaped groove via the gate oxide film, and insulated by the gate electrode and an interlayer insulating film. A source electrode mainly composed of aluminum electrically connected to the base region and the source region; a field oxide film provided in the recess in the gate pad portion; A gate pad made of aluminum as a main metal provided through the interlayer insulating film, a P-type polysilicon layer provided around the gate pad on the field oxide film, and a high-concentration N-type polysilicon layer sandwiching the P-type polysilicon layer. A source electrode is electrically connected to the outermost N-type polysilicon layer of the N-type polysilicon layer, and the innermost N-type polysilicon layer is connected to the innermost N-type polysilicon layer. The gate pads are electrically connected. (5) In the semiconductor device according to the present invention, in the above item (4), the semiconductor body is an epitaxial layer formed on a semiconductor substrate. (6) In the semiconductor device according to the present invention, in the above item (5), the semiconductor substrate is a high-concentration P-type. (7) In the semiconductor device according to the present invention, in the above item (6), the semiconductor substrate is a high-concentration N-type. (8) In the method of manufacturing a semiconductor device according to the present invention, an initial groove is formed in a cell portion on a surface of a semiconductor body including a low-concentration P-type semiconductor layer serving as a drain region on a surface side, and an initial recess is formed in a gate pad portion. After completion of the first step and the first step, the LOCOS oxide film is formed on the inner surface of the initial groove and the initial concave portion, so that the initial groove is deformed into a U-shaped groove and the initial concave portion. Covered with a polysilicon film,
After forming a P-type ion implantation layer in this polysilicon film,
This polysilicon film is patterned to form the LO
A second step of forming a polysilicon block on the outer periphery of the COS oxide film, and after completion of the second step, ion-implanting N-type impurities using the LOCOS oxide film as a mask and then thermally diffusing the same to form a surface layer of the semiconductor layer Forming an N-type base region in a region separated by the U-shaped groove, and thermally diffusing the P-type impurity ion-implanted layer by the thermal diffusion to make the polysilicon block a P-type polysilicon layer. Process and third
After the step is completed, a resist pattern exposing at least the innermost and outermost peripheral portions of the P-type polysilicon layer and a part of the surface of the base region is formed. Using this resist pattern as a mask, a high-concentration N-type impurity is formed. Is ion-implanted and then thermally diffused to form a high-concentration N-type contact base region on the base region surface layer and a high-concentration N-type polysilicon layer on at least the innermost periphery and the outermost periphery of the P-type polysilicon layer. A fourth step of forming the polysilicon block as a bidirectional diode, and after completion of the fourth step, forming a resist pattern covering a part of the surface of the base region and the contact base region and the surface of the diode. Then, using this resist pattern and the LOCOS oxide film as a mask, a high-concentration P-type impurity is ion-implanted and then thermally diffused to form the base. A fifth step of forming a high-concentration P-type source region in the surface layer of the band, after the completion of the fifth step, LO of the recess to remove the LOCOS oxide film of the U-shaped groove
A sixth step in which the COS oxide film is left as a field oxide film, and after completion of the sixth step, a gate oxide film is formed on the exposed surface of the semiconductor body including the inner surface of the U-shaped groove, and then a polysilicon film is coated thereon. A sixth step of patterning the polysilicon film to form a gate electrode while leaving a part of the source region surface and the polysilicon film of the U-shaped groove; and after the completion of the sixth step, an interlayer insulating film is formed thereon. Coated with a membrane,
A seventh step of patterning the interlayer insulating film to expose the surfaces of the contact base region and the source region and the surface of the high-concentration N-type polysilicon layer at the innermost periphery and the outermost periphery of the polysilicon block; After the completion of the seventh step, a high-concentration N-type polysilicon layer of the contact base region, the source region, and the outermost peripheral portion is covered with an aluminum film from above, and the metal film containing aluminum as a main metal is patterned. And a gate pad electrically connected to the high-concentration N-type polysilicon layer at the innermost periphery is formed inside the diode on the field insulating film via the interlayer insulating film. And an eighth step.
【０００７】[0007]
【発明の実施の形態】以下に、本発明に基づき１実施例
のＰチャネル型パワーＭＯＳＦＥＴおよびその製造方法
を図１乃至図４を参照して説明する。まず、構成を説明
すると、図１において、２１は半導体本体で、高濃度Ｐ
型であるＰ+ 型半導体基板２２と、この半導体基板２２
上に設け、セル部Ａの表面にＵ字型溝２３が格子状に形
成されると共にゲートパッド部Ｂに凹部２４が形成され
たエピタキシャル層２５とを有している。セル部Ａにつ
いて説明する。エピタキシャル層２５表面に形成された
Ｕ字型溝２３の内部にゲート酸化膜２６を介してポリシ
リコンからなるゲート電極２７が形成されている。エピ
タキシャル層２５はエピタキシャル層２５の初期層であ
り低濃度Ｐ型であるＰ- 型ドレイン領域２８と、このド
レイン領域２８表面層のＵ字型溝２３により分離された
領域にＵ字型溝２３より浅く設けたＮ型ベース領域２９
と、ベース領域２９の表面層に設けたＮ+ 型コンタクト
ベース領域２９ａおよびＰ+ 型ソース領域３０とを含ん
でいる。エピタキシャル層２５表面のＵ字型溝２３によ
り分離された各領域の平面的な構造は図２に示すよう
に、ソース領域３０は全体が略正方形であり、且つ、所
定の一定幅で離隔した非環状の略４等分に分割された３
角形の４分割ソース領域３０ａであり、ベース領域２９
（コンタクトベース領域２９ａを含む）は４分割ソース
領域３０ａ間の幅狭なソース分割ベース領域２９ｂであ
る。エピタキシャル層２５上にはゲート電極２７を被覆
するように層間絶縁膜３１を設け、更にその上には層間
絶縁膜３１のコンタクトホールを通してソース領域３０
およびコンタクトベース領域２９ａ表面とオーミック接
触により電気的接続するアルミニウムを主金属とするソ
ース電極３２を設けている。ソース電極３２はその一部
を外部への電気的接続のためのソースパッドとしてい
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A P-channel power MOSFET according to one embodiment of the present invention and a method of manufacturing the same will be described below with reference to FIGS. First, the structure will be described. In FIG. 1, reference numeral 21 denotes a semiconductor body,
A P + type semiconductor substrate 22 and a semiconductor substrate 22
And an epitaxial layer 25 in which U-shaped grooves 23 are formed in a lattice shape on the surface of the cell portion A and a concave portion 24 is formed in the gate pad portion B. The cell section A will be described. A gate electrode 27 made of polysilicon is formed inside a U-shaped groove 23 formed on the surface of the epitaxial layer 25 via a gate oxide film 26. The epitaxial layer 25 is an initial layer of the epitaxial layer 25 and has a P- type drain region 28 of a low concentration P type, and a region separated by the U-shaped groove 23 on the surface layer of the drain region 28 from the U-shaped groove 23. N-type base region 29 provided shallowly
And an N + type contact base region 29a and a P + type source region 30 provided in the surface layer of the base region 29. As shown in FIG. 2, the planar structure of each region separated by the U-shaped groove 23 on the surface of the epitaxial layer 25 is such that the source region 30 is substantially square in its entirety and is separated by a predetermined constant width. 3 divided into approximately four equal rings
It is a quadrangular source region 30a and the base region 29
(Including the contact base region 29a) is a narrow source division base region 29b between the four division source regions 30a. An interlayer insulating film 31 is provided on the epitaxial layer 25 so as to cover the gate electrode 27, and a source region 30 is further formed thereon through a contact hole of the interlayer insulating film 31.
In addition, a source electrode 32 mainly made of aluminum and electrically connected to the surface of the contact base region 29a by ohmic contact is provided. Part of the source electrode 32 is used as a source pad for external electrical connection.
【０００８】次に、ゲートパッド部Ｂについて説明す
る。エピタキシャル層２５表面に形成された凹部２４内
面にフィールド酸化膜３３を設け、このフィールド酸化
膜３３上の周りにポリシリコンからなる双方向性ダイオ
ード３４を設けている。双方向性ダイオード３４はＮ+
型ポリシリコン層３５−Ｐ型ポリシリコン層３６−Ｎ+
型ポリシリコン層３５−Ｐ型ポリシリコン層３６−Ｐ+
型ポリシリコン層３５のＰ−Ｎ接合により構成されてい
る。この双方向性ダイオード３４を被覆するようにフィ
ールド酸化膜３３および双方向性ダイオード３４上にセ
ル部Ａと共通の層間絶縁膜３１を設けている。フィール
ド酸化膜３３上の双方向性ダイオード３４の内側には層
間絶縁膜３１を介して外部への電気的接続のためのゲー
トパッド３７を設けている。双方向性ダイオード３４の
最外周部（図１では右端側）のＮ+型ポリシリコン層３
５には層間絶縁膜３１のコンタクトホールを通してセル
部Ａからソース電極３２が跨り電気的接続しており、双
方向性ダイオード３４の最内周部（図１では左端側）の
Ｎ+ 型ポリシリコン層３５には層間絶縁膜３１のコンタ
クトホールを通してゲートパッド３７が跨り電気的接続
している。ゲートパッド３７はゲート電極２７に図示し
ないゲート配線により接続されている。Next, the gate pad section B will be described. A field oxide film 33 is provided on the inner surface of the recess 24 formed on the surface of the epitaxial layer 25, and a bidirectional diode 34 made of polysilicon is provided around the field oxide film 33. The bidirectional diode 34 is N +
Polysilicon layer 35-P polysilicon layer 36-N @ +
Type polysilicon layer 35-P type polysilicon layer 36-P +
It is constituted by a PN junction of the type polysilicon layer 35. An interlayer insulating film 31 common to the cell portion A is provided on the field oxide film 33 and the bidirectional diode 34 so as to cover the bidirectional diode 34. A gate pad 37 for electrical connection to the outside via the interlayer insulating film 31 is provided inside the bidirectional diode 34 on the field oxide film 33. N + type polysilicon layer 3 at the outermost periphery (right end in FIG. 1) of bidirectional diode 34
5 is electrically connected across the source electrode 32 from the cell portion A through the contact hole of the interlayer insulating film 31. The N + type polysilicon at the innermost portion (left end in FIG. 1) of the bidirectional diode 34 is connected. The gate pad 37 is electrically connected to the layer 35 through the contact hole of the interlayer insulating film 31. The gate pad 37 is connected to the gate electrode 27 by a gate wiring (not shown).
【０００９】上記構成によれば、ポリシリコンの双方向
性ダイオード３４をＮ+ ／Ｐ／Ｎ+／Ｐ／Ｎ+ とＰ型ポ
リシリコン層３６をＮ+ 型ポリシリコン層３５で挟む導
電型構造としているので、双方向性ダイオード３４の降
伏電圧波形はハードとなり、動作抵抗が小さくなるため
Ｐチャネル型パワーＭＯＳＦＥＴの静電破壊耐量が向上
する。またＮ+ 型ポリシリコン層３５の不純物濃度が高
いため、ゲートパッド３７とＮ+ 型ポリシリコン層３５
に挟まれた層間絶縁膜３１の製造工程での汚染に対して
もＮ+ 型ポリシリコン層３５の表面層は影響されること
はなく、双方向性ダイオード３４の降伏電圧値の製造バ
ラツキ及び製品変動は小さくなり、設計どおりの降伏電
圧値で信頼性の高い双方向性ダイオード３４を有するＰ
チャネル型パワーＭＯＳＦＥＴを製造できる。According to the above structure, the polysilicon type bidirectional diode 34 has a conductive type structure in which the N + / P / N + / P / N + and the P-type polysilicon layer 36 are sandwiched between the N + -type polysilicon layers 35. Therefore, the breakdown voltage waveform of the bidirectional diode 34 becomes hard and the operating resistance is reduced, so that the electrostatic breakdown resistance of the P-channel power MOSFET is improved. Since the impurity concentration of the N + type polysilicon layer 35 is high, the gate pad 37 and the N + type polysilicon layer 35
The surface layer of the N + -type polysilicon layer 35 is not affected by the contamination in the manufacturing process of the interlayer insulating film 31 sandwiched between the layers, and the manufacturing variation of the breakdown voltage value of the bidirectional diode 34 and the product The fluctuation is small, and a P-type diode having a highly reliable bidirectional diode 34 with a designed breakdown voltage value is obtained.
A channel type power MOSFET can be manufactured.
【００１０】次に製造方法を図３（ａ）〜（ｄ）、図４
（ｅ）〜（ｈ）および図１を参照して説明する。先ず、
第１工程はこの工程の完了後を図３（ａ）に示すよう
に、半導体本体２１として高濃度Ｐ型であるＰ+ 型半導
体基板２２上に低濃度Ｐ型半導体層であるＰ- 型エピタ
キシャル層２５を形成したウェーハを準備し、このエピ
タキシャル層２５の表面に熱酸化法によりシリコン酸化
膜５３を例えば、膜厚５００オングストローム程度に形
成し、更にその上にシリコン窒化膜５４をＣＶＤ法によ
り例えば、膜厚９００オングストローム程度に成長させ
た後、フォトリソグラフィ法およびドライエッチ法によ
り選択的に窒化膜５４、酸化膜５３およびエピタキシャ
ル層２５をエッチングして、セル部Ａとなる領域に初期
溝５５を格子状に形成すると共に、ゲートパッド部Ｂと
なる領域に初期凹部５６を形成する。初期溝５５および
初期凹部５６は深さを例えば、１．３μｍねらいでエッ
チングして形成される。Next, the manufacturing method will be described with reference to FIGS.
This will be described with reference to (e) to (h) and FIG. First,
In the first step, as shown in FIG. 3A, after the completion of this step, a P- type epitaxial layer, which is a low-concentration P-type semiconductor layer, is formed on a high-concentration P-type P + type semiconductor substrate 22 as a semiconductor body 21. A wafer having the layer 25 formed thereon is prepared, a silicon oxide film 53 is formed on the surface of the epitaxial layer 25 by thermal oxidation to a thickness of, for example, about 500 angstroms, and a silicon nitride film 54 is further formed thereon by, for example, a CVD method. After growing to a thickness of about 900 angstroms, the nitride film 54, the oxide film 53 and the epitaxial layer 25 are selectively etched by photolithography and dry etching to form an initial groove 55 in a region to be the cell portion A. The initial concave portion 56 is formed in a region to be the gate pad portion B while being formed in a lattice shape. The initial groove 55 and the initial concave portion 56 are formed by etching with a depth of, for example, 1.3 μm.
【００１１】次に、第２工程はこの工程の完了後を図３
（ｂ）に示すように、第１工程完了後、窒化膜５４をマ
スクとして初期溝５５および初期凹部５６の内面を熱酸
化して例えば、膜厚７０００オングストローム程度のＬ
ＯＣＯＳ酸化膜５７を形成すると、初期溝５５がＵ字型
溝２３、および、初期凹部５６が凹部２４に形状変形さ
れる。その後、ウェーハの表面をＣＶＤ法によりポリシ
リコン膜で被覆し、この上からホウ素イオンまたは弗化
ホウ素イオンを例えば４．０×１０14ｃｍ-2程度のドー
ズ量でイオン注入して表面にホウ素イオン注入層５８を
形成する。この後、フォトリソグラフィ法およびドライ
エッチ法により、ゲートパッド部ＢのＬＯＣＯＳ酸化膜
５７上にポリシリコン膜を残してポリシリコンブロック
５９を形成する。Next, in a second step, FIG.
As shown in (b), after the first step is completed, the inner surfaces of the initial groove 55 and the initial concave portion 56 are thermally oxidized using the nitride film 54 as a mask, for example, to form an L film having a thickness of about 7000 Å.
When the OCOS oxide film 57 is formed, the initial groove 55 is deformed into the U-shaped groove 23 and the initial concave part 56 is deformed into the concave part 24. Thereafter, the surface of the wafer is coated with a polysilicon film by the CVD method, and boron ions or boron fluoride ions are ion-implanted from above the polysilicon film at a dose of, for example, about 4.0 × 10 14 cm −2 to form boron ions on the surface. An injection layer 58 is formed. Thereafter, a polysilicon block 59 is formed on the LOCOS oxide film 57 of the gate pad portion B by a photolithography method and a dry etching method, leaving a polysilicon film.
【００１２】次に、第３工程はこの工程の完了後を図３
（ｃ）に示すように、第２工程完了後、窒化膜５４およ
び酸化膜５３をウェットエッチ法により全面除去し、熱
酸化法によりイオン注入のためのシリコン酸化膜６０を
例えば、膜厚１００オングストローム程度に形成して
後、ＬＯＣＯＳ酸化膜５７をマスクにしてシリコン酸化
膜６０を介してセル部Ａの表面層内に選択的にヒ素イオ
ン又はリンイオンを例えば３．０×１０13ｃｍ-2程度の
ドーズ量でイオン注入及び熱拡散してＮ型ベース領域２
９を形成する。このときの熱拡散によりホウ素イオン注
入層５８も熱拡散され、ポリシリコンブロック５９全体
がＰ型ポリシリコン層３６となる。ヒ素イオン又はリン
イオンのイオン注入のとき露出されたポリシリコンブロ
ック５９にもヒ素イオン又はリンイオンが同時に注入さ
れるがホウ素イオン注入層５８よりドーズ量が少ないた
めＰ型ポリシリコン層３６への影響はない。Next, FIG. 3 shows a third step after completion of this step.
As shown in (c), after the completion of the second step, the nitride film 54 and the oxide film 53 are entirely removed by a wet etching method, and a silicon oxide film 60 for ion implantation is formed to a thickness of, for example, 100 Å by a thermal oxidation method. After the formation, the LOCOS oxide film 57 is used as a mask to selectively deposit arsenic ions or phosphorus ions in the surface layer of the cell portion A via the silicon oxide film 60, for example, about 3.0 × 10 13 cm −2 . N-type base region 2 by ion implantation and thermal diffusion at a dose amount
9 is formed. At this time, the boron ion implantation layer 58 is also thermally diffused by the thermal diffusion, and the entire polysilicon block 59 becomes the P-type polysilicon layer 36. Arsenic ions or phosphorus ions are simultaneously implanted into the exposed polysilicon block 59 at the time of arsenic ion or phosphorus ion implantation, but the dose is smaller than that of the boron ion implantation layer 58, so that there is no effect on the P-type polysilicon layer 36. .
【００１３】次に、第４工程はこの工程の完了後を図３
（ｄ）に示すように、第３工程完了後、フォトリソグラ
フィ法でのレジストパターン６１をマスクにベース領域
２９表面層に選択的にヒ素イオン又はリンイオンを例え
ば５．０×１０15ｃｍ-2程度のドーズ量でイオン注入し
レジストパターン６１を除去後に熱拡散してＮ+ 型コン
タクトベース領域２９ａを形成する。このとき同時に、
Ｐ型ポリシリコン層３６の少なくとも最内周部および最
外周部（本実施例では最内周部および最外周部と中央
部）にも選択的にヒ素イオン又はリンイオンをイオン注
入及び熱拡散してＮ+ 型ポリシリコン層３５を形成し、
Ｎ+ 型ポリシリコン層３５−Ｐ型ポリシリコン層３６−
Ｎ+ 型ポリシリコン層３５−Ｐ型ポリシリコン層３６−
Ｎ+ 型ポリシリコン層３５のＰ−Ｎ接合からなる双方向
性ダイオード３４を構成する。Next, in a fourth step, FIG.
As shown in (d), after the completion of the third step, arsenic ions or phosphorus ions are selectively applied to the surface layer of the base region 29 using the resist pattern 61 formed by photolithography as a mask, for example, about 5.0 × 10 15 cm −2. After the resist pattern 61 is removed by ion implantation at a dose of, a thermal diffusion is performed to form an N + -type contact base region 29a. At the same time,
Arsenic ions or phosphorus ions are selectively ion-implanted and thermally diffused into at least the innermost peripheral portion and the outermost peripheral portion (in the present embodiment, the innermost peripheral portion, the outermost peripheral portion, and the central portion) of the P-type polysilicon layer 36. Forming an N + type polysilicon layer 35;
N + type polysilicon layer 35-P type polysilicon layer 36-
N + type polysilicon layer 35-P type polysilicon layer 36-
A bidirectional diode 34 comprising a PN junction of an N + type polysilicon layer 35 is constructed.
【００１４】次に、第５工程はこの工程の完了後を図４
（ｅ）に示すように、第４工程完了後、ＬＯＣＯＳ酸化
膜５７及びレジストパターン６２をマスクにベース領域
２９およびベースコンタクト領域２９ａの表面層内に選
択的にホウ素イオン又は弗化ホウ素イオンを例えば５．
０×１０15ｃｍ-2程度のドーズ量でイオン注入しレジス
トパターン６２を除去してＰ+ 型ソース領域３０を形成
する。ベース領域２９、コンタクトベース領域２９ａ及
びソース領域３０が形成された後のエピタキシャル層２
５の元のままの領域はＰ- 型ドレイン領域２８となる。Next, in a fifth step, the completion of this step is shown in FIG.
As shown in (e), after the completion of the fourth step, the LOCOS oxide film 57 and the resist pattern 62 are used as masks to selectively deposit boron ions or boron fluoride ions in the surface layers of the base region 29 and the base contact region 29a, for example. 5.
Ion implantation is performed at a dose of about 0 × 10 15 cm −2 to remove the resist pattern 62 to form a P + type source region 30. Epitaxial layer 2 after formation of base region 29, contact base region 29a and source region 30
5 remains the P @-type drain region 28.
【００１５】次に、第６工程はこの工程の完了後を図４
（ｆ）に示すように、第５工程完了後、凹部２４内のＬ
ＯＣＯＳ酸化膜５７および双方向性ダイオード３４をフ
ォトリソグラフィ法でのレジストパターン６３でマスク
しウェットエッチ法によりＵ字型溝２３内のＬＯＣＯＳ
酸化膜５７とベース領域２９、ベースコンタクト領域２
９ａおよびソース領域３０上の酸化膜６０を除去するこ
とによりベース領域２９、ソース領域３０およびベース
コンタクト領域２９ａの表面と溝２３の内面を露出さ
せ、凹部２４に形成されたＬＯＣＯＳ酸化膜５７をフィ
ールド酸化膜３３として残す。Next, in a sixth step, FIG.
As shown in (f), after completion of the fifth step, L
The OCOS oxide film 57 and the bidirectional diode 34 are masked with a resist pattern 63 by photolithography, and the LOCOS in the U-shaped groove 23 is wet-etched.
Oxide film 57, base region 29, base contact region 2
By removing the oxide film 60 on the base region 29, the source region 30, and the base contact region 29a and the inner surface of the groove 23, the LOCOS oxide film 57 formed in the concave portion 24 is removed. The oxide film 33 is left.
【００１６】次に、第７工程はこの工程の完了後を図４
（ｇ）に示すように、第６工程完了後、ベース領域２
９、ベースコンタクト領域２９ａおよびソース領域３０
の表面と溝２３の内面に熱酸化法によりゲート酸化膜２
６を形成する。ゲート酸化膜２６の膜厚は、例えば、溝
２３の内面のベース領域２９上で５００オングストロー
ム程度に形成される。以上の工程を経たウェーハの表面
をＣＶＤ法によりポリシリコン膜で被覆し、フォトリソ
グラフィ法およびドライエッチ法により、ソース領域３
０表面の一部および溝２３のポリシリコン膜を残してゲ
ート電極２７を形成する。Next, a seventh step is shown in FIG. 4 after the completion of this step.
After completion of the sixth step, as shown in FIG.
9, base contact region 29a and source region 30
The gate oxide film 2 is formed on the surface of the
6 is formed. The gate oxide film 26 is formed to have a thickness of, for example, about 500 Å on the base region 29 on the inner surface of the groove 23. The surface of the wafer having undergone the above steps is covered with a polysilicon film by CVD, and the source region 3 is covered by photolithography and dry etching.
The gate electrode 27 is formed leaving a part of the zero surface and the polysilicon film in the groove 23.
【００１７】次に、第８工程はこの工程の完了後を図４
（ｈ）に示すように、第７工程完了後、ウェーハの表面
を層間絶縁膜３１で被覆し、この層間絶縁膜３１および
酸化膜２６をレジストパターンをマスクにエッチングし
ソース領域３０及びコンタクトベース領域２９ａと双方
向性ダイオード３４の最内周部および最外周部のＮ+型
ポリシリコン層３５表面を露出させる。そして、このと
き使用したレジストパターンを除去する。Next, in an eighth step, FIG.
As shown in (h), after the completion of the seventh step, the surface of the wafer is covered with an interlayer insulating film 31, and the interlayer insulating film 31 and the oxide film 26 are etched using a resist pattern as a mask to form a source region 30 and a contact base region. 29a and the innermost and outermost N + type polysilicon layer 35 surfaces of the bidirectional diode 34 are exposed. Then, the resist pattern used at this time is removed.
【００１８】次に、第９工程はこの工程の完了後を図１
に示すように、第８工程完了後、ウェーハの表面をアル
ミニウムを主金属とする金属膜で被覆し、レジストパタ
ーンをマスクに不要部分をエッチングにより除去して、
セル部Ａ上からゲートパッド部Ｂ上に跨がって、表面が
露出されたソース領域３０及びコンタクトベース領域２
９ａと双方向性ダイオード３４の最外周部（図１では右
端側）のＮ+ 型ポリシリコン層３５とに電気的接続した
ソース電極３２を形成し、ゲートパッド部Ｂにおいて双
方向性ダイオード４２の内側のフィールド酸化膜３３上
に層間絶縁膜３１を介して、双方向性ダイオード４２の
最内周部（図１では左端側）の表面が露出されたＮ+ 型
ポリシリコン層３５に電気的接続したゲートパッド３７
を形成する。ソース電極３２はその一部を外部への電気
的接続のためのソースパッドとしている。ゲートパッド
４７は図示しないゲート配線を介してゲート電極２７に
電気的に接続されている。Next, a ninth step is shown in FIG. 1 after the completion of this step.
As shown in the above, after the completion of the eighth step, the surface of the wafer is covered with a metal film containing aluminum as a main metal, and unnecessary portions are removed by etching using a resist pattern as a mask,
The source region 30 and the contact base region 2 whose surfaces are exposed from the cell portion A to the gate pad portion B
The source electrode 32 electrically connected to the N + -type polysilicon layer 35 at the outermost peripheral portion (the right end side in FIG. 1) of the bidirectional diode 34 is formed at the gate pad portion B. The surface of the innermost peripheral portion (left end in FIG. 1) of the bidirectional diode 42 is electrically connected to the exposed N + type polysilicon layer 35 on the inner field oxide film 33 via the interlayer insulating film 31. Gate pad 37
To form Part of the source electrode 32 is used as a source pad for external electrical connection. The gate pad 47 is electrically connected to the gate electrode 27 via a gate wiring (not shown).
【００１９】以上説明した方法によれば、ポリシリコン
の双方向性ダイオード３４をＮ+ ／Ｐ／Ｎ+ ／Ｐ／Ｎ+
とＰ型ポリシリコン層３６をＮ+ 型ポリシリコン層３５
で挟む導電型のＰ−Ｎ接合構造として形成するとき、Ｐ
型ポリシリコン層３６を形成するためのイオン注入をウ
ェーハ表面をポリシリコン膜で被覆後ポリシリコンブロ
ック５９を形成する前に行い、かつ、Ｐ型ポリシリコン
層３６を形成するためのイオン注入後の熱拡散をベース
領域２９を形成するためのイオン注入後の熱拡散と同時
に行うことにより、Ｐ型ポリシリコン層３６を形成する
ためのイオン注入以外に新たに工程を追加することな
く、Ｐ型ポリシリコン層３６の不純物のドーズ量の制御
をセル部Ａとは独立に任意に行え、かつ、Ｐ型ポリシリ
コン層３６の拡散深さをセル部Ａの不純物濃度や拡散深
さに影響せずに十分深くでき、更にＮ+ 型ポリシリコン
層３５を形成するためのイオン注入及び熱拡散はコンタ
クトベース領域２９ａを形成するためのイオン注入及び
熱拡散と同時に行うことにより、新たに工程を追加する
ことなく、Ｎ+ 型ポリシリコン層３５は高不純物濃度に
形成できる。したがって、降伏電圧波形のハードで降伏
電圧値の製造バラツキ及び工程変動の小さい双方向性ダ
イオード３４を有するＰチャネル型パワーＭＯＳＦＥＴ
を安定して製造することができる。また、Ｐチャネル型
ポリシリコン層３６の不純物濃度を制御することにより
双方向性ダイオードの降伏電圧値を任意に設定できる。According to the method described above, the polysilicon bidirectional diode 34 is connected to N + / P / N + / P / N +.
And the P-type polysilicon layer 36 with the N + type polysilicon layer 35.
When formed as a conductive type PN junction structure sandwiched by
Implantation for forming the p-type polysilicon layer 36 is performed after the wafer surface is covered with the polysilicon film and before the polysilicon block 59 is formed, and after the ion implantation for forming the p-type polysilicon layer 36 is performed. By performing the thermal diffusion at the same time as the thermal diffusion after the ion implantation for forming the base region 29, the P-type polysilicon layer can be formed without adding a new process other than the ion implantation for forming the P-type polysilicon layer 36. The dose of the impurity in the silicon layer 36 can be arbitrarily controlled independently of the cell portion A, and the diffusion depth of the P-type polysilicon layer 36 can be controlled without affecting the impurity concentration and the diffusion depth of the cell portion A. The ion implantation and thermal diffusion for forming the N + type polysilicon layer 35 can be performed simultaneously with the ion implantation and thermal diffusion for forming the contact base region 29a. And by, without adding a new step, N + -type polysilicon layer 35 may be formed on the high impurity concentration. Accordingly, a P-channel type power MOSFET having a bidirectional diode 34 having a hard breakdown voltage waveform and a small manufacturing variation of a breakdown voltage value and a small process variation.
Can be manufactured stably. Further, the breakdown voltage value of the bidirectional diode can be arbitrarily set by controlling the impurity concentration of the P-channel type polysilicon layer 36.
【００２０】上記実施例において、双方向性ダイオード
をＮ+ ／Ｐ／Ｎ+ ／Ｐ／Ｎ+ の導電型Ｐ−Ｎ接合構造で
説明したが、要求される降伏電圧値によりＰ−Ｎ接合の
段数を増減してもよい。また、セル部Ａのエピタキシャ
ル層表面の平面的な構造を図２に示すソースが非環状パ
ターンのもので説明したが、これに限定されることな
く、他の非環状パターンやソース領域がベース領域を取
り囲む環状パターンであってもよい。また、Ｕ字型溝を
格子状に形成されたもので説明したが、ストライプ状に
形成されたものであってもよい。また、Ｐチャネル型パ
ワーＭＯＳトランジスタをパワーＭＯＳＦＥＴで説明し
たが、伝導度変調型ＭＯＳＦＥＴであってもよい。この
場合、半導体基板を高濃度Ｎ型とする。また、半導体本
体を半導体基板上にエピタキシャル層を成長させたもの
で説明したが、半導体基板だけで構成してもよい。また
Ｐチャネル型パワーＭＯＳトランジスタは半導体集積回
路の中に含まれたものであってもよい。In the above-described embodiment, the bidirectional diode has been described with the N + / P / N + / P / N + conductivity type PN junction structure. The number of stages may be increased or decreased. The planar structure of the epitaxial layer surface of the cell portion A has been described with reference to FIG. 2 in which the source is a non-circular pattern. However, the present invention is not limited to this. May be formed in an annular pattern. In addition, although the U-shaped grooves are described as being formed in a lattice shape, they may be formed in a stripe shape. Further, the P-channel type power MOS transistor has been described as a power MOSFET, but may be a conductivity modulation type MOSFET. In this case, the semiconductor substrate is a high-concentration N-type. In addition, although the semiconductor body has been described with the epitaxial layer grown on the semiconductor substrate, the semiconductor body may be constituted only by the semiconductor substrate. Further, the P-channel power MOS transistor may be included in a semiconductor integrated circuit.
【００２１】[0021]
【発明の効果】本発明に係わる半導体装置によれば、ポ
リシリコンの双方向性ダイオードをＰ型ポリシリコン層
を高不純物濃度のＮ型ポリシリコン層で挟む導電型のＰ
−Ｎ接合構造としているので、双方向性ダイオードの降
伏電圧波形はハードとなり、動作抵抗が小さくなるため
Ｐチャネル型パワーＭＯＳトランジスタの静電破壊耐量
が向上する。またＮ型ポリシリコン層の不純物濃度が高
いため、層間絶縁膜の製造工程での汚染に対してもＮ型
ポリシリコン層の表面層は影響されることはなく、双方
向性ダイオードの降伏電圧値の製造バラツキ及び製品変
動は小さくなり、信頼性の高い半導体装置を提供でき、
また製造歩留まりを向上させることができる。また本発
明の方法によれば、ポリシリコンの双方向性ダイオード
をＰ型ポリシリコン層を高不純物濃度のＮ型ポリシリコ
ン層で挟む導電型構造として形成するとき、Ｐ型ポリシ
リコン層を形成するためのイオン注入をウェーハ表面を
ポリシリコン膜で被覆後ポリシリコンブロックを形成す
る前に行い、かつ、Ｐ型ポリシリコン層を形成するため
のイオン注入後の熱拡散をベース領域を形成するための
イオン注入後の熱拡散と同時に行い、Ｎ型ポリシリコン
層を形成するためのイオン注入及び熱拡散はコンタクト
ベース領域を形成するためのイオン注入及び熱拡散と同
時に行うことにより、Ｐ型ポリシリコン層を形成するた
めのイオン注入以外に新たに工程を追加することなく、
Ｐ型ポリシリコン層の不純物のドーズ量の制御をセル部
とは独立に行え、かつ、セル部の不純物濃度や拡散深さ
に影響しないように行え、Ｎ型ポリシリコン層はコンタ
クトベース領域と同時に高不純物濃度に形成でき、降伏
電圧波形のハードで降伏電圧値の製造バラツキ及び工程
変動の小さい双方向性ダイオードを有する半導体装置を
安定して製造することができる。また、Ｐ型ポリシリコ
ン層の不純物濃度を制御することによりダイオードの段
数を増減する以外に双方向性ダイオードの降伏電圧値を
任意に設定できるAccording to the semiconductor device of the present invention, a conductive P-type diode in which a polysilicon bidirectional diode is sandwiched between a P-type polysilicon layer and an N-type polysilicon layer having a high impurity concentration.
Due to the -N junction structure, the breakdown voltage waveform of the bidirectional diode becomes hard and the operating resistance is reduced, so that the electrostatic breakdown resistance of the P-channel power MOS transistor is improved. Further, since the impurity concentration of the N-type polysilicon layer is high, the surface layer of the N-type polysilicon layer is not affected by the contamination in the manufacturing process of the interlayer insulating film. Manufacturing variations and product fluctuations are reduced, and highly reliable semiconductor devices can be provided.
Further, the production yield can be improved. Further, according to the method of the present invention, a P-type polysilicon layer is formed when a polysilicon bidirectional diode is formed as a conductive type structure in which a P-type polysilicon layer is sandwiched between N-type polysilicon layers having a high impurity concentration. For covering the wafer surface with a polysilicon film before forming a polysilicon block, and performing thermal diffusion after ion implantation for forming a P-type polysilicon layer to form a base region. The P-type polysilicon layer is formed simultaneously with the thermal diffusion after the ion implantation, and the ion implantation and the thermal diffusion for forming the N-type polysilicon layer are performed simultaneously with the ion implantation and the thermal diffusion for forming the contact base region. Without adding a new process other than ion implantation for forming
The dose of the impurity in the P-type polysilicon layer can be controlled independently of the cell portion and without affecting the impurity concentration and diffusion depth of the cell portion. The N-type polysilicon layer can be formed simultaneously with the contact base region. A semiconductor device having a bidirectional diode which can be formed with a high impurity concentration, has a hard breakdown voltage waveform, and has small manufacturing variations in breakdown voltage value and small process variations can be manufactured stably. Further, by controlling the impurity concentration of the P-type polysilicon layer, the breakdown voltage value of the bidirectional diode can be arbitrarily set in addition to increasing or decreasing the number of diode stages.
【図面の簡単な説明】[Brief description of the drawings]
【図１】 本発明の１実施例であるＰチャネル型パワー
ＭＯＳＦＥＴの要部断面図。FIG. 1 is a cross-sectional view of a main part of a P-channel power MOSFET according to an embodiment of the present invention.
【図２】 図１のＰチャネル型パワーＭＯＳＦＥＴのＵ
字型溝で分離された半導体本体表面の１セル分の平面パ
ターンを示す１実施例のパターン図。FIG. 2 shows a U-channel power MOSFET of FIG.
FIG. 4 is a pattern diagram of one embodiment showing a planar pattern of one cell on the surface of a semiconductor body separated by a V-shaped groove.
【図３】 図１のＰチャネル型パワーＭＯＳＦＥＴの製
造工程（第１〜第４工程）を示す要部断面図FIG. 3 is a cross-sectional view of a principal part showing manufacturing steps (first to fourth steps) of the P-channel power MOSFET of FIG. 1;
【図４】 図１のＰチャネル型パワーＭＯＳＦＥＴの製
造工程（第５〜第８工程）を示す要部断面図FIG. 4 is an essential part cross sectional view showing a manufacturing step (fifth through eighth steps) of the P-channel power MOSFET of FIG. 1;
【図５】 従来のＰチャネル型パワーＭＯＳＦＥＴの要
部断面図。FIG. 5 is a sectional view of a main part of a conventional P-channel type power MOSFET.
２１ 半導体本体 ２２ 半導体基板 ２３ Ｕ字型溝 ２４ 凹部 ２５ エピタキシャル層 ２６ ゲート酸化膜 ２７ ゲート電極 ２８ ドレイン領域 ２９ ベース領域 ２９ａ コンタクトベース領域 ３０ ソース領域 ３１ 層間絶縁膜 ３２ ソース電極 ３３ フィールド酸化膜 ３４ 双方向性ダイオード ３５ Ｎ+ 型ポリシリコン層 ３６ Ｐ型ポリシリコン層 ３７ ゲートパッド ５３ シリコン酸化膜 ５４ 窒化膜 ５５ 初期溝 ５６ 初期凹部 ５７ ＬＯＣＯＳ酸化膜 ５８ ホウ素イオン注入層 ５９ ポリシリコンブロック ６０ シリコン酸化膜 ６１，６２，６３ レジストパターン Reference Signs List 21 semiconductor body 22 semiconductor substrate 23 U-shaped groove 24 concave portion 25 epitaxial layer 26 gate oxide film 27 gate electrode 28 drain region 29 base region 29a contact base region 30 source region 31 interlayer insulating film 32 source electrode 33 field oxide film 34 bidirectional Functional diode 35 N + type polysilicon layer 36 P type polysilicon layer 37 Gate pad 53 Silicon oxide film 54 Nitride film 55 Initial groove 56 Initial recess 57 LOCOS oxide film 58 Boron ion implanted layer 59 Polysilicon block 60 Silicon oxide film 61, 62, 63 resist pattern
Claims (8)
より溝の深さ方向にチャネルが形成されるＰチャネル型
パワーＭＯＳトランジスタと、このＭＯＳトランジスタ
を保護する双方向性ダイオードとを有する半導体装置に
おいて、 前記双方向性ダイオードがＰ型ポリシリコン層とこれを
挟む高濃度Ｎ型ポリシリコン層とのＰ−Ｎ接合構造から
なることを特徴とする半導体装置。1. A semiconductor having a P-channel power MOS transistor in which a channel is formed in a depth direction of a trench by applying a voltage to a gate electrode provided in the trench, and a bidirectional diode for protecting the MOS transistor. In the device, the bidirectional diode has a PN junction structure of a P-type polysilicon layer and a high-concentration N-type polysilicon layer sandwiching the P-type polysilicon layer.
物イオン注入層の形成は前記ＭＯＳトランジスタのため
のイオン注入とは独立に行うとともに、前記Ｐ型不純物
イオン注入層の熱拡散は前記ＭＯＳトランジスタのため
のイオン注入後の熱拡散で行ない、前記高濃度Ｎ型ポリ
シリコン層の形成は前記ＭＯＳトランジスタのためのイ
オン注入およびこの後の熱拡散で行なうことを特徴とす
る請求項１記載の半導体装置の製造方法。2. The method according to claim 1, wherein the formation of the P-type impurity ion implantation layer for the P-type polysilicon layer is performed independently of the ion implantation for the MOS transistor. 2. The method according to claim 1, wherein the high-concentration N-type polysilicon layer is formed by ion implantation for the MOS transistor and thermal diffusion after the ion implantation for the MOS transistor. Of manufacturing a semiconductor device.
Ｐ型およびＮ型ポリシリコン層にパターニングする前の
ポリシリコン膜の状態で行なうとともに、前記Ｐ型不純
物イオン注入層の熱拡散を前記ＭＯＳトランジスタのベ
ース領域形成のためのイオン注入後の熱拡散で行ない、
前記高濃度Ｎ型ポリシリコン層の形成は前記ＭＯＳトラ
ンジスタのコンタクトベース領域形成のためのイオン注
入およびこの後の熱拡散で行なうことを特徴とする請求
項２記載の半導体装置の製造方法。3. The P-type impurity ion-implanted layer is formed in a state of the polysilicon film before being patterned into the P-type and N-type polysilicon layers, and the P-type impurity ion-implanted layer is thermally diffused. Thermal diffusion after ion implantation for forming the base region of the MOS transistor,
3. The method according to claim 2, wherein the high-concentration N-type polysilicon layer is formed by ion implantation for forming a contact base region of the MOS transistor and thereafter by thermal diffusion.
凹部が形成されセル部およびゲートパッド部に共通の低
濃度Ｐ型ドレイン領域を含む半導体本体を具備し、 セル部において、前記半導体本体に含まれ前記ドレイン
領域の表面層で前記Ｕ字型溝に分離された領域に設けた
Ｎ型ベース領域と、このベース領域の表面層に設けた高
濃度Ｐ型ソース領域と、前記Ｕ字型溝の内面に設けたゲ
ート酸化膜と、前記Ｕ字型溝にゲート酸化膜を介して設
けたポリシリコンからなるゲート電極と、このゲート電
極と層間絶縁膜で絶縁し前記ベース領域およびソース領
域に電気的接続したアルミニウムを主金属とするソース
電極とを具備し、 ゲートパッド部において、前記凹部内に設けたフィール
ド酸化膜と、このフィールド酸化膜上に前記層間絶縁膜
を介して設けたアルミニウムを主金属とするゲートパッ
ドと、前記フィールド酸化膜上でこのゲートパッドの周
りに設け、Ｐ型ポリシリコン層とこれを挟む高濃度Ｎ型
ポリシリコン層とからなる双方向性ダイオードとを具備
し、 前記Ｎ型ポリシリコン層のうち、最外周部のＮ型ポリシ
リコン層に前記ソース電極を電気的接続し、最内周部の
Ｎ型ポリシリコン層に前記ゲートパッドを電気的接続し
た半導体装置。4. A semiconductor body having a U-shaped groove in a cell portion and a concave portion formed in a gate pad portion, the semiconductor body including a low-concentration P-type drain region common to the cell portion and the gate pad portion. An N-type base region provided in a region included in the main body and separated by the U-shaped groove in a surface layer of the drain region; a high-concentration P-type source region provided in a surface layer of the base region; A gate oxide film provided on the inner surface of the mold groove; a gate electrode made of polysilicon provided in the U-shaped groove via the gate oxide film; and a base region and a source region insulated from the gate electrode by an interlayer insulating film. A source electrode having aluminum as a main metal electrically connected to the field oxide film; and a gate pad portion including a field oxide film provided in the recess, and the interlayer insulating film formed on the field oxide film. A gate pad made of aluminum as a main metal and a P-type polysilicon layer provided on the field oxide film around the gate pad and a high-concentration N-type polysilicon layer sandwiching the P-type polysilicon layer. A diode; and electrically connecting the source electrode to the outermost N-type polysilicon layer of the N-type polysilicon layer, and electrically connecting the gate pad to the innermost N-type polysilicon layer. Connected semiconductor devices.
たエピタキシャル層であることを特徴とする請求項４記
載の半導体装置。5. The semiconductor device according to claim 4, wherein said semiconductor body is an epitaxial layer formed on a semiconductor substrate.
特徴とする請求項５記載の半導体装置。6. The semiconductor device according to claim 5, wherein said semiconductor substrate is of a high concentration P type.
特徴とする請求項５記載の半導体装置。7. The semiconductor device according to claim 5, wherein said semiconductor substrate is a high-concentration N-type.
表面側に含む半導体本体表面のセル部に初期溝とゲート
パッド部に初期凹部とを形成する第１工程と、 第１工程完了後、前記初期溝および初期凹部の内面にＬ
ＯＣＯＳ酸化膜を形成することより初期溝がＵ字型溝お
よび初期凹部が凹部に形状変形された後、半導体本体表
面をポリシリコン膜で被覆し、このポリシリコン膜にＰ
型イオン注入層を形成して後、このポリシリコン膜をパ
ターニングして前記凹部のＬＯＣＯＳ酸化膜上の外周に
ポリシリコンブロックを形成する第２工程と、 第２工程完了後、前記ＬＯＣＯＳ酸化膜をマスクにＮ型
不純物をイオン注入しその後熱拡散して、前記半導体層
の表面層の前記Ｕ字型溝に分離された領域にＮ型ベース
領域を形成し、前記熱拡散により前記Ｐ型不純物イオン
注入層を熱拡散して前記ポリシリコンブロックをＰ型ポ
リシリコン層とする第３工程と、 第３工程完了後、前記Ｐ型ポリシリコン層の少なくとも
最内周部および最外周部と前記ベース領域表面の一部と
を露出させたレジストパターンを形成し、このレジスト
パターンをマスクに高濃度Ｎ型不純物をイオン注入しそ
の後熱拡散して、前記ベース領域表面層に高濃度Ｎ型コ
ンタクトベース領域と前記Ｐ型ポリシリコン層の少なく
とも最内周部および最外周部に高濃度Ｎ型ポリシリコン
層とを形成し、前記ポリシリコンブロックを双方向性ダ
イオードとする第４工程と、 第４工程完了後、前記ベース領域およびコンタクトベー
ス領域の表面の一部と前記ダイオードの表面を被覆させ
たレジストパターンを形成して後、このレジストパター
ンと前記ＬＯＣＯＳ酸化膜とをマスクに高濃度Ｐ型不純
物をイオン注入しその後熱拡散して、前記ベース領域の
表面層に高濃度Ｐ型ソース領域を形成する第５工程と、 第５工程完了後、前記Ｕ字型溝のＬＯＣＯＳ酸化膜を除
去するとともに前記凹部のＬＯＣＯＳ酸化膜をフィール
ド酸化膜として残す第６工程と、 第６工程完了後、Ｕ字型溝内面を含む露出した半導体本
体表面にゲート酸化膜を形成した後、その上からポリシ
リコン膜で被覆し、このポリシリコン膜をパターニング
して、前記ソース領域表面の一部およびＵ字型溝のポリ
シリコン膜を残してゲート電極を形成する第６工程と、 第６工程完了後、その上から層間絶縁膜で被覆し、この
層間絶縁膜をパターニングして、前記コンタクトベース
領域およびソース領域の表面と前記ポリシリコンブロッ
クの最内周部および最外周部の高濃度Ｎ型ポリシリコン
層の表面とを露出する第７工程と、 第７工程完了後、その上からアルミニウムを主金属とす
る金属膜で被覆し、この金属膜をパターニングして、前
記コンタクトベース領域およびソース領域と前記最外周
部の高濃度Ｎ型ポリシリコン層とに電気的接続するソー
ス電極を形成し、前記最内周部の高濃度Ｎ型ポリシリコ
ン層に電気的接続するゲートパッドを前記フィールド絶
縁膜上のダイオード内側に前記層間絶縁膜を介して形成
する第８工程とを有する半導体装置の製造方法。8. A first step of forming an initial groove in a cell portion on a surface of a semiconductor body including a low-concentration P-type semiconductor layer serving as a drain region on a surface side and an initial concave portion in a gate pad portion, after the first step is completed. L on the inner surfaces of the initial groove and the initial concave portion.
After the formation of the OCOS oxide film, the initial groove is deformed into a U-shaped groove and the initial concave part is deformed into a concave part. Then, the surface of the semiconductor body is covered with a polysilicon film.
Forming a polysilicon block around the LOCOS oxide film in the recess by patterning the polysilicon film after forming the type ion implantation layer; and, after the completion of the second step, removing the LOCOS oxide film. An N-type impurity is ion-implanted into a mask and then thermally diffused to form an N-type base region in a region of the surface layer of the semiconductor layer separated by the U-shaped groove, and the P-type impurity ion is formed by the thermal diffusion. A third step of thermally diffusing the injection layer to make the polysilicon block a P-type polysilicon layer; and, after completing the third step, at least the innermost and outermost portions of the P-type polysilicon layer and the base region. A resist pattern exposing a part of the surface is formed, high-concentration N-type impurities are ion-implanted using the resist pattern as a mask, and then thermally diffused to form a highly-concentrated N-type A fourth step of forming an N-type contact base region and a high-concentration N-type polysilicon layer at least at an innermost portion and an outermost portion of the P-type polysilicon layer, and using the polysilicon block as a bidirectional diode; After the completion of the fourth step, a resist pattern covering a part of the surface of the base region and the contact base region and the surface of the diode is formed, and then, using this resist pattern and the LOCOS oxide film as a mask, A fifth step of ion-implanting a P-type impurity and then thermally diffusing the same to form a high-concentration P-type source region in the surface layer of the base region; and, after completing the fifth step, removing the LOCOS oxide film of the U-shaped groove. A sixth step of removing and leaving the LOCOS oxide film in the concave portion as a field oxide film; and after the completion of the sixth step, an exposed semiconductor body including an inner surface of the U-shaped groove. After a gate oxide film is formed on the surface, it is covered with a polysilicon film from above, and the polysilicon film is patterned to leave a part of the source region surface and a polysilicon film of a U-shaped groove. And after completion of the sixth step, covering with an interlayer insulating film from above, patterning the interlayer insulating film to form a surface of the contact base region and the source region and an innermost portion of the polysilicon block. A seventh step of exposing the surface of the high-concentration N-type polysilicon layer at the peripheral part and the outermost peripheral part; after the completion of the seventh step, a metal film containing aluminum as a main metal is coated on the seventh step; Patterning to form a source electrode electrically connected to the contact base region and the source region and the high-concentration N-type polysilicon layer at the outermost periphery; Method of manufacturing a semiconductor device having an eighth step of a gate pad electrically connected to the N type polysilicon layer is formed through the interlayer insulating film diode inside on the field insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10512699A JP3642466B2 (en) | 1999-04-13 | 1999-04-13 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10512699A JP3642466B2 (en) | 1999-04-13 | 1999-04-13 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000299457A true JP2000299457A (en) | 2000-10-24 |
| JP3642466B2 JP3642466B2 (en) | 2005-04-27 |
Family
ID=14399102
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10512699A Expired - Fee Related JP3642466B2 (en) | 1999-04-13 | 1999-04-13 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3642466B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006100494A (en) * | 2004-09-29 | 2006-04-13 | Nec Electronics Corp | Vertical mosfet |
| JP2006135038A (en) * | 2004-11-04 | 2006-05-25 | Nec Electronics Corp | Semiconductor device and its manufacturing method |
| US7091555B2 (en) | 2003-04-02 | 2006-08-15 | Rohm Co., Ltd. | Semiconductor device for switching |
| US8004067B2 (en) | 2007-03-06 | 2011-08-23 | Kabushiki Kaisha Toshiba | Semiconductor apparatus |
| CN103474426A (en) * | 2013-09-16 | 2013-12-25 | 上海恺创电子有限公司 | Super junction device structure which is high in capacity and resistant to avalanche breakdown |
| JP2016178197A (en) * | 2015-03-19 | 2016-10-06 | 新電元工業株式会社 | Semiconductor device and method of manufacturing the same |
-
1999
- 1999-04-13 JP JP10512699A patent/JP3642466B2/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7091555B2 (en) | 2003-04-02 | 2006-08-15 | Rohm Co., Ltd. | Semiconductor device for switching |
| JP2006100494A (en) * | 2004-09-29 | 2006-04-13 | Nec Electronics Corp | Vertical mosfet |
| JP2006135038A (en) * | 2004-11-04 | 2006-05-25 | Nec Electronics Corp | Semiconductor device and its manufacturing method |
| US8004067B2 (en) | 2007-03-06 | 2011-08-23 | Kabushiki Kaisha Toshiba | Semiconductor apparatus |
| CN103474426A (en) * | 2013-09-16 | 2013-12-25 | 上海恺创电子有限公司 | Super junction device structure which is high in capacity and resistant to avalanche breakdown |
| JP2016178197A (en) * | 2015-03-19 | 2016-10-06 | 新電元工業株式会社 | Semiconductor device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3642466B2 (en) | 2005-04-27 |
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