CN103474426A - Super junction device structure which is high in capacity and resistant to avalanche breakdown - Google Patents
Super junction device structure which is high in capacity and resistant to avalanche breakdown Download PDFInfo
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- CN103474426A CN103474426A CN2013104193691A CN201310419369A CN103474426A CN 103474426 A CN103474426 A CN 103474426A CN 2013104193691 A CN2013104193691 A CN 2013104193691A CN 201310419369 A CN201310419369 A CN 201310419369A CN 103474426 A CN103474426 A CN 103474426A
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Abstract
The invention discloses a super junction device structure which is high in capacity and resistant to avalanche breakdown. The structure comprises a substrate heavy doping region. An epitaxy drifting region is arranged on the substrate heavy doping region; P-type semi-insulating pillar regions are arranged on two sides in the epitaxy drifting region; an ion implantation P-type trap region is formed on the surface of the epitaxy drifting region; N-type polycrystals are formed in the positions, above the interior of a cellular region, on the P-type trap region and are the grid electrode of the device; source regions formed by ion implantation are arranged on two sides of the grid electrode; a P-type semi-insulating pillar region array is arranged in a terminal region at intervals, and field oxides are formed above the side in transition with the cellular region; the N-type polycrystals and P-type polycrystals are formed above the field oxides and are arranged at intervals to form an array, the N-type polycrystals are arranged on the outermost side, close to the cellular region, of the polycrystal array and are connected with the grid electrode of the cellular region through contact holes.
Description
Technical field
The present invention relates to the super-junction device structure in a kind of semiconductor integrated circuit, be specifically related to a kind of structural design and process implementation method of super junction-semiconductor device of shallow/deep groove type.
Background technology
Super junction-semiconductor device is the inherent actuating force of the power-electronic system of development.Especially at aspects such as energy savings, dynamically control, noise minimizings.Product is mainly used in to be controlled the energy between the energy and load, and should have the characteristics that precision is high, speed is fast and low in energy consumption.
But the application of super junction device is limited to its avalanche capability.When super-junction device instantaneous shutoff under the state of opening (grid voltage of product drop to 0 or negative voltage), owing to there being load inductance, play within a certain period of time the effect of afterflow, load current progressively drops to 0 gradually from operating current.Now, because device channel is closed, device source is leaked the poor blocking voltage that is device application of both end voltage.The integration of blocking voltage and load current, be the avalanche capability that device bears at shutdown moment.Because there is grid-leakage coupling capacitance in device, when the coupled voltages value surpasses the device cut-in voltage, device occurs opening in the process of turn-offing again, and causes the actual avalanche energy that bears of device to increase.How the unlatching again of suppression device, be the problem that the present invention studies.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of structure cell and corresponding technical solutions of super junction-semiconductor device of shallow/deep groove type, and it can improve the avalanche breakdown tolerance of super junction product.
For solving the problems of the technologies described above, technical solution of the present invention is: be different from conventional design, integrated design Zener diode in the structure of super junction product.When super-junction device enters shutoff from the state of opening, the grid voltage that leaks the coupling effect generation due to source is raised, can be discharged by the Zener diode in the connection grid source designed in structure, guarantee that device can not enter opening again, and owing to opening again the extra avalanche energy produced, do not put on product, thereby improved the reliability of product.The upper polycrystalline that adopts of device design injects the Zener diode that formation N-type polycrystalline is connected with P type polycrystalline, is technical characterstic of the present invention.On the one hand, (the Zener diode breakdown current is comprised of dissufion current and drift current, and the dissufion current of PN contact has the negative temperature interdependence, and drift current has positive temperature dependency can to utilize the temperature dependency of Zener diode lower.Regulate suitable N, P implantation concentration, can make the temperature dependency of Zener diode drop to minimum), more stable for the protection of product; On the other hand, the N-type polycrystalline is connected with P type polycrystalline, can control the electric pressure needed protection according to the number of series connection.
The accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
The structural representation of Fig. 1 super junction-semiconductor device of the present invention;
Embodiment
The invention discloses a kind of Terminal Design structure of super-junction device, this structure comprises: substrate heavily doped region [01]; Be positioned at the extension drift region [11] on substrate heavily doped region [01]; Be positioned at substrate heavily doped region [01] and be positioned at the semi-insulating post of the P type district [41] of both sides, extension drift region [11]; Form Implantation P type well region [31] on surface, described extension drift region [11]; Described P type well region [31] top in device cellular region [100] is formed with N-type polycrystalline [51], is device grids; The source region [61] that described grid both sides have Implantation to form; The design semi-insulating post of P type at regular intervals district [41] array in termination environment [101], with cellular transition zone side above be formed with an oxygen [21]; Described oxygen [21] top is formed with N-type polycrystalline [51] and P type polycrystalline [52], two kinds of polycrystalline gap arrays, and it is N-type polycrystalline [51] that described polycrystalline array approaches cellular region [100] outermost, by contact hole [71], metal [81], with the grid of cellular region, is connected; The polycrystalline gap array of described N-type polycrystalline [51] and P type polycrystalline [52], be P type polycrystalline [52] by the outside, termination environment [101], by contact hole [71], metal [81], with P type well region [31], is connected.Described termination environment [101] outermost is formed with a cut-off ring, and described cut-off ring consists of N-type heavy doping injection region [61], contact hole [71], N-type polycrystalline [51] field plate and an oxygen [22].
Claims (4)
1. a super-junction device Terminal Design structure, is characterized in that, this structure comprises:
Substrate heavily doped region [01]; Be positioned at the extension drift region [11] on substrate heavily doped region [01]; Be positioned at substrate heavily doped region [01] and be positioned at the semi-insulating post of the P type district [41] of both sides, extension drift region [11]; Form Implantation P type well region [31] on surface, described extension drift region [11]; Described P type well region [31] top in device cellular region [100] is formed with N-type polycrystalline [51], is device grids; The source region [61] that described grid both sides have Implantation to form; The design semi-insulating post of P type at regular intervals district [41] array in termination environment [101], with cellular transition zone side above be formed with an oxygen [21]; Described oxygen [21] top is formed with N-type polycrystalline [51] and P type polycrystalline [52], two kinds of polycrystalline gap arrays, and it is N-type polycrystalline [51] that described polycrystalline array approaches cellular region [100] outermost, by contact hole [71], metal [81], with the grid of cellular region, is connected; The polycrystalline gap array of described N-type polycrystalline [51] and P type polycrystalline [52], be P type polycrystalline [52] by the outside, termination environment [101], by contact hole [71], metal [81], with P type well region [31], is connected.Described termination environment [101] outermost is formed with a cut-off ring, and described cut-off ring consists of N-type heavy doping injection region [61], contact hole [71], N-type polycrystalline [51] field plate and an oxygen [22].
2. the device grids N-type polycrystalline [51] in cellular region according to claim 1 [100] is positioned at silicon body top, i.e. planar device structure in illustrating in the present invention; The structure of the terminal of overvoltage self-protection of the present invention and terminal and cellular transition region, can be applicable to trench gate type device equally.Being the device grids N-type polycrystalline [51] in described cellular region [100], can be plane, can be also groove-shaped.
3. the N-type polycrystalline [51] in termination environment according to claim 1 [101] and the gap array of P type polycrystalline [52] polycrystalline, its N-type polycrystalline [51] and P type polycrystalline [52] polycrystalline are realized by the method for Implantation, can be used mask plate to define respectively the injection zone of N-type polycrystalline [51] and P type polycrystalline [52]; Also can adopt first general notes N-type ion, after define P type Implantation zone by mask plate and carry out P type polycrystalline [52]; After injecting, the requirement of the bulk concentration of N-type polycrystalline [51] and P type polycrystalline [52] is at 1E+17 atom/more than cubic centimetre.
4. the design semi-insulating post of P type at regular intervals district [41] array in termination environment according to claim 1 [101], this number of arrays the number, depend on the applied voltage scope of product, the overall width X5 volt/micron of general array must be greater than applied voltage.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2013104193691A CN103474426A (en) | 2013-09-16 | 2013-09-16 | Super junction device structure which is high in capacity and resistant to avalanche breakdown |
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| CN2013104193691A CN103474426A (en) | 2013-09-16 | 2013-09-16 | Super junction device structure which is high in capacity and resistant to avalanche breakdown |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106601731A (en) * | 2015-10-16 | 2017-04-26 | 比亚迪股份有限公司 | Semiconductor structure having ESD protection structure and manufacturing method thereof |
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| JPH0758330A (en) * | 1993-08-16 | 1995-03-03 | Ricoh Co Ltd | Mos semiconductor device for electric power |
| JPH09232572A (en) * | 1996-02-28 | 1997-09-05 | Nec Yamagata Ltd | Vertical field-effect transistor and method of selection and assembling |
| US5886381A (en) * | 1995-11-10 | 1999-03-23 | Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno | MOS integrated device comprising a gate protection diode |
| JP2000299457A (en) * | 1999-04-13 | 2000-10-24 | Nec Kansai Ltd | Semiconductor device and its manufacture |
| CN101771082A (en) * | 2009-12-30 | 2010-07-07 | 四川长虹电器股份有限公司 | Silicon-based lateral double-diffused metal-oxide semiconductor device on insulating substrate |
| CN102832249A (en) * | 2012-09-11 | 2012-12-19 | 电子科技大学 | Metal oxide semiconductor (MOS) type power semiconductor device |
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2013
- 2013-09-16 CN CN2013104193691A patent/CN103474426A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0758330A (en) * | 1993-08-16 | 1995-03-03 | Ricoh Co Ltd | Mos semiconductor device for electric power |
| US5886381A (en) * | 1995-11-10 | 1999-03-23 | Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno | MOS integrated device comprising a gate protection diode |
| JPH09232572A (en) * | 1996-02-28 | 1997-09-05 | Nec Yamagata Ltd | Vertical field-effect transistor and method of selection and assembling |
| JP2000299457A (en) * | 1999-04-13 | 2000-10-24 | Nec Kansai Ltd | Semiconductor device and its manufacture |
| CN101771082A (en) * | 2009-12-30 | 2010-07-07 | 四川长虹电器股份有限公司 | Silicon-based lateral double-diffused metal-oxide semiconductor device on insulating substrate |
| CN102832249A (en) * | 2012-09-11 | 2012-12-19 | 电子科技大学 | Metal oxide semiconductor (MOS) type power semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106601731A (en) * | 2015-10-16 | 2017-04-26 | 比亚迪股份有限公司 | Semiconductor structure having ESD protection structure and manufacturing method thereof |
| CN106601731B (en) * | 2015-10-16 | 2020-06-23 | 深圳比亚迪微电子有限公司 | Semiconductor structure with ESD protection structure and manufacturing method thereof |
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Application publication date: 20131225 |