CN203179900U - A fast recovery diode FRD chip - Google Patents
A fast recovery diode FRD chip Download PDFInfo
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- CN203179900U CN203179900U CN 201320168067 CN201320168067U CN203179900U CN 203179900 U CN203179900 U CN 203179900U CN 201320168067 CN201320168067 CN 201320168067 CN 201320168067 U CN201320168067 U CN 201320168067U CN 203179900 U CN203179900 U CN 203179900U
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Abstract
The utility model provides a fast recovery diode FRD chip comprising a chip active region and a chip terminal protective region. The chip terminal protective region comprises a P-typed doped region positioned at the bottom of the chip terminal protective region. The P-typed doped region is contacted with a cathode electrode. Besides, the junction depth of the P-typed doped region is less than the junction depth of the N+-typed cathode region of the chip active region. When the FRD is forward conducted, the electron zero injection of the N-base region in the FRD terminal protective region is realized so that the carrier concentration the N-base region in the FRD terminal protective region is greatly reduced. When the FRD is turned off, the extraction speed of the carrier in the entire N-base region is accelerated. That is to say, the turn-off time is shortened so that the turn-off loss is reduced.
Description
Technical field
The utility model relates to a kind of semiconductor device, relates in particular to a kind of fast recovery diode FRD chip.
Background technology
As everyone knows, IGBT in most cases uses under the inductive load condition, needs inverse parallel fast recovery diode (FRD) to use together, and FRD provides the afterflow path under the IGBT on off state, so this FRD also claims fly-wheel diode.
Yet, based on the FRD of P-i-N structure the oscillatory occurences of electric current and voltage appears easily in the reversely restoring process of having no progeny in the pass, particularly in big cut-off current rate of change di/dt, big circuit parasitic inductance, low forward conduction electric current I
FAnd it is particularly evident under the extreme case of low junction temperature.Test shows, adopts thick N-base or thick N buffer layer structure and life-span control technology, can improve the situation of vibration.But the loss in the combination property of FRD (comprising conduction loss and turn-off power loss), soft recovery characteristics and reverse recovery trouble free service zone properties are conflicting, need to optimize compromise.In order to make FRD reach better comprehensive performance, the most frequently used method is the control technology of life-span control technology and anode/cathode injection efficiency.But the life-span is controlled particularly, and the local lifetime control technology can cause reverse leakage current to increase, so the research of the control technology of antianode/negative electrode injection efficiency is increasingly extensive.
At present, there are three kinds of structures to optimize the combination property of FRD by the control of negative electrode injection efficiency substantially.A kind of structure is to adopt the FRD of buffer layer structure (SPT), as shown in Figure 1, be provided with N-type resilient coating 150 ' in the top in N+ cathodic region 130 ', reduced the thickness in N+ cathodic region 130 ', reduced the electron injection efficiency in N+ cathodic region 130 ', because the adding of N-type resilient coating 150 ' has reduced chip thickness, reduced forward conduction voltage drop, but improved very little to reverse soft recovery characteristic aspect.
Another structure is based on an electric charge and extracts (Field Charge Extraction, FCE) FRD, as shown in Figure 2, this structure is on the basis of above-mentioned SPT structure, a plurality of P+ island 140 ' (the N+ cathodic region is set to the alternate structure of N+P+) is set in N+ cathodic region 130 ', by the area ratio of control P+ island 140 ' with N+ cathodic region 130 ', the electron injection efficiency in N+ cathodic region 130 ' when having controlled conducting (control is between 70%-80% usually).When turn-offing, the continuity of electric current is kept to N-base 120 ' injected hole in P+ island 140 ', thereby obtains soft recovery characteristics.But this structure has been lost cathode area, thereby has reduced the negative electrode injection efficiency, has increased forward voltage drop, and under very little restoring current, oscillatory occurences still exists.
Also have a kind of based on the controlled injection in hole, back (Controlled Injection of Backside Holes, FRD CIBH), as shown in Figure 3.P+ island 140 ' is moved in the N-base 120 ' from N+ cathodic region 130 ', kept cathode area, can control the injection efficiency of electronics by the doping content in N+ cathodic region 130 ', simultaneously P+ island 140 ' when turn-offing to N-base 120 ' injected hole, keep the continuity of electric current, thereby obtain soft recovery characteristics, in addition, by near negative electrode place, back many P+ type doped islands being set, avoided NN+ knot place because of high electric field avalanche breakdown to take place, can improve the dynamic robustness (ruggedness) of FRD, improve reverse recovery trouble free service zone properties in other words.But there is following shortcoming in this structure, and the electronics of the N+ cathode portion of below, this FRD chip terminal district injects and makes when turn-offing the extraction time of stored charge longer, and turn-off power loss is bigger.
The utility model content
In view of this, the utility model provides a kind of fast recovery diode FRD chip, when solving above-mentioned shutoff the extraction time of stored charge longer, the technical problem that turn-off power loss is bigger.
In order to solve the problems of the technologies described above, the utility model has adopted following technical scheme:
A kind of fast recovery diode FRD chip; described FRD chip comprises the chip terminal protection zone; described chip terminal protection zone comprises the P type doped region that is positioned at bottom, described chip terminal protection zone; described P type doped region contacts with cathode electrode, and the junction depth of described P type doped region is less than the junction depth in N+ type cathodic region.
Further, the doping content of described P type doped region equates with the doping content in described N+ type cathodic region.
Further, described FRD chip also comprises the N-type resilient coating, and described N-type resilient coating is positioned at the top in described N+ type cathodic region and contacts with described N+ type cathodic region.
Further, described N-type resilient coating extends to described chip terminal protection zone.
Further, described N-type resilient coating perpendicular to the border on the described chip direction be positioned at the terminal protection structure of described chip terminal protection zone perpendicular to the boundary alignment on the described chip direction.
Further, described FRD chip also comprises the chip active area, and described chip active area comprises several P type islands, and described P type island is positioned at the FRD cathode terminal near the position in N+ type cathodic region.
Further, the place, coboundary that is centered close to described N-type resilient coating on described P type island.
Further, described P type island is positioned at described N-type resilient coating inside fully, and the distance between the coboundary of the coboundary on described P type island and described N-type resilient coating is 2-5 μ m.
The utlity model has following beneficial effect:
The FRD chip that the utility model provides, its terminal protection district comprises the P type doped region that is positioned at its bottom, this P type doped region has replaced the N+ type cathodic region in the terminal protection of the prior art district.This P type doped region is when the FRD forward conduction; N-base in the FRD terminal protection district is realized that zero of electronics injects; reduced the carrier concentration in the N-base in the FRD terminal protection district greatly; when FRD turn-offs; charge carrier in the whole N-base extracts speed will be accelerated; reduced turn-off time, thereby reduced turn-off power loss.
Simultaneously, because on the withstand voltage PN junction that occurs in the chip anode tap, therefore P type doped region of the present utility model can not have influence on the blocking voltage ability of FRD; Simultaneously, the forward voltage drop of FRD is main, and effectively the conductivity modulation effect size in the district is relevant with chip, with carrier concentration relation in the N-base of below, FRD terminal protection district not quite, so what influence this P type doped region can not produce to the forward voltage drop of FRD yet.
Description of drawings
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is embodiment more of the present utility model, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the FRD chip structure schematic diagram that adopts SPT;
Fig. 2 is based on the FRD chip structure schematic diagram of FCE;
Fig. 3 is based on the FRD chip structure schematic diagram of CIBH;
Fig. 4 to Fig. 6 is the FRD chip structure schematic diagram of the utility model embodiment.
Embodiment
For the ease of those skilled in the art's understanding, specify the concrete structure of described fast recovery diode FRD chip below in conjunction with accompanying drawing.
A lot of details have been set forth in the following description so that fully understand the utility model, but the utility model can also adopt other to be different from alternate manner described here and implement, those skilled in the art can do similar popularization under the situation of the utility model intension, so the utility model is not subjected to the restriction of following public specific embodiment.
Secondly, the utility model is described in detail in conjunction with schematic diagram, when the utility model embodiment is described in detail in detail; for ease of explanation; the profile of expression chip structure can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of the utility model protection at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
For the FRD chip; especially high pressure FRD chip; the area in terminal protection district can account for the chip gross area 30% or more; and the charge carrier of the N-base part of below, terminal protection district is less to the influence of forward conduction voltage drop; charge carrier when but influence is turn-offed extracts speed, has namely increased switching loss.If manage to reduce this regional carrier concentration, neither can align to conducting voltage influence too greatly, also can reduce switching loss.Based on this inventive concept, the present utility model a kind of fast recovery diode FRD chip.
The structure of the FRD chip that the utility model provides is described in conjunction with Fig. 4.The thickness of this FRD chip can be 60 μ m～750 μ m, and withstand voltage scope can 600V～6500V.
The backing material of making this FRD chip can be conventional semiconductor or wide bandgap semiconductors such as SiC, GaN such as Si.
This FRD chip comprises two zones of chip active area and chip terminal protection zone:
The chip active area of this FRD chip can adopt the structure of chip active area of the prior art, also can adopt following structure.As shown in Figure 4, this chip active area is anode electrode 100, p type anode district 110, N-base 120, N+ type cathodic region 130 and cathode electrode 101 from top to bottom successively, this active area also comprises several P type islands 140, and this P type island 140 is positioned at the inside of N-base 120 and the position in close FRD cathode terminal N+ type cathodic region 130.
Wherein, anode electrode 100 can be metals such as aluminium or copper with cathode electrode 101, and thickness is 3 μ m～50 μ m; The doping content in p type anode district 110 is 6E15/cm
3～3E17/cm
3, junction depth is 5 μ m～15 μ m; The doping content of N-base is 8E12/cm
3～5E14/cm
3, thickness is 40 μ m～700 μ m; The doping content on P type island 140 is 3E15/cm
3～5E16/cm
3, junction depth is 2 μ m～5 μ m, and the width on this P type island 140 is 5 μ m～10 μ m, the ratio of the spacing between the width on P type island 140 and adjacent two the P type islands 140 is 20%～40%, guarantee reverse when withstand voltage P type island 140 can all be exhausted; The doping content in N+ cathodic region is 5E18/cm
3～1E20/cm
3, junction depth is 5 μ m～10 μ m.
This terminal protection district is down to comprise successively to beginning above the FRD structural representation shown in Figure 4 to the back side from the front of chip: dielectric layer 200, terminal protection structure 210 and N+ channel cutoff ring 220, N-base 120, P type doped region 230 and cathode electrode 101.
Wherein, P type doped region 230 is positioned at the bottom of FRD chip terminal protection zone and contacts with the cathode electrode 101 that is positioned at bottom, chip terminal protection zone; the junction depth of this P type doped region 230 is less than the junction depth that is positioned at N+ type cathodic region 130; both differ greatly and are about 3-5 μ m; for example, the junction depth of P type doped region 230 can be 0.5～2 μ m.
The doping content of P type doped region 230 can equate with the doping content in N+ type cathodic region, be 5E18/cm
3～1E20/cm
3, also can be unequal.
The existence of P type doped region 230, the low electronics of chip terminal protection zone lower zone injects when having realized the chip conducting, thereby make the carrier concentration of below, terminal protection district low, therefore the N-base charge carrier extraction speed of chip is faster when turn-offing, and has shortened the turn-off time; Simultaneously, because P type doped region 230 only is positioned at the chip terminal protection zone, so, can not influence forward voltage drop and exert an influence.
In this terminal protection district, dielectric layer 200 has comprised semi-insulating polysilicon layer (Semi-ins μ lating Polysilicon, SIPOS) protective layer and passivation protection layer etc.; The passivation protection layer can be boron-phosphorosilicate glass (BPSG), phosphorosilicate glass (PSB) or Pyrex (BSG) etc.
The FRD chip that above-described embodiment provides does not add control to the injection efficiency of the useful electronics (electronics of the active area part of FRD chip) of the negative electrode of FRD, and identical with common FRD, its electron injection efficiency still is 100%, thereby the forward voltage drop that guarantees FRD does not increase.And the injection efficiency of the useless electronics (electronics of FRD chip terminal protection zone part) of the negative electrode of FRD is controlled; the utility model replaces the N+ type cathodic region 130 that is positioned at FRD chip terminal protection zone of the prior art with P type doped region 230; compare with common FRD; the cathode electronics injection efficiency in terminal protection district drops to 0% from 100%; thereby reduced the carrier concentration of the N-base of below, FRD terminal protection district; improve switching speed, reduced turn-off power loss.
In addition, close this part-structure of FRD cathode electrode below the chip terminal protection zone no longer arranges P type island 140, has reduced reverse leakage current.
In addition, be provided with P type island at the chip active area, can not influence the electron injection efficiency in N+ type cathodic region, namely can not increase the conduction loss of FRD; When FRD turn-offed, the continuity of electric current had been kept to N-base injected hole in P type island, thereby had obtained soft recovery characteristics, had eliminated the electric current of the generation because electric current is discontinuous and the oscillatory occurences of voltage simultaneously.In addition, avoid NN+ knot place because of high electric field avalanche breakdown to take place by a plurality of near the FRD chip back P+ of negative electrode place type doped island, improved reverse recovery trouble free service zone properties.
The above-mentioned FRD chip structure that provides does not arrange the N-type resilient coating, and this FRD chip structure is the break-through structure.
In order to reduce the forward voltage drop of chip, can also above N+ type cathodic region 130, the N-type resilient coating be set.This N-type resilient coating can only be positioned at the chip active area, also can extend to the chip terminal protection zone, and can extend to arbitrary position of chip terminal protection zone, until with the border of chip terminal protection zone.In order to improve the withstand voltage properties of chip better; and further reduce the thickness of chip; reduce the forward conduction voltage drop of chip; the N-type resilient coating preferably extends to the chip terminal protection zone; and the N-type resilient coating protects structure 210 perpendicular to the boundary alignment of chip direction perpendicular to border and the chip terminal of chip direction, and the structural representation of this FRD chip as shown in Figure 5.FRD chip structure shown in Figure 5 and FRD chip structure shown in Figure 4 have just increased one deck resilient coating 150, and other parts are identical with FRD structure shown in Figure 4, for the purpose of concise and to the point, only position and the structural relation of resilient coating 150 are described herein.
This N-type resilient coating 150 is positioned at the top in N+ cathodic region 130 and contact with it.If this N-type resilient coating 150 extends to the chip terminal protection zone, these N-type resilient coating 150 parts that extend to the chip terminal protection zone are positioned at the top of P type doped region 230 and contact with it.N-type resilient coating 150 parts that are positioned at the chip active area equate with the junction depth of the part of the N-type resilient coating 150 that is positioned at the chip terminal protection zone.The doping content of this N-type resilient coating 150 is littler than the doping content in N+ cathodic region 130, is approximately 5E16/cm
3～5E17/cm
3, its junction depth can be 8 μ m～15 μ m.At this moment, on the interface that is centered close to N-type resilient coating 150 and N-base 120 on P type island 140, namely the latter half on P type island is positioned at the inside of N-type resilient coating 150, and the first half on P type island is positioned at the inside of N-base 120, as shown in Figure 5.At this moment, the doping content on P type island 140 can be lower than the doping content of N-type resilient coating 150, thus guarantee reverse when withstand voltage P type island all exhaust, can not exert an influence to withstand voltage.
Certainly, the junction depth of N-type resilient coating 150 can also increase, and all surrounded by N-type resilient coating 150 until whole P type island 140, and the coboundary of N-type resilient coating 150 can also exceed the coboundary 2-5 μ m on P type island 140.Fig. 6 has expressed the structure that N-type resilient coating 150 surrounds whole P type island 140.When whole P type island 140 is all surrounded by N-type resilient coating 150, then need to arrange the doping content on P type island higher, the doping content that is higher than N-type resilient coating 150, but the doping content on P type island can not be too high, and too high doping content is easy to generate the parasitic thyristor effect.
More than fast recovery diode FRD chip provided by the utility model is described in detail, used specific case herein principle of the present utility model and execution mode are set forth, the explanation of above embodiment just is used for helping to understand method of the present utility model and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present utility model, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as restriction of the present utility model.
Claims (8)
1. fast recovery diode FRD chip; described FRD chip comprises the chip terminal protection zone; it is characterized in that; described chip terminal protection zone comprises the P type doped region that is positioned at bottom, described chip terminal protection zone; described P type doped region contacts with cathode electrode, and the junction depth of described P type doped region is less than the junction depth in N+ type cathodic region.
2. FRD chip according to claim 1 is characterized in that, the doping content of described P type doped region equates with the doping content in described N+ type cathodic region.
3. FRD chip according to claim 1 and 2 is characterized in that, described FRD chip also comprises the N-type resilient coating, and described N-type resilient coating is positioned at the top in described N+ type cathodic region and contacts with described N+ type cathodic region.
4. FRD chip according to claim 3 is characterized in that, described N-type resilient coating extends to described chip terminal protection zone.
5. FRD chip according to claim 4 is characterized in that, described N-type resilient coating is perpendicular to the border on the described chip direction and be positioned at the terminal protection structure of described chip terminal protection zone perpendicular to the boundary alignment on the described chip direction.
6. FRD chip according to claim 3 is characterized in that, described FRD chip also comprises the chip active area, and described chip active area comprises several P type islands, and described P type island is positioned at the FRD cathode terminal near the position in N+ type cathodic region.
7. FRD chip according to claim 6 is characterized in that, the place, coboundary that is centered close to described N-type resilient coating on described P type island.
8. FRD chip according to claim 6 is characterized in that, described P type island is positioned at described N-type resilient coating inside fully, and the distance between the coboundary of the coboundary on described P type island and described N-type resilient coating is 2-5 μ m.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320168067 CN203179900U (en) | 2013-04-07 | 2013-04-07 | A fast recovery diode FRD chip |
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|---|---|---|---|
| CN 201320168067 CN203179900U (en) | 2013-04-07 | 2013-04-07 | A fast recovery diode FRD chip |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103208531A (en) * | 2013-04-07 | 2013-07-17 | 株洲南车时代电气股份有限公司 | Fast recovery diode (FRD) chip and manufacturing method for FRD chip |
| CN110648996A (en) * | 2019-09-18 | 2020-01-03 | 上海擎茂微电子科技有限公司 | FRD chip with current sensing function |
| CN112310226A (en) * | 2019-07-29 | 2021-02-02 | 珠海格力电器股份有限公司 | Fast recovery diode and preparation method thereof |
-
2013
- 2013-04-07 CN CN 201320168067 patent/CN203179900U/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103208531A (en) * | 2013-04-07 | 2013-07-17 | 株洲南车时代电气股份有限公司 | Fast recovery diode (FRD) chip and manufacturing method for FRD chip |
| CN103208531B (en) * | 2013-04-07 | 2015-07-15 | 株洲南车时代电气股份有限公司 | Fast recovery diode (FRD) chip and manufacturing method for FRD chip |
| CN112310226A (en) * | 2019-07-29 | 2021-02-02 | 珠海格力电器股份有限公司 | Fast recovery diode and preparation method thereof |
| CN112310226B (en) * | 2019-07-29 | 2022-01-28 | 珠海格力电器股份有限公司 | Fast recovery diode and preparation method thereof |
| CN110648996A (en) * | 2019-09-18 | 2020-01-03 | 上海擎茂微电子科技有限公司 | FRD chip with current sensing function |
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Address after: The age of 412001 in Hunan Province, Zhuzhou Shifeng District Road No. 169 Patentee after: ZHUZHOU CRRC TIMES ELECTRIC Co.,Ltd. Address before: The age of 412001 in Hunan Province, Zhuzhou Shifeng District Road No. 169 Patentee before: ZHUZHOU CSR TIMES ELECTRIC Co.,Ltd. |
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Effective date of registration: 20201013 Address after: 412001 Room 309, floor 3, semiconductor third line office building, Tianxin hi tech park, Shifeng District, Zhuzhou City, Hunan Province Patentee after: Zhuzhou CRRC times Semiconductor Co.,Ltd. Address before: The age of 412001 in Hunan Province, Zhuzhou Shifeng District Road No. 169 Patentee before: ZHUZHOU CRRC TIMES ELECTRIC Co.,Ltd. |
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Granted publication date: 20130904 |