JPH11102917A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance a semiconductor device in withstand voltage through a simple process by a method wherein a groove is previously formed on the surface of a semiconductor layer, the surface of the semiconductor layer with the groove is subjected to an ion implantation and diffusion process once for the formation of an impurity diffusion region whose center base is substantially deep along the groove. SOLUTION: MOSFET cells are formed in a cell region A. The cells are each possessed of a P-type base region 30 doped with P-type impurities such as boron or the like on the surface region of an N-type epitaxial layer 20, and a shallow N<+> -type source region 60 doped with N-type impurities such as arsenic or the like is provided in the P-type base region 30. A groove 220 is provided in the inner surface of the N<+> -type source region 60, and the P-type base region 30 is formed extending as wide as prescribed from the surface of a substrate and the inner surface of the groove 220. The base of the P-type base region 30 is substantially deep.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a structure of a double diffusion type insulated gate field effect transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIGS. 5A to 6G show a conventional n-channel double-spread type MO used as a power device.
FIG. 4 is a process chart showing a general method for manufacturing an SFET (hereinafter, referred to as a D-MOSFET) cell. Hereinafter, a method for manufacturing a conventional D-MOSFET will be described with reference to these drawings.

[0003] As shown in FIG. 5 (a), a single crystal n ⁺ -type silicon substrate 510 doped with phosphorus (P), which is an n-type impurity, is also formed with an n-type impurity by a vapor phase growth method. An n ⁻ -type epitaxial layer 520 doped with a certain concentration of phosphorus is formed.

[0005] Next, as shown in FIG. 5 (b), a resist film 610 is coated on the surface of the n ⁻ -type epitaxial layer 520, and a resist pattern is formed by using a usual photolithography process. Using this resist pattern as an implantation mask, boron (B) ions are implanted into the substrate surface by ion implantation to form an implantation layer 530a indicated by a broken line in the figure in a region corresponding to the center of each cell.

As shown in FIG. 5C, after the implantation, the resist film 610 is removed, and the substrate is annealed at a substrate temperature of 1100 to 1200 ° C. As the implanted ions are activated, they diffuse more deeply and have a depth of about 4 to 4 at the center of each cell.
A deep p-type diffusion region 530 of about 5 μm is formed. Thereafter, the substrate growth surface is thermally oxidized, and a film thickness of about 50 to 1
A gate oxide film 540 of about 00 nm is formed. Further, a low pressure CVD (chemical
A polycrystalline silicon (Si) film 550a having a thickness of about 500 nm is formed by using a vapor deposition method.

As shown in FIG. 5D, the gate electrode pattern 550 is formed by selectively etching the polycrystalline Si 550a using a normal photolithography process. Using this gate electrode pattern 550 as an implantation mask,
B ions are again implanted into the substrate growth surface by using an ion implantation method to form an ion implantation layer 560a.

After the implantation, annealing is performed to form an ion-implanted layer 56.
0a is activated. As shown in FIG. 6E, a p-type diffusion layer 570 having a depth of about 1 to 2 μm is formed around the deep p-type diffusion layer 530 formed in the center of each cell. That is, the p-type diffusion layer 570 and the deep p-type diffusion layer
Form a mold base region. Note that the oxide film layer 580 is a layer formed by oxidizing the substrate growth surface during annealing.

As shown in FIG. 6F, a resist film is coated on the substrate growth surface, and a photolithography process is performed to form a resist pattern 620 at the center of each cell. Using this resist pattern 620 as an implantation mask,
Arsenic (As) ions are shallowly implanted into the substrate growth surface by using an ion implantation method to form an n-type ion implanted layer 590a.

[0009] As shown in FIG. 6 (g), annealing is performed after the implantation to activate the ion implanted layer 590 to a depth of about 0.5.
A μm n ⁺ type source region 590 is formed. Through the above series of steps, the basic structure of the cell of the n-channel D-MOSFET is formed.

[0010]

SUMMARY OF THE INVENTION General D-MOSF
In ET, a deep p-type diffusion region 530 is often formed in the center of the p-type base region of each cell, as shown in FIG. The presence of the deep p-type diffusion region 530 allows the boundary of the depletion layer generated in the n ⁻ -type epitaxial layer 20 to be formed stably and deeply during the operation of the device. Is effective.

However, in order to form the deep p-type diffusion region 530, as shown in FIGS. 5B and 5C, the process of forming the p-type base region shown in FIG. Separately,
An ion implantation process under different conditions and an accompanying annealing process are required. Also, the deep p-type diffusion region 530
In the ion implantation step required for forming the gate electrode, a self-aligned method using a gate pattern as a mask cannot be used as in the case of forming a p-type base region. It must also be formed in a pattern.

As described above, the conventional D-MOSFET having the deep diffusion region at the center of the base region can obtain high withstand voltage characteristics, but involves the burden of new processes such as an ion implantation process and a diffusion process. .

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a novel structure having substantially the same breakdown voltage characteristics as the conventional one and having a small process load, and a method of manufacturing the same.

[0014]

A first feature of the semiconductor device of the present invention is that a semiconductor substrate of a first conductivity type or a second conductivity type, a drain electrode formed on the back surface of the semiconductor substrate, A first conductive type semiconductor layer formed on the main surface of the substrate, a first groove formed on the main surface of the semiconductor layer, and a second conductive layer formed on the periphery including the side and bottom surfaces of the first groove; A first impurity diffusion region of the first conductivity type, and a second impurity of the first conductivity type formed shallower than the trench around the side surface of the first trench.
An impurity diffusion region; a gate insulating film formed so as to cover at least an exposed surface of the first impurity diffusion region sandwiched between an exposed surface of the second impurity diffusion region and an exposed surface of the semiconductor layer; And a gate electrode formed on the insulating film.

According to the first feature of the semiconductor device of the present invention, the first impurity diffusion region of the second conductivity type formed around the first groove and including the side surface and the bottom surface is formed on the surface of the semiconductor layer in advance. One groove is formed, and then ion implantation and diffusion are respectively performed once on the surface including the first groove, whereby the first groove is formed.
According to the shape of the groove, the first impurity diffusion region whose central bottom surface is substantially deep can be formed. With the configuration having the first groove in the center of the first impurity diffusion region in this manner, a semiconductor device having a high withstand voltage characteristic substantially similar to that of the related art can be obtained with a simple process.

If a semiconductor substrate of the first conductivity type is selected, a semiconductor device having a MOSFET structure can be provided. Further, if a substrate of the second conductivity type is selected as the semiconductor substrate, a semiconductor device having an IGBT structure can be provided.

According to a second feature of the semiconductor device of the present invention, in the semiconductor device having the first feature, the first impurity diffusion region, the second impurity diffusion region, a gate insulating film, and a gate electrode are further formed. A plurality of semiconductor cells having a plurality of semiconductor cells, a plurality of second grooves formed so as to surround the outer periphery of the cell region, and a plurality of second grooves formed around the cell including side surfaces and bottom surfaces of the second grooves; And a third impurity diffusion region of the second conductivity type.

According to the second feature of the semiconductor device of the present invention, in the third impurity diffusion region formed around the outside of the cell region, a second groove is previously formed on the surface of the semiconductor layer around the outside of the cell region. Thereafter, it can be formed by performing ion implantation and diffusion on the surface including the second groove.

Since the third impurity diffusion region has a shape that conforms to the shape of the second groove, the bottom surface becomes a substantially deep diffusion region, thereby improving the breakdown voltage characteristics of the device.

A third feature of the semiconductor device of the present invention is that, in the semiconductor device having the second feature, both the first groove and the second groove have the same groove depth.

According to the third feature of the semiconductor device of the present invention, since the first groove and the second groove have the same depth, both grooves can be formed simultaneously in the same step. Also,
By forming each diffusion region around each groove by using the same ion implantation step and annealing step, the depths of the first impurity diffusion region and the third impurity diffusion region can be made uniform.

A first feature of the method for manufacturing a semiconductor device of the present invention is that a step of forming an epitaxial semiconductor layer having a second conductivity type on a semiconductor substrate having a first conductivity type or a second conductivity type; Forming a first groove in a region corresponding to the center of each cell on the surface of the epitaxial semiconductor layer;
Forming a gate insulating film on the surface of the epitaxial semiconductor layer, forming a first conductive film on the gate insulating film, and selectively etching the first conductive film;
Forming a gate electrode, implanting impurity ions contributing to the second conductivity type into the inner surface of the first trench and the surface of the epitaxial semiconductor layer around the inner surface of the first trench, using the gate electrode as an implantation mask; Annealing to form a first impurity diffusion region; forming a resist pattern filling only the first groove;
Using the resist pattern filling only the trench and the gate electrode as an implantation mask, implanting impurity ions contributing to the first conductivity type into the inner surface of the first trench and the surrounding epitaxial semiconductor layer, and then implanting the implanted region. Annealing,
Forming a second impurity diffusion region.

According to the first feature of the method of manufacturing a semiconductor device, the first groove is formed in advance on the surface of the semiconductor layer, and then ion implantation is performed on the surface region including the first groove.
The first impurity diffusion region having a shape along the groove can be formed. In other words, the first impurity diffusion region can be formed by a single ion implantation process, in which the center is substantially deep and the periphery of the center of the second impurity diffusion region where the channel is formed is shallow.

According to a second feature of the method of manufacturing a semiconductor device of the present invention, in the method of manufacturing a semiconductor device having the above-described first feature, the step of forming the first groove is performed simultaneously with the formation of each of the cells. Forming, on the surface of the semiconductor layer around the outer periphery of the cell region, one or more second trenches surrounding the outer periphery of the cell region on a plane, and forming the first impurity diffusion region; Further, when impurity ions contributing to the second conductivity type are implanted into the inner surface of the first trench and the surface of the epitaxial semiconductor layer around the second conductivity type, the second conductivity type is simultaneously implanted into the inner surface of the second trench and the periphery thereof. Implanting impurity ions that contribute to the above.

According to a second feature of the method of manufacturing a semiconductor device, in the step of forming the first groove in the cell region, the second groove is also formed on the surface of the semiconductor layer around the outside of the cell region at the same time. When the impurity ions contributing to the second conductivity type are implanted into the epitaxial semiconductor layer around the first groove, the ions are implanted into the second groove and the periphery thereof at the same time. A third impurity diffusion region having substantially the same depth as the region can be formed.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of a double diffusion type insulated gate field effect transistor according to an embodiment of the present invention will be described with reference to the drawings, taking an n-channel D-MOSFET as an example.

FIG. 1 is a partial sectional view of an apparatus showing the structure of an n-channel D-MOSFET according to the present embodiment. Hereinafter, with reference to FIG.
The structure of the MOSFET will be described. The plane structure is almost the same as the conventional structure. The details will be described later.

As shown in FIG. 1, a conventional D-MOSFE
As in the case of T, an n ⁺ -type Si single crystal substrate 10 doped with an n-type impurity such as phosphorus (P) is used as the substrate. On the back surface of the substrate 10, a drain electrode 150 is formed. On the main surface of the substrate 10, an n ^- type epitaxial layer 20 of Si doped with an n-type impurity such as phosphorus at a low concentration.
Are formed.

In FIG. 1, the left side is the cell region A at the center of the pellet.
Is equivalent to In this cell area A, a plurality of MOSFET cells are formed. Each cell has a p-type base region 30 doped with a p-type impurity such as boron (B) in the surface region of the n ⁻ -type epitaxial layer 20, and further has arsenic (As) or the like in the p-type base region 30. A shallow n ⁺ -type source region 60 doped with the n-type impurity.

A feature of the D-MOSFET according to the present embodiment is that a groove (hereinafter, referred to as a trench) 220 is formed on the inner surface of the n ⁻ type source region 60 and the p type base region 30 is formed on the substrate surface. And that it is formed in a region having a constant width from the inner surface of the trench 220.

Therefore, the bottom shape of the p-type base region 30 is substantially the same as that of the conventional D-MOSFET, and the substantial position of the center bottom of the p-type base region 30 is The conventional MOSF shown in FIG.
It is almost as deep as the p-type diffusion region 530 of ET.

On the surface of the n ^- type epitaxial layer 20,
A gate electrode 90 is formed via a gate oxide film 80 so as to straddle the n ⁺ -type source region of each adjacent cell. An interlayer insulating film 100 is formed on the substrate growth surface,
Contact holes are opened as necessary.

In the contact hole opened in the center of each cell, the n ⁺ type source region 60 and the source electrode 110 are electrically connected. Further, the interlayer insulating film 1 on the rightmost, that is, the outermost gate electrode 90 in FIG.
A contact hole is also formed in the gate electrode 90.
And the gate lead-out electrode 120 is electrically connected.

Similarly to the p-type base region 30, a p-type diffusion layer 40 formed by diffusing boron (B) and a p-type guard are formed in the surface region of the n ^- type epitaxial layer 20 around the cell region A. A ring 50 is formed. A trench is also formed on the surface of n ⁻ type epitaxial layer 20 corresponding to the center of each region. The p-type diffusion layer 40 and the p-type guard ring 50 are formed along the trench, and the bottom is substantially deeper.

A contact hole is formed in the interlayer insulating film on the p-type guard ring 50, and a guard ring electrode 130 is formed through the contact hole.

A channel stopper region 70 of a shallow n-type diffusion layer is formed in the surface region of the n ⁻ -type epitaxial layer 20 along the outer edge of the substrate, and a channel stopper electrode 140 is formed on the channel stopper region 70. .

As described above, each of the p-type base region 30, the p-type diffusion layer 40 and the p-type guard ring 50 has a substantially deep region having substantially the same depth. ^- can be deeply forming the boundary of the depletion layer occurring during -type epitaxial layer 20 has the effect of improving the withstand voltage characteristics of the device.

FIG. 2A is a partial plan view of a device showing a schematic plan structure of the n-channel D-MOSFET according to the present embodiment. FIG. 2 is a sectional view of the apparatus shown in FIG.
(A) corresponds to a partial cross-sectional view taken along a broken line AA ′.

D-MOSFET in this embodiment
Has a plane configuration substantially similar to that of a conventional one, as shown in FIG. The center of the surface of the pellet having a regular quadrilateral or rectangular planar shape is a cell region in which a plurality of cells are formed. On this cell region, the cell region is electrically connected to the n ⁺ type source region of each cell. Source electrode 110
Are formed. In the figure, a quadrilateral small frame indicated by a broken line corresponds to each cell.

Although a passivation film is finally formed on the surface of the pellet, an exposed portion is provided on a part of the source electrode 110 as an electrode pad 110E in order to make electrical contact with the outside of the pellet.

A gate electrode pad (gate lead-out electrode) 120 is formed in a certain area adjacent to the cell area. The gate electrode pad 120 is electrically connected to the gate electrode of each cell, and has an exposed electrode surface for electrical connection with the outside of the pellet. The connection between each pad and the outside of the pellet is performed by bonding or the like.

A frame-shaped guard ring electrode 130 is formed around the cell region and the gate electrode pad 120. A frame-shaped channel stopper electrode 140 is formed on the outer side. Note that only one guard ring is shown here, but the number is appropriately selected according to the device characteristics.

FIG. 2B is a partially enlarged plan view of a cell region surrounded by a broken line a in FIG. 2A. As shown in the figure, each cell has a p-type base region 30 having a quadrilateral planar shape and an n-type source region 60 having a frame-like planar shape inside thereof.

A trench is formed in the center of the cell surrounded by a broken line inside the n-type source region 60.

Hereinafter, referring to FIGS. 3 (a) to 4 (h),
A method for manufacturing a D-MOSFET according to the present embodiment will be described. Here, for comparison with the conventional example, particularly, only the cell region is extracted and shown.

As shown in FIG. 3A, an n ⁻ -type epitaxial layer 20 is formed on a single crystal n ⁺ -type silicon substrate 10 doped with phosphorus (P) by using a vapor growth method. The conditions for the vapor phase growth include, for example, setting the substrate temperature to about 1200 ° C. under reduced pressure, and using monosilane (S
iH ₄ ) gas and phosphine (P
H ₃ ).

As shown in FIG. 3B, a resist film is coated on the n ⁻ -type epitaxial layer 20, and a resist pattern 210 having an opening at the center of each cell is formed by using a usual photolithography process. .

Using the resist pattern 210 as an etching mask, the n ⁻ -type epitaxial layer 20 is etched by reactive ion etching (RIE), and a plane size of about 3 μm × 3 is formed on the surface of the n ⁻ -type epitaxial layer 20.
μm, a trench 2 having a depth of about 2 to 5 μm, preferably 3 μm
20 is formed. The size of the trench may be smaller than the deep p-type diffusion layer formed in the center of the p-type base region in the related art, for example, the depth and the width may be reduced by about 1 μm. Thereafter, the unnecessary resist pattern 210 is removed.

At the same time, the p-type diffusion layer forming region and the guard ring forming region around the cell region have a width of about 3 μm.
It is desirable to form a trench having a depth of about 2 to 5 μm, preferably 3 μm, in a frame shape so as to surround the cell region.

As shown in FIG. 3C, a gate oxide film 80 having a thickness of about 100 nm is formed on the substrate growth surface by using a thermal oxidation method. Further, on the surface of the gate oxide film 80,
A polycrystalline Si film 90a having a thickness of about 500 nm is formed by using a low pressure CVD method.

As shown in FIG. 3D, a resist pattern 230 is formed on the polycrystalline Si film 90a by using a normal photolithography process.

As shown in FIG. 4E, using this as an etching mask, a polycrystalline Si film 90a is formed by RIE.
Is selectively etched to form a gate electrode 90.

Further, using the gate electrode 90 as a mask, boron (B) ions, which are p-type impurities, are implanted into the substrate surface by ion implantation. The implantation conditions are, for example, an ion implantation energy of 40 to 50 keV and a dose of 10 ¹³ to 10 ¹⁴ / cm ² . As shown by the broken line in the figure, the ions are implanted to a substantially constant depth from the ion implantation surface, so that the ion implantation has a deep region in the center of the cell along the shape of the substrate surface, that is, along the shape of the trench. The layer 30a is formed.

Thereafter, a substrate temperature of about 1100 to 1200 ° C.
Then, the ion implantation layer is annealed. As shown in FIG. 4F, the implanted ions are diffused deeper, and each ion implanted layer is recrystallized to activate the implanted ions.
The p-type base region 30 thus formed is formed below the central trench 220 by n
^- depth from type epitaxial layer 20 surface about 5~6μ
m, the depth of the p-type base region 30 around the periphery thereof is about 2 to 3
It is about μm.

As described above, if trench 220 is previously formed on the surface of n ⁻ -type epitaxial layer 20, p-type base region 30 having a deep region at the center can be formed by one ion implantation process. .

If ion implantation and annealing are simultaneously performed on the p-type diffusion layer forming region and the p-type guard ring forming region outside the cell region under the same conditions, substantially, according to the trench shape previously formed in each region, A deep p-type diffusion layer and a p-type guard ring can be formed.

As shown in FIG. 4F, a thin oxide film layer 240 is formed on the surface of the substrate including the gate electrode 90 as the substrate is annealed.

After the oxide layer 240 is removed by etching,
As shown in FIG. 4G, a resist film is formed on the entire surface of the substrate growth surface, and then the resist film is etched back to form a resist pattern 250 leaving the resist film only in the trench 220. Further, arsenic (As) ions, which are n-type impurities, are implanted into the substrate surface using an ion implantation method, using the oxide film and the resist pattern 250 remaining in the gate electrode 90 and the trench 220 at the center of the cell as an implantation mask. The ion implantation conditions at this time are as follows:
For example, the ion implantation energy is about 50 keV, and the dose is about 10 ¹⁵ / cm ² . A shallow ion implantation layer 60a is formed in the surface layer of p-type base region 30 around trench 220.

At the same time, As ions are implanted into each gate electrode 90 formed of polycrystalline Si.
After the implantation step, the resist pattern 250 remaining in the trench 220 is removed.

As shown in FIG.
Anneal the substrate at 0-1000 ° C. for about 10-20 minutes. The ion implantation layer 60a is recrystallized, and the implanted ions are activated. Thus, around the trench 220,
A shallow n ⁺ type source region 60 having a depth of about 0.5 μm is formed.

Further, a thin oxide film layer 260 is formed on the substrate surface in accordance with the annealing step. The As ions implanted and diffused into each gate electrode 90 in the same step have the effect of improving the electrical characteristics of the gate electrode 90.

The subsequent steps will be described with reference to FIG.

Using a CVD method, a film thickness of about 1
A μm interlayer insulating film 100 is formed. Interlayer insulating film 100
It is preferable to use a laminated film composed of a plurality of layers such as a non-doped SiO ₂ film and a phosphosilicate glass (BPSG) film having high flatness.

After a resist pattern is formed using a normal photolithography process, the interlayer insulating film 100 is selectively etched using RIE, and the n ⁺ -type source region 60 and the p-type impurity diffusion layer constituting the MOSFET are formed. 40,
P-type guard ring 50 and channel stopper region 70
A contact hole is formed on each of them.

An alloy film of Al and Si having a thickness of about 3 to 4 μm is formed on the surface of the substrate by a sputtering method. This Al / Si alloy film is etched using a normal photolithography process to form a source electrode 110, a gate extraction electrode 120, a guard ring electrode 130, and a channel stopper electrode 140.

Using a sputtering method, gold (Au) having a thickness of about 50 nm is deposited on the entire back surface of the n ⁺ -type single crystal substrate 10, and this is used as a drain electrode 150.

Thereafter, a passivation film is formed on the substrate surface by using the CVD method, and the wafer as the substrate is scribed for each chip.
A semiconductor device having an SFET structure is completed.

Conventionally, in order to form a p-type base region having a different depth depending on the location, it has been necessary to repeat the ion implantation step and the accompanying steps a plurality of times while having the same conductivity type. According to the method of the present embodiment, by forming a trench in the n ⁻ -type epitaxial layer 20 in advance, the center is substantially deep and the periphery is substantially deep according to the trench shape by a single ion implantation and annealing step. A substantially shallow p-type base region can be formed.

That is, according to this method, a series of additional steps including the patterning of the implantation mask, the ion implantation, the annealing, and the like, which were conventionally required, can be replaced with the patterning and etching of the etching mask. Since the latter process is a simpler process than the ion implantation process and the like, the running cost of the entire process can be reduced.

The present invention has been described in connection with the preferred embodiments. However, the present invention is not limited to these embodiments. For example, as a cell structure, an IGBT (Insulated Gate Bipolar Tr) having a similar double diffusion type insulated gate structure is used.
ansistor). n-channel IGBT
Is formed, the semiconductor substrate 10 may be p-type.

In the above-described embodiment, Si is used as the substrate, but other semiconductor substrates such as gallium arsenide (GaAs) can be used. Various materials can be similarly used for other electrode materials and insulating film materials. Further, in the above-described embodiment, the case of the n-channel is described, but the conductivity type of each region of the device may be all inverted to be the p-channel.

[0072]

As described above, in the semiconductor device of the present invention, a groove is formed on the surface of the semiconductor layer in advance, and then ion implantation and annealing are performed on the surface region including the groove. Regions can be formed.

In order to form a first impurity diffusion region having a deep diffusion region at the center, such as a p-type base region in a MOSFET, while conventionally having the same conductivity type,
It was necessary to repeat the ion implantation step and the accompanying steps a plurality of times. However, according to the configuration of the semiconductor device of the present invention, since the first groove is formed on the surface of the semiconductor layer, after the first groove is formed in advance, ion implantation is performed on the inner surface and the periphery thereof, and the annealing process is further performed. Depending on the groove shape, a p-type base region can be formed that is substantially deep at the center and substantially shallow at the periphery.

That is, according to the present semiconductor device and the method of manufacturing the semiconductor device, a series of additional steps including the patterning of the implantation mask, the ion implantation, and the annealing, which have been conventionally required, are replaced with a simpler step of patterning the resist. It is possible to replace the steps with an etching step and the like, so that the steps required for manufacturing the semiconductor device can be further simplified, and the cost of the entire step can be reduced.

[Brief description of the drawings]

FIG. 1 shows a D-MOSFET according to an embodiment of the present invention.
FIG.

FIG. 2 shows a D-MOSFET according to an embodiment of the present invention.
It is a schematic plan view of.

FIG. 3 shows a D-MOSFET according to an embodiment of the present invention.
FIG. 7 is a partial cross-sectional view of the apparatus in each step for explaining the manufacturing process.

FIG. 4 shows a D-MOSFET according to an embodiment of the present invention.
FIG. 7 is a partial cross-sectional view of the apparatus in each step for explaining the manufacturing process.

FIG. 5 is a partial cross-sectional view of the device in each step for explaining a conventional D-MOSFET manufacturing process.

FIG. 6 is a partial cross-sectional view of the device in each process for explaining a conventional manufacturing process of a D-MOSFET.

[Explanation of symbols]

10 · · · n ⁺ -type single-crystal Si substrate 20 · · · n ^- -type epitaxial layer 30 · · · p-type base region 40 · · · p-type impurity diffusion layer 50 · · · p-type guard ring 60 · · · n Mold source region 70 channel stopper region 80 gate oxide film 90 gate electrode 100 interlayer insulating film 110 source electrode 120 gate extraction electrode 130 guard ring electrode 140: channel stopper electrode 150: drain electrode

Claims (6)

[Claims] A semiconductor substrate of a first conductivity type or a second conductivity type; a drain electrode formed on a back surface of the semiconductor substrate; and a semiconductor layer of a first conductivity type formed on a main surface of the semiconductor substrate. A first groove formed on a main surface of the semiconductor layer; a first impurity diffusion region of a second conductivity type formed around a side surface and a bottom surface of the first groove; and a periphery of a side surface of the first groove A second impurity diffusion region of a first conductivity type formed shallower than the trench; and an exposure of the first impurity diffusion region sandwiched between an exposed surface of the second impurity diffusion region and an exposed surface of the semiconductor layer. A semiconductor device comprising: a gate insulating film formed so as to cover at least a surface; and a gate electrode formed on the gate insulating film. 2. A cell region in which a plurality of semiconductor cells each having the first impurity diffusion region, the second impurity diffusion region, a gate insulating film and a gate electrode are formed, and the cell region is formed on a surface of the semiconductor layer. A second groove formed so as to surround an outer periphery of the second groove, and a third impurity diffusion region of a second conductivity type formed around the second groove and including a side surface and a bottom surface of the second groove. 2. The semiconductor device according to 1. 3. The semiconductor device according to claim 1, wherein said first groove and said second groove both have the same groove depth. 4. The semiconductor device according to claim 1, wherein the first groove and the second groove are 2 μm.
4. The semiconductor device according to claim 1, wherein the semiconductor device has a groove depth of about 5 [mu] m. 5. A step of forming an epitaxial semiconductor layer having a first conductivity type on a semiconductor substrate having a first conductivity type or a second conductivity type, and a region corresponding to the center of each cell on the surface of the epitaxial semiconductor layer. Forming a first groove on the surface of the epitaxial semiconductor layer, forming a gate insulating film on the surface of the epitaxial semiconductor layer, forming a first conductive film on the gate insulating film, and selectively forming the first conductive film. Forming a gate electrode, implanting impurity ions contributing to the second conductivity type into the inner surface of the first trench and the surface of the epitaxial semiconductor layer around the inner surface of the first trench using the gate electrode as an implantation mask; Then, annealing the implanted region to form a first impurity diffusion region; forming a resist pattern that fills only the first groove; Using the resist pattern filling the gap and the gate electrode as an implantation mask, impurity ions contributing to a first conductivity type are implanted into the surface of the epitaxial semiconductor layer around the first trench, and then the implanted region is annealed, Forming a two impurity diffusion region. 6. The step of forming the first groove includes, simultaneously, forming one or more second grooves surrounding the outer periphery of the cell region on a plane on the surface of the semiconductor layer around the outer periphery of the cell region. A step of forming the first impurity diffusion region, further comprising: implanting impurity ions contributing to a second conductivity type into the inner surface of the first trench and the surface of the epitaxial semiconductor layer around the first trench. And simultaneously implanting impurity ions contributing to the second conductivity type into and around the inner surface of the second groove.