JP3257225B2 - Planar type semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planar semiconductor device having a high breakdown voltage by providing a guard ring structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art A guard ring structure or a field plate structure is often used to widen a depletion layer exposed on the surface of a planar type semiconductor element toward an edge of a semiconductor substrate to reduce an electric field and improve a breakdown voltage. Are known. FIG. 2 shows an edge structure of a high-breakdown-voltage diode having a guard ring structure. A p-type anode region 2 is formed on an n-type silicon substrate 1 by impurity diffusion from the surface, and a p-type guard ring region having the same depth is formed. 3 are formed. If the guard ring region 3 is shallow, the breakdown voltage becomes unstable due to the influence of the external world such as movable ions accumulating on the surface of the oxide film 4 on the guard ring region. Similarly, the impurity concentration was increased and the depth was increased. An n ⁺ edge region 11 having the same potential as that of the cathode electrode is formed at the edge of the substrate, the anode electrode 5 is formed in the p anode region 2 at the opening of the oxide film 4, and the depletion layer is extended in the edge region 11. Are in contact with each other.

[0003] In the diode shown in FIG. 3, a field plate structure is used in combination with a guard ring structure in order to reduce the influence of the outside world. The electric field is connected to the external electric field.

[0004]

In view of the progress of semiconductor devices and the progress of required characteristics, it is necessary to increase the speed of semiconductor devices. In order to achieve higher speed, for example, in the diodes shown in FIGS. 2 and 3, it is necessary to lower the impurity concentration of the p anode region 2 and to reduce the diffusion depth. Simply lowering the impurity concentration and decreasing the diffusion depth lowers the reverse breakdown voltage of the PN junction. At the same time, since the impurity concentration of the guard ring region 3 decreases and the diffusion depth decreases, the reverse breakdown voltage becomes unstable due to a strong influence of the external environment and a change in the carrier concentration of the surface layer.
Further, when the impurity concentration of the guard ring region 3 becomes low, the resistance between the guard ring region 3 and the field plate electrode 6 becomes large, and the effect of the field plate to stabilize the electric field becomes insufficient.

[0005] In the diode of FIG.
When a reverse bias is applied to the PN junction between the regions 2, a depletion layer is formed on the n substrate 1 as shown by a dotted line 71 in FIG.
Although extending along the guard ring region 3, when the impurity concentration of the p region 2 is low, the peripheral portion formed by lateral diffusion has a particularly low impurity concentration.
It spreads considerably inside the region 2 and, when it reaches the anode electrode 5, punch-through occurs. To prevent this punch-through from occurring, the oxide film 4 covering the peripheral portion of the surface of the p region 2 is expanded to a width of about 10 μm, and the depletion layer end face 7 is formed.
2 does not reach the contact surface of the anode electrode 5. However, this causes the contact area of the anode electrode 5 to be narrowed, thus increasing the dimensions of the element.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and reduce the impurity concentration in order to increase the speed of the second conductivity type region formed in the semiconductor layer of the first conductivity type. It is an object of the present invention to provide a planar semiconductor element which can be prevented from lowering and a method for manufacturing the same.

[0007]

SUMMARY OF THE INVENTION To achieve the above object, the present invention provides a planar electrode in which one of the main electrodes contacts a second conductivity type region formed in a surface layer of a semiconductor layer of a first conductivity type. In the type semiconductor device, it is assumed that a high impurity concentration region is provided at a peripheral portion of the second conductivity type region, and a peripheral portion of the main electrode is in contact with a surface of a portion inside the high impurity concentration region. On the surface layer of the semiconductor layer of the first conductivity type, a guard ring region of the second conductivity type is formed simultaneously with the second conductivity type region and surrounds the region, and the surface layer of the guard ring region also has a high impurity. It is effective that the density region is provided. In addition, the method of manufacturing such a semiconductor device of the present invention includes forming a second conductivity type region on a surface layer of a semiconductor layer of a first conductivity type, covering the surface with an insulating glass layer containing a doping element, and performing a heat treatment. To form a high impurity concentration region by diffusing the doping element. Alternatively, a second conductivity type region and a guard ring region of the second conductivity type surrounding the second conductivity type region are simultaneously formed on the surface layer of the semiconductor layer of the first conductivity type, and then the surface is covered with an insulating glass layer containing a doping element, followed by heat treatment. Therefore, it is preferable to simultaneously form the second conductivity type high impurity concentration regions on the surface layer of each region.

[0008]

A high impurity concentration region is provided on the periphery of the second conductivity type region forming a PN junction with the first conductivity type semiconductor layer, and the main electrode is brought into contact with the inner surface of the high impurity concentration region. Even if the depletion layer spreads from the PN junction at the periphery of the shaped region, the spread is suppressed in the high impurity concentration region.
No punch through. If a high impurity concentration is also formed in the guard ring region at the same time, the guard ring region is less affected by the external environment.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings in which the same parts as those in FIGS. 2, 3 and 4 are denoted by the same reference numerals. FIG. 1 shows a planar type diode according to one embodiment of the present invention, in which boron is doped into a surface layer at a peripheral portion of a p anode region 2 and a central portion of a guard ring region 3 formed on a surface layer of an n substrate 1. P ⁺ region 8 is formed.
The anode electrode 5 and the field plate electrode 6 are in contact with the region. Further, the potential fixing electrode 12
A boron-doped p ⁺ region 8 is also formed at the portion where the contact is made.

Such an element is manufactured by the steps shown in FIGS. 5 (a) to 5 (f). First, an oxide film 4 is formed on the n-type silicon substrate 1 by thermal oxidation [FIG. 2A], a window is opened in an impurity diffusion region by photolithography [FIG. 2B], and impurities such as boron are ion-implanted. Low impurity concentration and shallow p
An anode region 2 and a p-guard ring region 3 are formed [FIG. Next, a boron glass BSG film 9 is formed on the surface.
Is deposited to a thickness of 1 μm (FIG. 4D), and a diffusion process at 1000 ° C. or higher is performed to diffuse the boron to the surface portion again using the window of the oxide film 4 to form the p ⁺ region 8. Form [same figure
(e)]. Thereafter, contact holes are formed in the insulating BSG film 9 and the oxide film 4 by photolithography, an electrode layer is formed by vapor deposition of metal, and then divided into an anode electrode 5 and a field plate electrode 6 by photolithography [FIG. (f)]. Although not shown, an n ⁺ layer is formed on the back surface side, and a cathode electrode is deposited.

In this element, p ⁺ region 8 exists in the peripheral surface layer of anode region 2 due to boron diffusion from BSG film 9, so that p ⁺ region 8 is formed from PN junction with n substrate 1.
The depletion layer extending inside does not reach the anode electrode 5 in contact with the p ⁺ region 8 and does not cause punch-through. Therefore, the anode electrode 5 can be extended to near the surface exposed portion of the PN junction, so that the effective area of the anode region 2 is increased.

In this embodiment, the PN junction is formed by the n substrate and the p region 2 formed in the surface layer.
Obviously, the present invention can be applied to a case where an n region is formed in a surface layer using a p substrate. In this case, a phosphorus glass (PSG) film is used instead of the BSG film.

[0013]

According to the present invention, a mask used to previously form the second conductivity type region around the periphery of the second conductivity type region for the PN junction formed in the first conductivity type region. By providing a high impurity concentration region that can be formed again by using
Even if the impurity concentration of the second conductivity type region is low and the depth is shallow, the spread of the depletion layer to that region can be suppressed, and punch-through can be prevented. In addition, a high impurity concentration region that can be simultaneously formed in the surface layer of the guard ring region can also reduce the influence of the external environment on the region surface layer.
As a result, a highly reliable, high-speed, high-withstand-voltage diode is completed.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of a planar diode according to an embodiment of the present invention.

FIG. 2 is a sectional view of a main part of a conventional planar diode having a guard ring structure.

FIG. 3 is a sectional view of a main part of a conventional planar diode having a field plate structure.

FIG. 4 is a cross-sectional view showing a depletion layer in a conventional planar diode.

FIGS. 5A to 5D show the manufacturing process of the diode of FIG.
Sectional view shown in order of (f)

[Explanation of symbols]

Reference Signs List 1 n-type silicon substrate 2 p anode region 3 p guard ring region 4 oxide film 5 anode electrode 6 field plate electrode 8 p ⁺ boron-doped region 9 BSG film

Claims (4)

(57) [Claims] 1. A semiconductor device of a first conductivity type, wherein one of the main electrodes contacts a second conductivity type region formed on a surface layer of a semiconductor layer of the first conductivity type, wherein a high impurity concentration region is provided at a peripheral portion of the second conductivity type region. And a peripheral portion of the main electrode is in contact with a surface of a portion inside the high impurity concentration region. 2. A guard ring region of a second conductivity type formed simultaneously with and surrounding a second conductivity type region in a surface layer of a semiconductor layer of a first conductivity type, and a surface of the guard ring region. 2. The planar semiconductor device according to claim 1, wherein a high impurity concentration region is also provided in the layer. 3. A second conductivity type region is formed on a surface layer of a semiconductor layer of a first conductivity type, and the surface is covered with an insulating glass layer containing a doping element. 3. The method according to claim 1, wherein a conductive type high impurity concentration region is formed. 4. A second conductivity type region and a second conductivity type guard ring region surrounding the second conductivity type region are simultaneously formed on the surface layer of the semiconductor layer of the first conductivity type, and the surface is formed of an insulating glass layer containing a doping element. 3. A high impurity concentration region of the second conductivity type is simultaneously formed on the surface layer of each region by covering and heat treatment.
A manufacturing method of the planar type semiconductor device according to the above.