JPH04177840A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To make a rapid operation possible by installing, in a part of an epitaxial layer which is just below an insulated film which passes through a base layer and an emitter layer, a high-density layer which has the same conductivity as the epitaxial layer. CONSTITUTION:On a P-type silicon substrate 1, an N<+> type buried layer 2 and an N-type epitaxial layer 3 are formed. In the N-type epitaxial layer 3, a P-type base layer 5 and an N<+> type emitter layer 6 are formed. SiO2 films 8 and 9 are so formed as to pass through the N<+> type emitter layer 6 and P-type base layer 5. A high density N<+> type layer 10 is formed in a part of the N-type epitaxial layer 3 which is just below the SiO2 film 8. Since the N<+> type layer 10 exists in a place near and under the P-type base layer 5, a base force-out effect is prevented from occuring and thus a rapid transistor is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a bipolar transistor structure with good high frequency characteristics.

[Conventional technology]

An example of a conventional bipolar transistor is shown in FIG.

In FIG. 4, an N+ type buried layer 2 is formed on a P type silicon substrate 1.
An N-type epitaxial layer 3 is formed, and an oxide film 4 is formed.
The elements are separated in the lateral direction. 5 is a P-type base layer, 6 is an N+-type emitter layer, and 11 is an N+-type extraction layer for drawing out the collector from the buried layer, and these are connected to the base electrode 14, emitter electrode 13, and collector electrode 12 through windows, respectively. has been done.

The above parts are basic, but in this example, in order to increase the speed, a Si○2 film 8, which penetrates the P type base layer 5 and the N+ type emitter layer 6, is installed inside the emitter opening except for the periphery. 9
exists.

[Problem to be solved by the invention]

However, in the structure of the above-mentioned bipolar transistor, the emitter area becomes small, so the current density becomes high, the base extrusion effect is likely to occur, and high speed is limited.

[Means to solve the problem]

The semiconductor integrated circuit of the present invention includes an epitaxial layer of opposite conductivity type formed on a semiconductor substrate of -conductivity type, a base layer of one conductivity type formed on this epitaxial layer, and an emitter of opposite conductivity type formed on this base layer. and an insulating layer formed penetrating the emitter layer and the base layer, in which a highly concentrated reverse conductivity type impurity layer is provided in the epitaxial layer directly below the insulating layer. be.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a sectional view of a first embodiment of the invention.

In FIG. 1, an N+ type buried layer 2 and an N type epitaxial layer 3 are formed on a P type silicon substrate 1, and a P type substitute layer 5 and an N+ type epitaxial layer 3 are formed on this N type epitaxial layer 3. An emitter layer 6 is formed. SiO2 films 8 and 9 are formed through this N+ type emitter layer 6 and P type substitute layer 5, and furthermore, the N type epitaxial layer 3 directly under this SiO2 film 8 has a high concentration. An N+ type layer 10 is formed. In FIG. 1, 4 is an oxide film and 7 is an N
11 is an N+ type extraction layer, 12 is a collector electrode, 13 is an emitter electrode, and 14 is a base electrode. The concentration of the P-type substitute layer 5 at this time is 1018 cm-3
, the depth is Q, 21 tm, the depth of the N+ type emitter layer 6 is 0.05 μm, and the bottom of the 5i02 film 8 is 0.13 μm deep. And the concentration of the epitaxial layer is I x 101
6 cm −3 and the depth is 0.6 μm.

Next, an example of the manufacturing process of the emitter section will be explained with reference to FIG.

First, as shown in FIG. 2(a), an N+ type buried layer 2, an N type epitaxial layer 3, an oxide film 4,
After forming the P-type substitute layer 5, SiN with a thickness of 0.1 μm is applied to the entire surface.
5 deposits on 1 membrane. Next, the 5-oxide film 4 on the SiN film 1 is etched to form an emitter opening, and a 0.25 μm N-type polysilicon layer 7 is grown.

Next, as shown in FIG. 2(b), the N+ type polysilicon layer 7 and the epitaxial layer are etched deeper than the bottom of the P type substituent layer 5 by anisotropic dry etching, and phosphorus is further etched at a dose of 150 keV. IX 1013an-
By implanting ions under the conditions of 2, the concentration is 1018c.
An N+ type layer 10 of about m-3 is formed.

Next, as shown in FIG. 2(c), a 5i02 film 8 is grown by heat treatment in an oxidizing atmosphere, and at the same time an N+ type emitter layer 6 is grown by impurity diffusion from the N+ type polysilicon layer 7.
form.

Next, as shown in FIG. 2(d), a 5i02 film 9 is grown on the entire surface by CVD method so that the upper part is almost flat.
Next, as shown in FIG. 2(e), S i 02 M8
, etch back 9. The following is processed according to the conventional method.
Complete the transistor shown in the figure.

In FIG. 1, an N+ type layer 1 is located near the bottom of the P type layer 5.
The presence of 0 suppresses the base extrusion effect, making it possible to improve the high-speed performance of the transistor by several tens of percent.

FIG. 3 is a sectional view of a semiconductor chip for explaining a second embodiment of the present invention. In this second embodiment, another N+ type layer 16 is added to the entire surface immediately below the emitter opening.

In order to provide this N+ type layer 16, for example, as shown in FIG.
Before forming the N+ type polysilicon layer 7 in
As shown in Figure (a), phosphorus ions are implanted at an energy of about 200 keV.

As shown in FIG. 3(b) below, FIGS. 2(a) to (e)
A transistor is formed in the same process as described above.

According to the embodiment of genuine leather 2, there is an advantage that the base extrusion effect can be further suppressed by adding the N+ type layer 16.

〔Effect of the invention〕

As explained above, the present invention provides a bipolar transistor having an epitaxial layer, which includes an insulating film that penetrates the base layer and the emitter layer inside the emitter opening except for the periphery thereof, and an epitaxial layer in the epitaxial layer immediately below the insulating film. By providing a highly concentrated layer of the same conductivity type as
Since the base dozing effect can be suppressed, there is an effect that a semiconductor integrated circuit capable of higher speed operation can be obtained.

[Brief explanation of drawings]

FIG. 1 is a sectional view of the first embodiment of the present invention, and FIG. 2 is a sectional view of the first embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the manufacturing process of the second embodiment of the present invention, and FIG. 4 is a cross-sectional view of an example of a conventional semiconductor integrated circuit. 1...P type silicon substrate, 2...N+ type buried layer, 3
... N type epitaxial layer, 5... P type base layer,
6...N+ type emitter layer, 8,9...5i02 film,
10.16...N+ type layer.

Claims (1)

[Claims] an epitaxial layer of opposite conductivity type formed on a semiconductor substrate of one conductivity type; a base layer of one conductivity type formed on this epitaxial layer; an emitter layer of opposite conductivity type formed on this base layer; In a semiconductor integrated circuit having a base layer and an insulating layer formed through the base layer,
A semiconductor integrated circuit characterized in that a highly concentrated impurity layer of opposite conductivity type is provided in the epitaxial layer directly below the insulating layer.