JPH05283624A - Bimos semiconductor device - Google Patents

Abstract

PURPOSE:To improve performance by reducing a collector series resistance of a bipolar part and also to improve reliability by preventing punch-through and soft error of an MOS part. CONSTITUTION:A thick buried layer 15 is formed in a bipolar part 12 in an interface between an Si substrate 11 and an epitaxial layer 21, and a thin buried layer 33 is formed in an NMOS part 14. A potential barrier is formed by an existance of a buried layer 33 and soft error resistance of an NMOS part 14 is high; however, since the buried layer 33 is thin, a punch through is hard to be generated between the buried layer 33 and a diffusion layer 37 even if the epitaxial layer 21 is thin. Meanwhile, the buried layer 15 of the bipolar part 12 can be made thick and the epitaxial layer 21 can be made thin as mentioned above. Therefore, a collector series resistance can be reduced by making the buried layer 15 a collector.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a bipolar portion and a MOS.
And a BiMOS semiconductor device having a section.

[0002]

2. Description of the Related Art FIG. 3 shows a first conventional example of a BiCMOS-SRAM which is a kind of BiMOS semiconductor device. In the first conventional example, of the surface of the P-type Si substrate 11, the bipolar part 12, the PMOS part 13 and the NMO are formed.
N ⁺ type, P ⁺ type and N ⁺ type buried layers 15 to 17 are selectively formed in each of the S portions 14.

An N type epitaxial layer 21 having a resistivity of about 1 Ωcm and a thickness of about 1.0 to 1.5 μm is laminated on the Si substrate 11, and the Si substrate 11 and the epitaxial layer 21 are composed of the N type epitaxial layer 21. The Si base 22 is configured.
Then, in the epitaxial layer 21, the NMOS portion 14
A P-type well 23 is formed in the.

Bipolar section 12, PMOS section 13 and N
The MOS portion 14 is surrounded by the SiO ₂ film 24 for element isolation on the surface of the epitaxial layer 21, and the bipolar portion 12 penetrates the epitaxial layer 21 from the SiO ₂ film 24 to reach the Si substrate 11. It is surrounded by a P-type diffusion layer 25 for separation.

FIG. 4 shows a second conventional example of a BiCMOS-SRAM. In this second conventional example, the PMOS section 13
And the NMOS section 14 in the P ⁺ type and N ⁺ type buried layers 1
The structure is substantially the same as that of the first conventional example shown in FIG. 3, except that 6 and 17 are not formed.

[0006]

However, when the N ⁺ type buried layer 17 is formed in the NMOS section 14 as in the first conventional example shown in FIG. 3, the diffusion coefficient is small, for example, Sb.
Even if the buried layer 17 is formed by using
7 has a high impurity concentration, the buried layer 17 has a thickness of 0.5 μm.
A degree of upward diffusion occurs.

Moreover, in the NMOS portion 14 which constitutes the memory cell of the SRAM, the polycrystalline Si film (not shown) which is the gate electrode and the diffusion layer (37 in FIG. 1) which is the source / drain are connected by the buried contact. I often do
In this buried contact portion, the epitaxial layer 21 has a thickness of 0.
Only 1 to 0.2 μm can be dug.

On the other hand, Bi whose design rule is 0.8 μm or later
In the CMOS-SRAM, in order to improve the performance of the bipolar part 12, the thin epitaxial layer 21 of 1.5 μm or less is required as described above. Therefore, NMOS
The distance between the source / drain of the portion 14 and the buried layer 17 is short, and punch-through easily occurs between them.

On the other hand, if the N ⁺ type buried layer 17 is not formed in the NMOS portion 14 as in the second conventional example shown in FIG. 4, the punch through described above does not occur. However, if the buried layer 17 is not formed, the electrons of the electron-hole pairs generated in the Si substrate 11 due to the α rays reach the storage node of the memory cell, so that the soft error resistance is low.

That is, in both the first and second conventional examples shown in FIGS. 3 and 4, the epitaxial layer 21 is thinned to improve the performance of the bipolar portion 12, while the NMOS portion 14 is
It was not possible to prevent punch through and improve soft error resistance to improve reliability.

[0011]

According to another aspect of the present invention, there is provided a BiMOS semiconductor device in which a semiconductor substrate 22 is composed of a first semiconductor layer 11 and a second semiconductor layer 21 laminated on the first semiconductor layer 11. The diffusion layers 15 and 33 are formed at the interfaces between the first and second semiconductor layers 11 and 21, and the diffusion layers 15 and 33 are relatively thick in the bipolar portion 12. , The MOS portions 13 and 14 are relatively thin.

According to another aspect of the BiMOS semiconductor device of the present invention, the impurity concentration of the diffusion layers 15 and 33 is the bipolar portion 1.
It is lower than that in the MOS parts 13 and 14 than 2.

[0013]

In the BiMOS semiconductor device according to the first aspect, the MOS
First and second semiconductor layers 11, 2 in parts 13, 14
Since the diffusion layer 33 is formed at the interface between the ones, a potential barrier is formed and the soft error resistance is high.
Since the thickness of the diffusion layer 33 is relatively thin, even if the thickness of the second semiconductor layer 21 is thin, the diffusion layer 33 and the source.
Punch through does not easily occur between the drain 37.

On the other hand, the diffusion layer 15 of the bipolar portion 12 is relatively thick, and as described above, the second semiconductor layer 2 is formed.
Since the thickness of 1 can be made thin, this diffusion layer 15
Is a buried collector, the collector series resistance can be reduced.

In the BiMOS semiconductor device according to the second aspect, the impurity concentration of the diffusion layers 15 and 33 is lower in the MOS portions 13 and 14 than in the bipolar portion 12, but the impurity concentration of the diffusion layer 33 in the MOS portions 13 and 14 is as described above. Is low,
The diffusion of the diffusion layer 33 in the MOS portions 13 and 14 is small.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention applied to a BiCMOS-SRAM will be described below with reference to FIGS.
The same components as those of the first and second conventional examples shown in FIGS. 3 and 4 are designated by the same reference numerals.

FIG. 1 shows this embodiment, and FIG. 2 shows
The manufacturing process is shown. In order to manufacture this embodiment, as shown in FIG. 2A, a SiO ₂ film 26 having a film thickness of about 0.3 to 0.5 μm is first grown on a P-type Si substrate 11 and embedded. Openings 27 in a pattern corresponding to layer 15
Is formed on the SiO ₂ film 26. Then, through the opening 27, 1 × 10 ¹⁵ to 1 × is obtained by solid layer diffusion or ion implantation.
Sb31 was added to the Si substrate 11 at a dose of about 10 ¹⁶ cm ^-2.
To introduce.

Next, as shown in FIG. 2B, after removing the SiO ₂ film 26, Phos 32 is applied to the entire surface of the Si substrate 11 with a dose amount of about 1 × 10 ¹² to 1 × 10 ¹³ cm ^-2. Ion implantation. In addition, the ion implantation of Phos32 is S
It may be performed before the growth of the iO ₂ film 26, that is, before the introduction of Sb31.

[0019] Then, by heat treatment in an oxidizing atmosphere to form an SiO ₂ film (not shown) on the surface of the Si substrate 11, removing the SiO ₂ film by wet etching. This is because the layer damaged by the ion implantation of Phos 32 is made into a SiO ₂ film, and the damaged layer is removed by removing this SiO ₂ film, and Phos 32 is diffused downward.

Next, as shown in FIG. 2C, the resistivity is 1
An N-type epitaxial layer 21 having a thickness of about 1.0 to 1.3 μm and a thickness of about Ωcm is grown on the Si substrate 11;
The Si substrate 11 and the epitaxial layer 21 form the Si substrate 22.
Make up.

At this time, Sb31 diffuses to form an N ⁺ type buried layer 15 having an impurity concentration of about 1 × 10 ²⁰ cm ^-3 , and Phos 32 diffuses to have an impurity concentration of 1 × 10.
^An N type buried layer 33 having a size of about ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ is formed. Although Phos32 has a larger diffusion coefficient than Sb31, it is 1 × 10 ¹² to 1 × 10 ¹³ c as described above.
If the dose amount of Phos 32 is small at about m ^−2, the upward diffusion of the buried layer 33 is about 0.2 μm.

Next, as shown in FIG. 2D, a SiO ₂ film 24 for element isolation surrounding the bipolar portion 12, the PMOS portion 13 and the NMOS portion 14 is formed on the surface of the epitaxial layer 21 by the LOCOS method. After that, boron or the like is ion-implanted to form the P-type and retrograde-type well 23 in the NM.
It is formed in the OS section 14.

Further, the projection range is set to two stages, and boron is ion-implanted with high energy to penetrate the epitaxial layer 21 and the burying layer 33 from the SiO ₂ film 24 to S.
P-type diffusion layer 25 for element isolation reaching the i-substrate 11
And the diffusion layer 25 surrounds the bipolar portion 12. At this time, since the buried layer 33 has a low impurity concentration and a small thickness, the buried layer 33 is easily compensated when the diffusion layer 25 is formed, and the diffusion layer 25 easily penetrates the buried layer 33.

Next, as shown in FIG. 1, the N-type diffusion layer 34, which is a collector electrode extraction region, is formed in the bipolar portion 12.
Then, the bipolar transistor 35 is formed.
In addition, the source / drain P ⁺ type diffusion layers 36 and N
^{The +} type diffusion layer 37 and the like are connected to the PMOS section 13 and the NMOS section 14.
Then, the PMOS transistor 41 and the NMOS transistor 42 are formed.

In this embodiment as described above, since the buried layer 33 is provided in the NMOS section 14 which constitutes the memory cell of the SRAM, the buried layer 33 has a low impurity concentration.
Even if is depleted, the potential barrier is formed. For this reason, the electrons of the electron-hole pairs generated in the Si substrate 11 due to the α rays hardly reach the storage node of the memory cell, and the soft error resistance is high.

Moreover, since the buried layer 33 is formed by ion-implanting Phos 32 over the entire surface of the Si substrate 11, even if the buried layer 33 is formed, the mask process does not increase.

The thickness of the embedding layer 33 is set to the embedding layer 15
In this embodiment, the buried layer 33 has an impurity concentration lower than that of the buried layer 15 in order to make the buried layer 33 thinner. However, by using an impurity having a diffusion coefficient smaller than that of the buried layer 15, the buried layer 33 has a smaller diffusion coefficient. Embedding layer 1 with a thickness of 33
It may be thinner than 5.

Further, in the present embodiment, the well 23 and the buried layer 33 have opposite conductivity types, but even if the well conductivity type is the same conductivity type, a potential barrier is formed to some extent if there is a difference in impurity concentration. The layer 33 and the layer 33 do not necessarily have to have opposite conductivity types.

[0029]

According to the BiMOS semiconductor device of the first aspect,
Since the collector series resistance of the bipolar part can be reduced, the performance can be improved, but the MO
Since the punch-through hardly occurs between the source / drain and the diffusion layer at the interface between the first and second semiconductor layers in the S portion and the soft error resistance is high, the reliability is also high.

In the BiMOS semiconductor device according to claim 2, M
The thickness of the diffusion layer is relatively thick in the bipolar portion and relatively thin in the MOS portion because the diffusion layer at the interface between the first and second semiconductor layers in the OS portion is less diffused.
The BiMOS semiconductor device can be easily manufactured.

[Brief description of drawings]

FIG. 1 is a side sectional view of an embodiment of the present invention.

FIG. 2 is a side sectional view sequentially showing a manufacturing process of an embodiment of the present invention.

FIG. 3 is a side sectional view of a first conventional example of the present invention.

FIG. 4 is a side sectional view of a second conventional example of the present invention.

[Explanation of symbols]

 11 Si Substrate 12 Bipolar Section 13 PMOS Section 14 NMOS Section 15 Buried Layer 21 Epitaxial Layer 22 Si Substrate 33 Buried Layer

Claims (2)

[Claims] 1. A semiconductor substrate is composed of a first semiconductor layer and a second semiconductor layer laminated on the first semiconductor layer, and an interface between the first and second semiconductor layers. A diffusion layer is formed on the bipolar layer, and the diffusion layer has a relatively large thickness in the bipolar portion.
BiMOS semiconductor device that is relatively thin in the OS section. 2. The B according to claim 1, wherein the impurity concentration of the diffusion layer is lower in the MOS portion than in the bipolar portion.
iMOS semiconductor device.