JP2012134542A - Power semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power semiconductor device in which a freewheeling diode connected to an IGBT region in inverse parallel has a low on-resistance.SOLUTION: A power semiconductor device including a freewheeling diode connected to an IGBT region in inverse parallel comprises: a second-conductive-type first guard-ring layer formed in a surface of a first-conductive-type base layer deeper than a second-conductive-type base layer so as to surround an IGBT region serving as an IGBT element including the first-conductive-type base layer above a second-conductive-type collector layer; a first-conductive-type first semiconductor layer formed between the second-conductive-type collector layer and the first-conductive-type base layer; and a first-conductive-type second semiconductor layer that surrounds the second-conductive-type first guard-ring layer, reaches the first-conductive-type first semiconductor layer from the surface of the first-conductive-type base layer, and is electrically connected to the first-conductive-type first semiconductor layer.

Description

  The present invention relates to a power semiconductor device used for a power device, and more particularly to a power semiconductor device having a diode antiparallelly connected on the same chip.

  An IGBT (Insulated Gate Bipolar Transistor) is widely used as a power semiconductor element having a withstand voltage of about 300 V or higher. This IGBT is often used as a switching element in a power supply circuit or an inverter circuit. In this case, a free-wheeling diode connected in reverse parallel to the IGBT is required in order to pass a continuous current by an inductor in these circuits or in a load connected to these circuits. There is a demand for miniaturization of a power semiconductor device, and there is a need for a power semiconductor device in which a freewheeling diode and an IGBT element are built in the same chip.

  A power semiconductor device in which an IGBT and a freewheeling diode are built in the same chip has already been proposed (Patent Document 1). In this power semiconductor device, an n-type channel stopper layer is provided on the end surface of the IGBT chip in order to prevent the depletion layer from extending on the dicing line of the chip. This is electrically connected to the collector electrode of the IGBT as a cathode layer. Further, a p-type diffusion layer formed on the outer periphery of the IGBT element region is connected to the emitter electrode of the IGBT element as an anode layer. A freewheeling diode having the p-type diffusion layer as an anode layer and a channel stopper layer as a cathode layer is integrally formed so as to be connected in reverse parallel to the IGBT region.

  In this conventional power semiconductor device, when a positive voltage is applied to the emitter electrode with respect to the collector electrode of the IGBT, the emitter electrode, the p-type semiconductor layer, the n-type epitaxial layer, the channel stopper layer, and the collector electrode are routed. Current flows. However, in this free-wheeling diode, the current concentrates near the surface of the n epitaxial layer, so the on-resistance of the free-wheeling diode is relatively high.

JP-A-11-54747

  Provided is a power semiconductor device in which a free-wheeling diode connected in reverse parallel to an IGBT region in the same chip is formed.

  A power semiconductor device according to an aspect of the present invention includes a first conductivity type base layer having a first surface and a second surface opposite to the first surface, and the first conductivity type base layer. A second conductivity type base layer selectively formed on the surface of the first conductivity type; a first conductivity type emitter layer formed on a surface of the second conductivity type base layer opposite to the first conductivity type base layer; A gate electrode formed on the first conductivity type base layer, the second conductivity type base layer, and the first conductivity type emitter layer via a gate insulating film; and a second surface of the first conductivity type base layer A first conductive type first semiconductor layer having an impurity concentration higher than that of the first conductive type base layer formed thereon, and a surface of the first conductive type first semiconductor layer opposite to the first conductive type base layer; And a second conductivity type collector layer formed on the substrate. An IGBT region, a second conductivity type first guard ring layer formed on a first surface of the first conductivity type base layer so as to surround the IGBT region, and the first conductivity type collector layer. A first main electrode formed on a surface opposite to the conductive first semiconductor layer; the first conductive emitter layer; the second conductive base layer; and the second conductive first guard ring layer. A second main electrode electrically connected to the gate electrode and insulated from the gate electrode by an interlayer insulating film; and the first conductive type base layer around the IGBT region and the second conductive type first guard ring layer. A first conductivity type second semiconductor layer that reaches the first conductivity type first semiconductor layer from a first surface and is electrically connected to the first main electrode; To do.

  According to another aspect of the present invention, there is provided a power semiconductor device including a first conductivity type base layer having a first surface and a second surface opposite to the first surface, and the first conductivity type base layer. A second conductivity type base layer selectively formed on the surface of the first conductivity type; a first conductivity type emitter layer formed on a surface of the second conductivity type base layer opposite to the first conductivity type base layer; A gate electrode formed on the first conductive type base layer, the second conductive type base layer and the first conductive type emitter layer with a gate insulating film interposed therebetween; and a second of the first conductive type base layer. A first conductivity type first semiconductor layer having an impurity concentration higher than that of the first conductivity type base layer formed on the surface; and a side of the first conductivity type first semiconductor layer opposite to the first conductivity type base layer. An IGBT unit having a second conductivity type collector layer formed on the surface of A plurality of IGBT regions, a plurality of second conductivity type first guard ring layers formed on a first surface of the first conductivity type base layer so as to surround each of the plurality of IGBT regions, A first main electrode formed on a surface of the two-conductivity-type collector layer opposite to the first-conductivity-type first semiconductor layer; the first-conductivity-type emitter layer; the second-conductivity-type base layer; A second main electrode electrically connected to the second conductivity type first guard ring layer and insulated from the gate electrode by an interlayer insulating film; the plurality of IGBT regions; and the plurality of second conductivity type first guards. A first conductivity type second that individually surrounds the ring layer, reaches the first semiconductor layer from the first surface of the first conductivity type base layer, and is electrically connected to the first electrode. And a semiconductor layer.

  According to the present invention, it is possible to reduce the on-resistance of the freewheeling diode in the power semiconductor device in which the freewheeling diode connected in reverse parallel to the IGBT region is formed in the same chip.

The top view of the semiconductor device for electric power of Example 1 of this invention. Sectional drawing of the principal part of the semiconductor device for electric power of Example 1 of this invention. The figure which shows the voltage-current characteristic of the semiconductor device for electric power of Example 1 of this invention. Sectional drawing of the principal part of the power semiconductor device of the modification of Example 1 of this invention. Sectional drawing of the principal part of the power semiconductor device of another modification of Example 1 of this invention. Sectional drawing of the principal part of the semiconductor device for electric power of Example 2 of this invention. The top view of the semiconductor device for electric power of Example 3 of this invention. Sectional drawing of the principal part of the semiconductor device for electric power of Example 3 of this invention. Sectional drawing of the principal part of the semiconductor device for electric power of Example 4 of this invention. The top view and sectional drawing of the principal part of the power semiconductor device of Example 5 of this invention.

  Embodiments of the present invention will be described below with reference to the drawings. In the embodiments, the first conductivity type is assumed to be n-type and the second conductivity type is assumed to be p-type. When n (−), n, and n (+) symbols are used as the n-type impurity layer, the n-type impurity concentration in the layer increases in the order of n (−) <n <n (+). To do. The same applies to the p-type impurity layer. Furthermore, unless otherwise specified, the impurity concentration refers to the net impurity concentration after compensation of each conductivity type.

In addition, the drawings used in the description in the embodiments are schematic for ease of description, and the shape, dimensions, magnitude relationship, etc. of each element in the drawings are not necessarily shown in the drawings in actual implementation. It is not always the case. Furthermore, it is possible to change the shape, size, magnitude relationship, impurity concentration, material, etc. within the range where the effects of the present invention can be obtained.

  Further, unless otherwise specified, the semiconductor layer (including a base layer, a collector layer, an emitter layer, an anode layer, a cathode layer, etc.) indicates a semiconductor layer made of Si (silicon) as an example. For example, a semiconductor layer made of SiC or the like is also possible.

  FIG. 1 is a plan view of a power semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a view of the AA cross section of FIG. FIG. 1 shows a plan view of the first guard ring layer 8, the n (−) type base layer 1, the n type second semiconductor layer 9, and the IGBT region 13, and details in the IGBT region 13 are shown. The structure and other elements are omitted.

  The power semiconductor device 100 of this embodiment includes an n (−) type (first conductivity type) base layer 1 having a first surface and a second surface opposite to the first surface. The impurity concentration of the n-type base layer 1 is, for example, about 1e12 to 1e15 / cm 3 and is appropriately selected according to the required breakdown voltage of the power semiconductor device 100. A p-type (second conductivity type) base layer 2 is formed on the first surface of the n (−) type base layer 1. The impurity concentration of the p-type base layer 2 is, for example, about 1e16 to 1e18 / cm3. An n-type emitter layer 3 is selectively formed on the surface of the p-type base layer 2. The impurity concentration of the n-type emitter layer 3 is appropriately selected so that an ohmic contact with an emitter electrode (second main electrode) 11 described later can be formed. A trench 16 is formed from the surface of the n-type emitter layer 3 through the n-type emitter layer 3 and the p-type base layer 2 to reach the n (−) base layer, and a gate is formed in the trench via the gate insulating film 4. The electrode 5 is formed so as to fill the trench 16. As the gate insulating film, for example, an oxide film obtained by thermally oxidizing the Si surface of the trench 16 is used. As the gate electrode 5, for example, polysilicon is used. An interlayer insulating film 14 is formed on the gate electrode 5, and the gate electrode 5 is insulated from the n (−) type base layer 1, the p type base layer 2, the n type emitter layer 3, and an emitter electrode 11 described later. Has been.

  An n-type first semiconductor layer 6 is formed on the second surface of the n (−)-type base layer 1, and the impurity concentration is set higher than that of the n (−)-type base layer 1, for example, 1e15 to 1e17 / cm 3. Is set to A p (+) type collector layer 7 is formed on the surface of the n type first semiconductor layer 6 opposite to the n (−) type base layer 1.

  With the gate electrode 5 as the center, the p (+) type collector layer 7, the n type first semiconductor layer 6, the n (−) type base layer 1, the p base layer 2, the gate electrode 5, and the gate insulating film 4. A region composed of the n-type emitter layer 3 facing the gate electrode 5 at both ends of the gate electrode 5 is an IGBT unit 12 that functions as one IGBT element. The IGBT region 12 is formed by repeatedly forming the IGBT unit 12 in the plane within the n (−) type base layer 1. As shown in FIG. 2, the n emitter layer 3 is provided on the outer peripheral side of the IGBT unit 12 located on the outermost periphery in order to suppress latch-up due to the avalanche current at the end of the p base layer 2. It is also possible to have a structure that is not provided.

  The p-type first guard ring layer 8 extends from the first surface of the n (−)-type base layer 1 toward the second surface so as to surround the IGBT region 13. More specifically, the first guard ring layer 8 can have an annular structure surrounding the IGBT region 13. The first guard ring layer 8 is formed deeper than the bottom of the p-type base layer 2. The impurity concentration of the first guard ring layer 8 is about 1e18 to 1e20 / cm 3, and is a depletion layer that spreads from the interface between the p-type base layer 2 and the n (−)-type base layer 1 at the outer peripheral edge of the p-type base layer 2. Is spread toward the n-type first semiconductor layer 6. Thereby, the breakdown due to the electric field concentration at the outer peripheral edge of the p-type base layer 2 is suppressed. The first guard ring layer 8 can be formed by ion implantation of a p-type impurity such as boron and the subsequent thermal diffusion process.

  The n (+)-type second semiconductor layer 9 is exposed from the first surface of the n (−)-type base layer 1 so as to further surround the first guard ring layer 8 outside the IGBT region 13. Stretched to reach As shown in FIG. 1, when the first guard ring layer 8 is a rectangular shape in a plan view as an example, for example, a square, the n (+) type second semiconductor layer 9 is formed so as to surround all four sides. A rectangular ring-shaped structure may be used, or a U-shaped shape (not shown) may be provided so that three sides are wrapped around the first guard ring layer 8 in a plan view. Alternatively, the n (+)-type second semiconductor layer 9 may be formed only in a portion facing one side of the first guard ring layer 8 in the plan view (not shown). However, in this case, since the area facing the first guard ring layer 8 of the n (+) type second semiconductor layer 9 serving as the cathode layer, that is, the cross-sectional area of the current path of the freewheeling diode is narrowed, n (+) The on-resistance is higher than when the second type semiconductor layer 9 has a ring structure.

The n-type (+) second semiconductor layer 9 only has to reach the n-type first semiconductor layer 6 and be electrically connected thereto. The n (−)-type base layer 1 of the n-type first semiconductor layer 6 is sufficient. It may be joined at the surface on the side, bite into the n-type first semiconductor layer 6, or may penetrate the n-type first semiconductor layer 6 and reach the p-type collector layer 7. The impurity concentration of the n (+)-type second semiconductor layer 9 may be at least equal to, preferably higher than, the impurity concentration of the n-type first semiconductor layer 6. Since the n (+) type second semiconductor layer 9 becomes a cathode layer of a free-wheeling diode described later, for example, it is desirable to set it to about 1e18 to 1e20 / cm3 in order to reduce the on-resistance of the free-wheeling diode. Even when the impurity concentration is lower than this, there is an effect that the switching speed of the freewheeling diode is increased.

The n (+) type second semiconductor layer 9 can be formed by ion implantation from the first surface of the n (−) type base layer 1 and a subsequent thermal diffusion process. Alternatively, a trench is formed by anisotropic etching such as dry etching or isotropic etching such as wet etching, and an n-type semiconductor layer such as an Si epitaxial layer or a polysilicon layer is embedded in the trench. You can also

  A first main electrode 10 is formed on the surface of the p (+) type collector layer 7 opposite to the n type first semiconductor layer 6, and the first main electrode 10 is electrically connected to the p (+) type collector layer 7. Connected. The second main electrode is electrically connected to the upper surfaces of the p-type base layer 2 and the n-type emitter layer 3, is insulated from the gate electrode 5 by the interlayer insulating film 14, and straddles the gate electrode 5, so that the first guard The upper surface of the ring layer 8 is electrically connected.

  A cathode electrode 15 is formed on the surface of the n (+) type second semiconductor layer 9 opposite to the first main electrode side, and the cathode electrode is electrically joined to the first main electrode. For example, by joining the lead frame electrically connected to the power semiconductor device 10 via the first main electrode and the cathode electrode 15 by a bonding wire or the like (not shown), such bonding can be achieved. Is possible.

  With the electrode connection, in the IBGT region 13, the first main electrode functions as a collector electrode, the second main electrode functions as an emitter electrode, and a current flowing from the first main electrode toward the second main electrode is gated. An IBGT structure controlled by electrodes is formed. In addition, a freewheeling diode is formed in which the p-type first guard ring layer 8 and the p base layer 2 function as an anode layer, and the n-type first semiconductor layer 6 and the n (+)-type second semiconductor layer 9 function as a cathode layer. Yes. In this free-wheeling diode, the p-type first guard ring layer 8 and the p base layer 2 that are anode layers are connected to the second main electrode 11, and the n-type first semiconductor layer 6 and n (+) type that are cathode layers. The second semiconductor layer 9 is electrically connected to the first main electrode 10 through the cathode electrode 15 to form an antiparallel connection with the IBGT region 13 and formed in the same semiconductor chip. Yes.

Next, the operation of the power semiconductor device 100 of this embodiment will be described. In a state where a voltage is applied to the second main electrode 11 so that the first main electrode 10 has a positive potential, the gate electrode 5 has a positive potential equal to or higher than a threshold value with respect to the second main electrode 11. When a voltage is applied to the p-type base layer 2, an n-channel layer having an inversion distribution is formed in a portion of the p-type base layer 2 facing the gate electrode 5, and the second main electrode passes through the n-type emitter layer 3 and the channel layer. When electrons are injected into the n (−) type drift layer 1, the n (−) type drift layer passes through the p (+) type collector layer 7 and the n type first semiconductor layer 6 from the first main electrode. Holes are injected into 1 to cause conductivity modulation and turn on. The holes then flow to the second main electrode via the p-type base layer 2, and the electrons flow to the first main electrode via the n-type first semiconductor layer 6 and the p (+)-type collector layer 7. To flow. As a result, current flows from the first main electrode to the second main electrode in the IGBT region 13. In addition, when a voltage is applied so that the second main electrode has a positive potential with respect to the first main electrode while the IGBT region is in an off state, a current flows from the second main electrode to the p-type first guard ring. (1) A part of current flows radially from the p-type first guard ring layer 8 toward the n-type second semiconductor layer 9 on the surface of the n (−)-type drift layer 1. C2 flows into the second semiconductor layer 9 and (2) the other part of the n (−) type drift layer 1 from the p-type first guard ring layer 8 toward the n-type first semiconductor layer 6. The current flows into the first semiconductor layer 6 through the current path C2 that spreads radially in the depth direction, flows along the first semiconductor layer along the plane, and flows into the second semiconductor layer 9. (3) Furthermore, a current flows from the second main electrode to the p-type base layer 2, and the depth direction of the n (−)-type drift layer 1 from the p-type base layer 2 toward the n-type first semiconductor layer 6. Then, it flows into the first semiconductor layer 6 through the current path C3, flows along the first semiconductor layer 6 along the surface, and flows into the second semiconductor layer 9. The current via the current path C1 and the current via the current paths C2 and C3 merge in the second semiconductor layer 9 and flow to the first main electrode via the cathode electrode 15. As a result, the freewheeling diode having the first guard ring layer 8 and the p base layer 2 as the anode layer and the first semiconductor layer 6 and the second semiconductor layer 9 as the cathode layer is turned on, and the second main diode is turned on. A current flows from the electrode toward the first main electrode.

  In the free-wheeling diode of the power semiconductor device 100 of the present embodiment, the n (+) type second semiconductor layer 9 serving as a cathode layer is directed from the first surface of the n (−) type base layer 1 toward the second surface. Since the structure extends and reaches the n-type first semiconductor layer 6 and is electrically connected to the n-type first semiconductor layer 6, only the n (+)-type second semiconductor layer 9 functions as a cathode layer. Instead, the n-type first semiconductor layer 6 is also characterized by functioning as a cathode layer. As a result, in the conventional power semiconductor device including the freewheeling diode described in Patent Document 1, the current of the freewheeling diode flows only near the surface of the n (−) type base layer 1 (current near the surface). In contrast, the freewheeling diode of this example further includes current paths C2 and C3 that flow in the depth direction of the n (−) type base layer 1, The on-resistance of the freewheeling diode can be further reduced. Here, FIG. 3 shows the result of comparing the voltage-current characteristics of the free-wheeling diode having the conventional structure in which the cathode layer is formed in a ring shape on the surface of the n (−) drift layer and the free-wheeling diode according to this embodiment by simulation. Thus, according to the present invention, the current density can be increased by 30% or more at the same on-voltage. In addition to the fact that the area of the cathode of the freewheeling diode according to the present embodiment is increased, this effect is generally due to the distance between the p-type first guard ring layer 8 and the p-type base layer 2 and the n-type first semiconductor layer 6. This is because the distance is shorter than the distance between the p-type first guard ring layer 8 and the n (+)-type second semiconductor layer 9, which is a special effect of the present invention.

  The on-resistance of the freewheeling diode of this example is the distance between the p-type first guard ring layer 8 and the p-type base layer 2, the n-type first semiconductor layer 6 and the n (+)-type second semiconductor layer 9. And the concentration of each impurity. Increasing the impurity concentration of the n-type first semiconductor layer 6 is not preferable because the injection of holes from the p (+)-type collector layer 7 is suppressed in the operation of the IGBT, and it is not preferable to suppress the impurity concentration to about 1e15 to 1e17 / cm3. desirable. Therefore, it is desirable to reduce the on-resistance of the freewheeling diode by increasing the impurity concentration of the n (+) type second semiconductor layer 9. The impurity concentration of the n (+)-type second semiconductor layer is desirably set to about 1e18 to 1e20 / cm 3, but can be lowered to the same level as that of the n-type first semiconductor layer 6. In this case, the on-resistance is sacrificed, but the high-speed response of the freewheeling diode is improved.

  Note that the trench gate electrode in the IGBT region may have a stripe shape extending in one direction, or a lattice shape or a staggered lattice structure. When the gate electrode 5 is on a stripe, the n-type emitter layer 3 may have a stripe shape extending along the stripe direction of the gate electrode 5, or the n-type emitter layer 3 and the p-type base layer 3 are alternately arranged. It can also be an arrayed structure. Furthermore, although the gate electrode has been described in the case of a trench gate structure, it is of course possible to use a planar gate electrode described in Modification 1 of the present embodiment described later. Furthermore, it is clear that all known IGBT structures can be combined with the freewheeling diode according to the invention.

  Although the first guard ring layer 8 has been described as a deeper layer independently of the p-type base layer 2, the p-type base layer 2 is actually used for the first guard ring layer 8 mainly for cost reduction. However, even in this case, it is clear that it has a function as the anode layer of the freewheeling diode according to the present invention and can be applied to the structure of the present invention.

  All of these changes can be made in the following embodiments and modifications.

  FIG. 4 shows a cross-sectional view of the main part of the power semiconductor device 200 of the first modification of the first embodiment of the present invention. The plan view of the power semiconductor device 200 is substantially the same as FIG. 1, and FIG. 4 corresponds to a cross-sectional view of the AA cross section of FIG. Hereinafter, the same or similar parts as those in the first embodiment will be described with the same reference numerals, and only different parts from the first embodiment will be described.

  The power semiconductor device 200 according to this modification is different from the power semiconductor device 100 according to the first embodiment in that the gate electrode has a planar structure instead of a trench structure. The power semiconductor device 100 according to the first embodiment is also provided with a p-type second guard ring layer 29 between the p-type first guard ring layer 8 and the n (+)-type second semiconductor layer 9. Is different. The rest is the same as the first embodiment. This difference will be described below.

  In the power semiconductor device 200 of this modification, the p-type base layer 22 is selectively formed on the first surface of the n (−)-type base layer 1. An n-type emitter layer 23 is selectively formed on the surface of the p-type base layer 22. A planar-type gate electrode 25 is formed on the surfaces of the n-type emitter layer 23, the p-type base layer 22, and the n (−)-type base layer 1 via a gate insulating film 24. An interlayer insulating film 26 is formed so as to cover the gate electrode 25. The second main electrode is insulated from the gate electrode 25 by the interlayer insulating film 26 and is electrically connected to the surfaces of the n-type emitter layer 3, the p-type base layer 2 and the p-type first guard ring layer 8.

  The p-type second guard ring layer 29 surrounds the p-type first guard ring layer 8 between the p-type first guard ring layer 8 and the n-type second semiconductor layer 9, and more specifically has a ring structure. Thus, the n (−) type base layer 1 extends from the surface toward the first main electrode. The second guard ring layer 29 is integrally formed in the same process as the first guard ring layer, and has the same depth and impurity concentration. These can be formed by ion implantation of p-type impurities and subsequent thermal diffusion. Alternatively, the trench may be buried with an Si epitaxial layer or a polysilicon layer after the trench is formed. In FIG. 4, the second guard ring layer 29 is formed as an annular structure at three locations concentric with the center of the IGBT region, but a single or a plurality may be selected as appropriate.

  Electrically connected guard ring electrodes 30 are formed on the surfaces of the three second guard ring layers 29, which are insulated from each other and in a floating state.

  Also in the power semiconductor device 200 of the present modified example, the n (+) type second semiconductor layer 9 serving as the cathode layer is the n (−) type base layer, like the free-wheeling diode of the power semiconductor device 100 of the first embodiment. Since the first surface extends from the first surface toward the second surface and reaches the n-type first semiconductor layer 6 and is electrically connected to the n-type first semiconductor layer 6, n (+ The n-type first semiconductor layer 6 also functions as a cathode layer, rather than functioning only the second semiconductor layer 9 as a cathode layer. As a result, the current of the freewheeling diode flows near the surface of the n (−) type base layer 1 (has a current path near the surface) and further has a current path that flows in the depth direction. The on-resistance of the diode can be reduced.

  Furthermore, by providing the second guard ring layer 29, the breakdown voltage at the chip end portion is improved as compared with the power semiconductor device 100 of the first embodiment.

  FIG. 5 shows a cross-sectional view of the main part of the power semiconductor device 300 of Modification 2 of Embodiment 1 of the present invention. A plan view of the power semiconductor device 300 is substantially the same as FIG. 1, and FIG. 5 corresponds to a cross-sectional view of the AA cross section of FIG. Hereinafter, the same or similar parts as those in the first embodiment will be described with the same reference numerals, and only different parts from the first embodiment will be described.

  The power semiconductor device 300 according to the present modification is different from the power semiconductor device 100 according to the first embodiment in that the n-type first semiconductor layer 6 further includes an n (+)-type third semiconductor layer 42 in the plane. Is different. That is, in the power semiconductor device 300, among the n-type first semiconductor layers 6, the n-type (+) second semiconductor layer 9 is at least directly below the p-type first guard ring layer 8. The region up to the portion reaching the point becomes the n (+)-type third semiconductor layer 42 having an impurity concentration higher than that of the n-type first semiconductor layer 6. The rest is the same as in the first embodiment.

  Also in the power semiconductor device 300 of the present modification, the n (+) type second semiconductor layer 9 serving as the cathode layer is the n (−) type base layer, as in the free-wheeling diode of the power semiconductor device 100 of the first embodiment. 1 extends from the first surface toward the second surface, reaches the n (+)-type third semiconductor layer 42 that is a part of the n-type first semiconductor layer 6, and reaches the n-type first semiconductor layer 6 and Since the n (+)-type third semiconductor layer 42 is electrically connected to the n-type third semiconductor layer 42, the n-type first semiconductor layer 9 is not made to function as the cathode layer alone. The 6 and n (+) type third semiconductor layer 42 is also characterized by functioning as a cathode layer. As a result, the current of the freewheeling diode flows near the surface of the n (−) type base layer 1 (including the current path C1 near the surface), and further includes current paths C2 and C3 that flow in the depth direction. Therefore, the on-resistance of the freewheeling diode can be reduced.

  Further, in at least the n-type first semiconductor layer 6, a region from immediately below the p-type first guard ring layer 8 to a portion where the n-type second semiconductor layer 9 reaches the n-type first semiconductor layer 6 is n Since the n-type third semiconductor layer has an impurity concentration higher than that of the first semiconductor layer 6, the n (−)-type base layer 1 and the n (+)-type third semiconductor layer from the first guard ring layer. The resistance of the current path C2 flowing to the n-type second semiconductor layer 9 via 42 can be made lower than that of the first embodiment. As a result, the on-resistance of the freewheeling diode can be further reduced as compared with the first embodiment.

  In this modification, the n-type first semiconductor layer 6 is not all the n (+)-type third semiconductor layer 42 having a high impurity concentration. This is because if the impurity concentration of the n-type first semiconductor layer 6 is increased in the IGBT region 13, the p (+)-type collector layer 7 in the IGBT region 13 in the on-state of the IGBT changes to the n (−)-type base. This is because the injection of holes into the layer 1 is suppressed, and the on-resistance between the collector and the emitter in the IGBT region 13 increases.

  As an example of a method for forming the n (+)-type third semiconductor layer 42, the n-type first semiconductor layer 6 is formed immediately below the p-type first guard ring layer 8 after the n-type first semiconductor layer 6 is formed. A step of ion-implanting an n-type impurity into a region up to a portion where the n (+)-type second semiconductor layer 9 reaches the n-type first semiconductor layer 6 and then forming an n (−)-type base layer 1 by an epitaxial growth method. Thus, the n (+) type third semiconductor layer 42 can be formed.

  FIG. 6 is a cross-sectional view of a main part of the power semiconductor device 400 according to the second embodiment of the present invention. A plan view of the power semiconductor device 400 is substantially the same as FIG. 1, and FIG. 6 corresponds to a cross-sectional view of the AA cross section of FIG. Hereinafter, the same or similar parts as those in the first embodiment will be described with the same reference numerals, and only different parts from the first embodiment will be described.

The power semiconductor device 400 of the present embodiment has an n (+) type that reaches the first main electrode 10 instead of the n (+) type second semiconductor layer 9 that has reached the n type first semiconductor layer 6. The second semiconductor layer 51 is different from the power semiconductor device 100 of the first embodiment in that the second semiconductor layer 51 is used. The rest is the same as the first embodiment. This difference will be described below.

  The n (+)-type second semiconductor layer 51 of the power semiconductor device 400 of the present embodiment has a structure surrounding the first guard ring layer 8, preferably an annular structure surrounding the first guard ring layer 8. The first main electrode 10 extends from the first surface of the n (−)-type base layer 1 toward the second surface, penetrates the n-type first semiconductor layer 6 and the p (+)-type collector layer 7. And is electrically connected to the first main electrode. Note that, in all regions of the annular structure of the second semiconductor layer 51, the first main electrode 10 may be reached through the n-type first semiconductor layer 6 and the p (+)-type collector layer 7. That is not necessary, that is, it may be connected to the first main electrode 10 through the n-type first semiconductor layer 6 and the p (+)-type collector layer 7 while maintaining the annular structure. For example, the n-type second semiconductor layer 51 extends in a circular structure from the first surface of the n (−)-type base layer 1 toward the second surface and is connected to the n-type first semiconductor layer 6 to form a ring. A part of the structure may be a columnar structure that penetrates the n-type first semiconductor layer 6 and the p (+)-type collector layer 7 and reaches the first main electrode 10. The portion of the n (+)-type second semiconductor layer 51 that passes through the n-type first semiconductor layer 6 and the p (+)-type collector layer 7 is the n-type first semiconductor layer 6 and the n (+)-type second semiconductor layer 51. Any structure that can electrically connect the semiconductor layer 51 to the first main electrode 10 may be used.

  The n (+)-type second semiconductor layer 51 is directly joined to the first main electrode 10, whereby the p-type first guard ring layer 8 and the p-type base layer 2 are used as anode layers, and the n-type first semiconductor layer. A free-wheeling diode using the 6 and n (+)-type second semiconductor layer 51 as a cathode layer is connected in reverse parallel to the IGBT region 13. Unlike Example 1, it is not necessary to provide the cathode electrode 15 electrically joined to the upper surface of the n (+) type second semiconductor layer 51, and the lead in which the power semiconductor device 400 is mounted via the first main electrode. There is no need to provide wire bonding or the like for electrically joining the frame and the cathode electrode 15. For this reason, the assembly of the semiconductor device is further simplified.

  Also in the power semiconductor device 400 of the present modification, the n (+) type second semiconductor layer 51 serving as the cathode layer is the n (−) type base layer, like the free-wheeling diode of the power semiconductor device 100 of the first embodiment. Since the first surface extends from the first surface toward the second surface and reaches the n-type first semiconductor layer 6 and is electrically connected to the n-type first semiconductor layer 6, n ( Not only the +) type second semiconductor layer 51 functions as a cathode layer, but also the n type first semiconductor layer 6 functions as a cathode layer. As a result, the current of the freewheeling diode flows near the surface of the n (−) type base layer 1 (including the current path C1 near the surface), and further includes current paths C2 and C3 that flow in the depth direction. Therefore, the on-resistance of the freewheeling diode can be reduced.

  7 is a plan view of a power semiconductor device 500 according to the third embodiment of the present invention, and FIG. 8 is a cross-sectional view of the BB cross section in FIG. A cross-sectional view of the AA cross section of FIG. 7 viewed in the direction of the arrow is the same as FIG. Hereinafter, the same or similar parts as those in the first embodiment will be described with the same reference numerals, and only different parts from the first embodiment will be described.

  The power semiconductor device 500 of this embodiment is a part of a cross section parallel to the first surface of the n (−) type base 1 of the n (+) type second semiconductor layer 9 surrounding the p type first guard ring layer 8. 1, in that it further includes a conductor 71 that reaches the first main electrode 10 from the first surface of the n (−) type base 1 and is electrically connected to the first main electrode 10. This is different from the power semiconductor device 100 of the embodiment. That is, the conductor 71 reaches the first main electrode 10 from the first surface of the n (−) type base 1 through the n (+) type second semiconductor layer 9 and the p (+) type collector layer 7. Then, the n (+) type second semiconductor layer 9 is electrically connected to the first main electrode 10 by being electrically connected to the first main electrode 10. As a result, the freewheeling diode having the p-type first guard ring layer 8 and the p-type base layer 2 as an anode layer and the n-type first semiconductor layer 6 and the n (+)-type second semiconductor layer 9 as a cathode layer is an IGBT. The region 13 is connected in antiparallel.

  The conductor 71 may be a conductive material, and may be a semiconductor layer or a metal. For example, a conductive material having good embedding properties such as polysilicon for a semiconductor and tungsten for a metal is preferable. The conductor 71 is formed from the first surface of the n (−) type base 1 through the n (+) type second semiconductor layer 9 and the p (+) type collector layer 7 to reach the first main electrode 10. This is possible by forming a via to be formed by etching or the like and embedding a conductor 71 in the via.

  In the power semiconductor device 500 of the present embodiment as well, unlike the power semiconductor device 100 of the first embodiment, the power semiconductor device 500 of the second embodiment is electrically connected to the upper surface of the n (+) type second semiconductor layer 9. There is no need to provide the cathode electrode 15 that is bonded to the power, and it is necessary to provide wire bonding or the like for electrically bonding the lead frame mounted on the power semiconductor device 500 via the first main electrode and the cathode electrode 15. Absent. For this reason, the assembly of the semiconductor device is further simplified.

  Also in the power semiconductor device 500 of the present embodiment, the second semiconductor layer 9 serving as the cathode layer is the first of the n (−) type base layer 1 as in the free-wheeling diode of the power semiconductor device 100 of the first embodiment. Since the structure extends from the surface of the first layer toward the second surface, reaches the n-type first semiconductor layer 6 and is electrically connected to the n-type first semiconductor layer 6, the n (+)-type first Not only the two semiconductor layers 9 function as a cathode layer, but the n-type first semiconductor layer 6 also functions as a cathode layer. As a result, the current of the freewheeling diode flows near the surface of the n (−) type base layer 1 (including the current path C1 near the surface), and further includes current paths C2 and C3 that flow in the depth direction. Therefore, the on-resistance of the freewheeling diode can be reduced.

  In the power semiconductor device 500 of the present embodiment, by using the conductor 71 as a metal material, the on-resistance of the freewheeling diode can be further reduced as compared with the power semiconductor device 400 of the second embodiment. .

  In the present embodiment, a via reaching the first main electrode 10 from the first surface of the n (−) type base layer 1 is formed in the n (+) type second semiconductor layer 9. The conductor 71 is embedded therein, and the conductor 71 is not exposed at the chip end of the power semiconductor device 500. However, when the chip is diced along the direction in which the n (+) type second semiconductor layer 9 extends, the chip is separated by dicing so that the dicing line divides the conductor 71, thereby separating the chip. It is also possible to adopt a structure in which the conductor 71 is exposed at the end (diced surface).

  FIG. 9 is a cross-sectional view of a main part of the power semiconductor device 600 according to the fourth embodiment of the present invention. A plan view of the power semiconductor device 600 is substantially the same as FIG. 1, and FIG. 9 corresponds to a cross-sectional view of the AA cross section of FIG. Hereinafter, the same or similar parts as those in the first embodiment will be described with the same reference numerals, and only different parts from the first embodiment will be described.

  The power semiconductor device 600 of this example is different from the power semiconductor device 100 of Example 1 in that a buried layer 83 is formed in the n (+) type second semiconductor layer 81 with an insulating film 82 interposed therebetween. Wrong. The insulating film 82 may be any material having an insulating property, and may be, for example, an oxide film or a nitride film. Further, since the buried layer 83 is intended to be buried, it may be a conductive material or an insulating material. An example is a polysilicon layer.

  As an example of a method for forming the n (+)-type second semiconductor layer 81, the insulating film 82, and the buried layer 83, for example, the p-type first guard ring layer 8 is surrounded so that an annular structure is preferable. A trench is formed surrounding and extending from the first surface of the n (−) type base layer to the second surface. An n (+)-type second semiconductor layer 81 can be formed by ion-implanting n-type impurities such as P (phosphorus) or As (arsenic) into the side and bottom of the trench and then thermally diffusing. Alternatively, after the trench is formed, the sidewall and the bottom of the trench are exposed to an atmosphere containing POCl 3 (phosphorus oxychloride) at a high temperature, so that phosphorus diffuses from the trench sidewall and the bottom to the n (−) type base layer 1. Thus, the n (+) type second semiconductor layer 81 can be formed.

  After that, the surface of the n (+) type second semiconductor layer 81 formed on the trench sidewall and the bottom is thermally oxidized to form an oxide film (SiO 2) that becomes the insulating film 82. The insulating film 82 may be formed by depositing a SiO2 film or a nitride film (SiN) by CVD (Chemical Vapor Deposition). In any case, the insulating film 82 is formed along the sidewall and bottom of the trench, and the trench shape is inherited as it is.

  After that, after forming the buried layer 83 so as to fill the trench, the surface of the buried layer 83 is made into an n (−) type base layer by a process of planarizing the surface such as CMP (Chemical Mechanical Polishing) or CDE (Chemical Dry Etching). The first surface of the first surface is flush with the first surface. Note that the buried layer 83 may be any material that can be buried flat, and may be a conductive material or an insulating material. As an example of a material having excellent embedding properties, polysilicon can be used as a semiconductor, and tungsten can be used as a metal. In this embodiment, the buried layer 83 is formed through the insulating film 82, but the buried layer 83 is formed directly on the surface of the n (+) type second semiconductor layer 81 without going through the insulating film 82. Can also be embedded. When silicon is formed on the surface of the insulating film 82 by CVD, polysilicon is deposited without forming an epitaxial layer of silicon. Since polysilicon has a higher trench burying property than a silicon epitaxial layer, it is preferable to bury a buried layer 83 made of polysilicon through an insulating film 82. The feature of the structure according to this embodiment is that the deep n-type second semiconductor layer 81 that becomes the cathode region of the diode can be easily formed. That is, in order to form the deep n-type second semiconductor layer 9 according to the first embodiment or the like, deep diffusion or epitaxial formation after trench formation is required, but it can be easily embedded with polysilicon or the like. It is a feature.

  Also in the power semiconductor device 600 of the present embodiment, the n (+)-type second semiconductor layer 81 serving as the cathode layer is the n (−)-type base layer, like the free-wheeling diode of the power semiconductor device 100 of the first embodiment. Since the first surface extends from the first surface toward the second surface and reaches the n-type first semiconductor layer 6 and is electrically connected to the n-type first semiconductor layer 6, n (+ The n-type first semiconductor layer 6 also functions as a cathode layer, rather than functioning only the second type semiconductor layer 81 as a cathode layer. As a result, the current of the freewheeling diode flows near the surface of the n (−) type base layer 1 (including the current path C1 near the surface), and further includes current paths C2 and C3 that flow in the depth direction. Therefore, the on-resistance of the freewheeling diode can be reduced.

  In the power semiconductor device 600 of the present embodiment, the surface of the n (+) type second semiconductor layer 81 is arranged so that the cathode electrode is electrically connected to at least the n (+) type second semiconductor layer 81. Preferably, it is also formed on the surface of the buried layer 83.

  10A and 10B are schematic views of a power semiconductor device 700 according to a fifth embodiment of the present invention. FIG. 10A is a plan view thereof, and FIG. 10B is a cross-sectional view taken along a line CC in FIG. It is the schematic of the cross section seen in the arrow direction. FIG. 10A shows a plan view of the p-type first guard ring layer 8, the n (−) type base layer 1, the n (+) type second semiconductor layer 91, and the IGBT region 13. The detailed structure and other elements in the IGBT region 13 are omitted. In FIG. 10B, the details of the structure of the IGBT region 13 are omitted as they are shown in the cross section of FIG.

  The power semiconductor device 700 according to the present embodiment includes the power semiconductor device 100 according to the first embodiment as a unit, and as illustrated in the plan view of FIG. The structure of the device 100 is repeated three times. Here, the structure of the IGBT region 13 has the same cross-sectional structure as that of the IGBT region shown in FIG. 2 in the first embodiment, and the details thereof are omitted. Further, the power semiconductor device 100 is continuously and repeatedly formed, so that the adjacent power semiconductor devices 100 are formed so as to share the adjacent portions of the respective n (+) type second semiconductor regions 9. . As a result, the n (+) type second semiconductor region 9 of Example 1 is formed in a ladder shape, and the n (+) type second semiconductor region in which the IGBT region 13 is formed in the opening of the ladder. 91. The n (+)-type second semiconductor region 91 has a planar shape surrounding each IGBT region 13 at the opening of the ladder.

  That is, the power semiconductor device 700 is configured as follows. The IGBT region 13 is composed of a plurality of IGBT units described in the first embodiment. Each IGBT unit has an n-type (first conductivity type) base layer 1 having a first surface and a second surface facing the first surface. A p-type (second conductivity type) base layer is selectively formed on the first surface of the n (−)-type base layer. An n-type emitter layer 3 is formed on the surface of the p-type base layer 2 opposite to the n (−)-type base layer 1. A gate electrode 5 is formed on the n (−) type base layer 1, the p type base layer 2 and the n type emitter layer 3 with a gate insulating film 4 interposed therebetween. An n-type first semiconductor layer 6 having an impurity concentration higher than that of the n (−)-type base layer 1 is formed on the second surface of the n (−)-type base layer 1. A p (+) type collector layer 7 is formed on the surface of the n type first semiconductor layer 6 opposite to the n (−) type base layer 1.

  The IGBT region 13 is arranged so as to repeat three periods as a unit, and the p-type first guard ring layer 8 is formed from the first surface of the n (−)-type base 1 so as to surround each IGBT region 13 in an annular shape. It is formed deeper than the p-type base layer 2 toward the second surface. A first main electrode 10 is formed on the surface of the p (+) type collector layer 7 opposite to the n-type first semiconductor layer 6. A second main electrode 11 (see FIG. 5) electrically connected to the n-type emitter layer 3 and the p-type base layer 2 and the p-type first guard ring layer 8 and insulated from the gate electrode 5 by an interlayer insulating film. (Not shown) is formed.

  Further, the n (+)-type second semiconductor layer 91 is n-type from the first surface of the n (−)-type base layer 1 so as to surround each IGBT region 13 and the p-type first guard ring layer 8 in an annular shape. It is formed so as to reach the first semiconductor layer 6. That is, the n (+)-type second semiconductor layer 91 is formed in a ladder shape, and each IGBT region 13 surrounded by the p-type first guard ring layer 8 is disposed in the opening thereof.

  The n (+) type second semiconductor layer 91 is formed by electrically connecting the cathode electrode 15 to the surface thereof (not shown) as in the first embodiment. The lead frame mounted with the power semiconductor device 700 electrically connected via the first main electrode 10 and the cathode electrode 15 are electrically connected by wire bonding or the like (not shown).

  Due to the electrode connection, as in the first embodiment, in the plurality of IBGT regions 13, the first main electrode functions as a collector electrode, the second main electrode 11 functions as an emitter electrode, and the first main electrode 10 to the second electrode Thus, an IBGT structure in which the current flowing toward the main electrode 11 is controlled by the gate electrode 5 is formed. In addition, a freewheeling diode is formed in which the p-type first guard ring layer 8 and the p-type base layer 2 function as an anode layer, and the n-type first semiconductor layer 6 and the n (+)-type second semiconductor layer 91 function as a cathode layer. ing. The p-type first guard ring layer 8 and the p-type base layer 2 that are anode layers are connected to the second main electrode, and the n-type first semiconductor layer 6 and the n (+)-type second semiconductor layer 91 that are cathode layers. Is electrically connected to the first main electrode 10 via the cathode electrode 15, so that this free-wheeling diode forms an antiparallel connection with the IBGT region and is formed in the same semiconductor chip.

  Also in the power semiconductor device 700 of the present modified example, the n (+) type second semiconductor layer 91 serving as the cathode layer is the n (−) type base layer, like the free-wheeling diode of the power semiconductor device 100 of the first embodiment. Since the first surface extends from the first surface toward the second surface and reaches the n-type first semiconductor layer 6 and is electrically connected to the n-type first semiconductor layer 6, n ( Not only the + type second semiconductor layer 91 functions as a cathode layer, but also the n type first semiconductor layer 6 functions as a cathode layer. As a result, the current of the freewheeling diode flows near the surface of the n (−) type base layer 1 (including the current path C1 near the surface), and further includes current paths C2 and C3 that flow in the depth direction. Therefore, the on-resistance of the freewheeling diode can be reduced. Furthermore, since the area occupied by the freewheeling diode in the same chip can be increased as compared with the power semiconductor device 100 of the first embodiment, the current capacity of the freewheeling current diode can be increased.

  In the present embodiment, the IGBT region 13 has a structure that is repeated three times in the horizontal direction, but it is of course possible to repeat it further. Furthermore, it can be arranged in a matrix form repeatedly in a plurality of times in both the vertical direction and the horizontal direction. In the present embodiment, the technical features of the first and second modifications of the first embodiment can be applied. That is, the trench gate structure can be replaced with a planar gate structure, and it is needless to say that the p-type second guard ring layer and the n-type third semiconductor layer can be applied to this embodiment.

  As mentioned above, although the form of the invention which concerns on this invention was demonstrated using said each Example, it is not restricted to the structure shown in each Example, Within the range which does not deviate from the summary of this invention, each component material, each layer Of course, the thickness, pattern shape, etc. may be changed. In addition, the film forming method and film forming conditions of each layer, the etching method and etching conditions, or the method of flattening the surface of the substrate can be changed without departing from the scope of the present invention.

  In particular, the structural differences from the first embodiment described in the second to fifth embodiments can be applied to the first and second modifications of the first embodiment, respectively.

1 n-type base layer 2, 22 p-type base layer 3, 23 n-type emitter layer 4, 24 gate insulating film 5, 25 gate electrode 6 n-type first semiconductor layer 7 p-type collector layer 8 first guard ring layer 9, 51, 81, 91 n-type second semiconductor layer 10 first main electrode 11 second main electrode 12, 27 IGBT unit 13, 28 IGBT region 14, 26 interlayer insulating film 15 cathode electrode 16 trench 29 second guard ring layer 30 guard Ring electrode 42 n-type third semiconductor layer 71 Conductor 82 Insulating film 100, 200, 300, 400, 500, 600, 700 Semiconductor device C1, C2, C3 Current path in off state

Claims (8)

A first conductivity type base layer having a first surface and a second surface facing the first surface;
A second conductivity type base layer selectively formed on the first surface of the first conductivity type base layer; and a surface of the second conductivity type base layer opposite to the first conductivity type base layer. A first conductive type emitter layer formed, a gate electrode formed on the first conductive type base layer, the second conductive type base layer, and the first conductive type emitter layer via a gate insulating film; A first conductivity type first semiconductor layer having an impurity concentration higher than that of the first conductivity type base layer formed on the second surface of the first conductivity type base layer; and the first conductivity type first semiconductor layer. An IGBT region having a plurality of IGBT units, the second conductivity type collector layer formed on the surface opposite to the first conductivity type base layer;
A second conductivity type first guard ring layer formed deeper than the second conductivity type base layer on the first surface of the first conductivity type base layer so as to surround the IGBT region;
A first main electrode formed on a surface of the second conductivity type collector layer opposite to the first conductivity type first semiconductor layer;
A second main main body electrically connected to the first conductive type emitter layer, the second conductive type base layer and the second conductive type first guard ring layer and insulated from the gate electrode by an interlayer insulating film. Electrodes,
The first main electrode reaches the first main electrode from the first surface of the first conductive type base layer around the IGBT region and the second conductive type first guard ring layer, and is electrically connected to the first main electrode. A first conductivity type second semiconductor layer connected to
The second conductive type first guard ring layer and the first conductive layer are formed on a first surface of the first conductive type base layer between the second conductive type first guard ring layer and the first conductive type second semiconductor layer. The second conductivity type second guard ring layer formed apart from the conductivity type second semiconductor layer, or the first conductivity between the second conductivity type first guard ring layer and the first conductivity type second semiconductor layer. Extending toward the first conductive type second semiconductor layer connected to the second conductive type first guard ring layer on the first surface of the mold base layer and formed shallower than the second conductive type first guard ring layer A second conductivity type RESURF layer,
Comprising
The first conductivity type first semiconductor layer is at least from a position immediately below the second conductivity type first guard ring layer to a portion where the first conductivity type second semiconductor layer reaches the first conductivity type first semiconductor layer. A power semiconductor device, wherein the region is a first conductivity type third semiconductor layer having an impurity concentration higher than that of the first conductivity type first semiconductor layer. A first conductivity type base layer having a first surface and a second surface facing the first surface;
A second conductivity type base layer selectively formed on the first surface of the first conductivity type base layer; and a surface of the second conductivity type base layer opposite to the first conductivity type base layer. A first conductive type emitter layer formed, a gate electrode formed on the first conductive type base layer, the second conductive type base layer, and the first conductive type emitter layer via a gate insulating film; A first conductivity type first semiconductor layer having an impurity concentration higher than that of the first conductivity type base layer formed on the second surface of the first conductivity type base layer; and the first conductivity type first semiconductor layer. An IGBT region having a plurality of IGBT units, the second conductivity type collector layer formed on the surface opposite to the first conductivity type base layer;
A second conductivity type first guard ring layer formed deeper than the second conductivity type base layer on the first surface of the first conductivity type base layer so as to surround the IGBT region;
A first main electrode formed on a surface of the second conductivity type collector layer opposite to the first conductivity type first semiconductor layer;
A second main main body electrically connected to the first conductive type emitter layer, the second conductive type base layer and the second conductive type first guard ring layer and insulated from the gate electrode by an interlayer insulating film. Electrodes,
The first conductive electrode reaches the first conductive type first semiconductor layer from the first surface of the first conductive type base layer around the IGBT region and the second conductive type first guard ring layer, and the first main electrode. A first conductivity type second semiconductor layer electrically connected to
A power semiconductor device comprising:   At least part of the first conductive type second semiconductor layer further penetrates the first conductive type first semiconductor layer and the second conductive type collector layer and reaches the first main electrode to be electrically connected. The power semiconductor device according to claim 2, wherein the power semiconductor device is a power semiconductor device.   A conductor that passes through the first conductive type second semiconductor layer from the surface of the first conductive type second semiconductor layer on the second main electrode side, reaches the first main electrode, and is electrically connected The power semiconductor device according to claim 2, further comprising:   3. The power semiconductor device according to claim 2, further comprising a buried layer formed on the surface of the bottom and side walls of the trench formed in the first conductive type second semiconductor layer via an insulator film. . A first conductivity type base layer having a first surface and a second surface opposite to the first surface; and a second selectively formed on the first surface of the first conductivity type base layer. A conductive type base layer; a first conductive type emitter layer formed on a surface of the second conductive type base layer opposite to the first conductive type base layer; the first conductive type base layer; and the second conductive type. A gate electrode formed on the first base layer and the first conductive type emitter layer via a gate insulating film, and a first conductive type base formed on the second surface of the first conductive type base layer A first conductivity type first semiconductor layer having a higher impurity concentration than the layer; a second conductivity type collector layer formed on a surface of the first conductivity type first semiconductor layer opposite to the first conductivity type base layer; A plurality of IGBT regions having a plurality of IGBT units, and the plurality The first surface of the first conductivity type base layer so as to surround each of the IGBT region, and the second conductivity type base layer a plurality of second conductivity type first guard ring layer which is deeper than,
A first main electrode formed on a surface of the second conductivity type collector layer opposite to the first conductivity type first semiconductor layer;
A second main main body electrically connected to the first conductive type emitter layer, the second conductive type base layer and the second conductive type first guard ring layer and insulated from the gate electrode by an interlayer insulating film. Electrodes,
The plurality of IGBT regions and the plurality of second conductivity type first guard ring layers are individually surrounded to reach the first semiconductor layer from the first surface of the first conductivity type base layer, and the first A first conductivity type second semiconductor layer electrically connected to the electrode of
A power semiconductor device comprising:   The second conductive type first guard ring layer and the first conductive layer are formed on a first surface of the first conductive type base layer between the second conductive type first guard ring layer and the first conductive type second semiconductor layer. The second conductivity type second guard ring layer formed apart from the conductivity type second semiconductor layer, or the first conductivity between the second conductivity type first guard ring layer and the first conductivity type second semiconductor layer. Extending toward the first conductive type second semiconductor layer connected to the second conductive type first guard ring layer on the first surface of the mold base layer and formed shallower than the second conductive type first guard ring layer The power semiconductor device according to claim 2, further comprising a second conductivity type RESURF layer. The first conductivity type first semiconductor layer is at least from a position immediately below the second conductivity type first guard ring layer to a portion where the first conductivity type second semiconductor layer reaches the first conductivity type first semiconductor layer. 8. The power semiconductor device according to claim 2, wherein the region is a first conductive type third semiconductor layer having an impurity concentration higher than that of the first conductive type first semiconductor layer. 9.

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