JPH01265569A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve an IGBT in a latch-up resistance by a method wherein a ratio of a length of a well to a width of a channel of a well layer section just under a source layer is made extremely small to be less than a specified value. CONSTITUTION:An n-type body layer 2 is formed on an n-type drain layer 1, and a p-type well layer 3 is selectively formed on the body layer 2. An n-type source layer 4 is selectively formed on the well layer 3 to form two or more unit cells. In an IGBT structured as mentioned above, the ratio of the well length to the channel width of the well layer 3 section just under the source layer 4 is made extremely small to be less than 5X10<-6> or so. By these processes, a unit cell of the IGBT is micronized and a bias region is made the most adequate, so that a parasitic thyristor can be effectively improved in a latch-up resistance. And, the IGBT can be improved in a short-circuit resistance by restraining a saturation current from increasing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device, particularly an IGBT, and more specifically to improving latch-up resistance in an IGBT.

[Conventional technology]

The basic configuration of a conventional IGBT of this type is shown in FIGS. 6 to 8.

That is, in the configuration of the conventional IGBT shown in FIG. 6, the symbol l represents a p-type drain layer, 2 represents an n-type body layer formed on this p-type drain layer l, and 3 represents this n-type body layer. A p-type well layer 4 is selectively formed on the p-type body layer 2, and an n-type source layer 4 is selectively formed within the p-type well layer 3. Furthermore, 5 is a gate oxide film, 6, 7 .
and 8 are a drain 'rrt, a pole, a source electrode, and a gate electrode, respectively.

As is well known, this IGBT also has a structure in which a plurality of unit cells are connected in parallel, similar to the power MOSFET.

[The problem that the invention aims to solve]

However, in the IGBT with this conventional configuration,
Holes are injected from the p-type drain layer l side of the vertical MO3FET into the n-type body layer 2 in the high resistance region, thereby modulating the conductivity of the n-type body layer 2 and lowering its resistance value. Because it is a normal MOSFET
It has the advantage that the voltage drop in the on state can be lowered compared to the on-state, and since the on-resistance (resistance value in the on-state) can be lowered in this way, the chip area can be reduced. This is particularly noticeable in the case of high-voltage device products that require a high resistance value of the n-type body layer 2. For example, in a tooov class device configuration, the chip size can be reduced to an area of about 1716. It is.

On the other hand, as shown in FIG. 6, this IGBT has an n-type source layer 4. P-type well layer 3. n-type body layer 2
．． There is a parasitic thyristor consisting of four layers, ie, a p-type drain layer l, and when this parasitic thyristor is turned on, the original function of the IGBT is lost, so it is necessary to suppress this parasitic effect.

The most desirable means for this purpose is to lower the lateral resistance R of the p-type base region directly under the n-type source layer 4, and in the conventional case, this lateral resistance R
In order to lower this, a structure in which a high concentration p-type well layer 31 is provided directly under the n-type source layer 4 as shown in FIG. As shown, a part of the n-type source layer 4 is removed and that part is used as a bypass region 41 (Japanese Patent Laid-Open No. 60-25465).
However, the most effective means is to reduce the total lateral resistance 1 by miniaturizing the unit cell of the IGBT.

Furthermore, on the other hand, this IGBT is generally mainly used in inverter devices, etc., and even if the inverter device etc. is short-circuited, it is required that the device will not be destroyed, and the short-circuit resistance is This short-circuit withstand capacity is determined by the current and voltage applied to the device.
It is determined by the product of time, and in particular, in the case of this type of IGBT, since the chip area is relatively small, this short circuit tolerance becomes severe.

The voltage for one hour, which determines the short-circuit withstand capability, is basically determined by the equipment conditions, and fortunately, the current has a self-control function because it enters a saturated state due to a short circuit. , this saturation current ICE (
The short circuit withstand capability can be improved by setting the saturation current IcE(sat) low in this IGBT.
is the following formula (1).

1 (sat)=%(:ox, W, VL(Vas-
Vas(th))"(+)However, the channel width W per unit area v is determined by the latch-up voltage, so when making the miniaturized structure, the channel width W becomes relatively large. Therefore, the saturation current Ic+=(sat) also became large.

This invention was made to solve these conventional problems, and its purpose is to miniaturize the device configuration to improve latch-up resistance, and to
This suppresses parasitic effects and reduces the saturation current 1c.
I tried not to increase E(sat). This type of semiconductor device, this S, is to provide an IGET.

[Means to solve the problem]

In order to achieve the above object, a semiconductor device according to the present invention includes a drain layer of a first conductivity type, a second conductivity type formed on the drain layer, and a second conductivity type drain layer formed on the drain layer. = Body layer of shape.

A well layer of a first conductivity type selectively formed on this body layer and a source layer of a second conductivity type selectively formed within this well layer are respectively provided to constitute a plurality of unit cells. The IGBT is characterized in that: 1) the ratio of the well length to channel width in the well layer portion immediately below the η source layer is miniaturized to approximately 5×1O−6 crn” or less;

[Function] Therefore, in the device of this invention, by miniaturizing the unit cell in the IGBT and optimizing the bypass region, it is possible to improve the latch-up resistance of the parasitic thyristor and suppress the increase in saturation current. ,As a result,
IG with improved short-circuit resistance and stable operation even at high temperatures exceeding 150°C.
BT is obtained.

〔Example〕

Hereinafter, a semiconductor device according to the present invention, hereinafter referred to as an IGBT
The embodiment will be described in detail with reference to FIGS. 1 to 5.

FIG. 1 is a cross-sectional perspective view schematically showing the general configuration of an IGBT to which an embodiment of the device of the present invention is applied.
In the illustrated example configuration, the same reference numerals as in the conventional example configuration shown in FIG. 8 represent the same or corresponding parts.

That is, in this case as well, the I
In the configuration of the GBT, reference numeral 1 indicates a p-type drain layer, 2 indicates an n-type body layer formed on the p-type drain layer 1, and 3 indicates a layer selectively formed on this n-type body layer 2. p
4 is an n-type source layer selectively formed in the p-type well layer 3, 5 is a gate oxide film, 6, 7 . g and 8 are a drain electrode, a source electrode, and a gate electrode, respectively, and 41 is a region where a part of the n-type source layer 4 is removed, that is, a bypass region, and this I
GBT also has a structure in which a plurality of unit cells are connected in parallel, as in the case of power MOS FET.

In addition, FIG. 2 shows the well length a/channel width W in the device configuration in this embodiment and the saturation current 1c per unit area.
, (sat) and the latch-up current IL.

In other words, as is clear from Fig. 2, the well length a/
It is shown that when the value of the channel depth reaches a local level, the latch-up current IL increases to about twice, while the saturation current ICE (sat) increases only about twice. Also, regarding the latch-up current [1,
For that value at an operating temperature of 25°C, this is 125°C.
At an operating temperature of
It will be about 1O. Also, in well length a/channel depth <5, latch-up current rt, (operating temperature 150°C)> saturation current Ice (Sat) (operating temperature 15
0℃), it becomes a non-latch type, and in this work, this a/w
The smaller the value, the lower the IL (operating temperature 150℃)
-IcF: (sat) (operating temperature 150℃) difference becomes large, but if the value of a/w becomes too small, the value of ICE (sat) will exceed the short circuit limit and its destruction will become a problem. becomes.

Moreover, FIG. 3 shows the bypass width Z/ in the same device configuration.
Well length a/channel rl when changing channel width W
1 is a graph showing the relationship between 1w and saturation current lct, (sat).

As is clear from FIG. 3, even if the well length a/channel width W is small, the bypass width Z/
By increasing the channel width W, the saturation current tcg(s
at) decreases, so the short circuit limit is no longer exceeded. On the other hand, increasing the channel width W of the bypass width 27 is because - part of the current flowing through the p-type well layer 4 directly under the n-type source layer 4 flows through the bypass region 41. The current flowing through the p-type well layer 4 directly under the n-type source layer 4 is effectively reduced, which has the effect of improving latch-up resistance, and there is no bypass layer 41, z/w=0.
In the case of 3.5X 10-'crn”<
If a/w < 5X 1O-6crn' is required and also z/wJ, 75, then a/w is: 1. sx
If you set z/w-0,5, a/w can be lowered to 1.5X In-'C, and even if you set z/w-0,5, ,a/
Since the channel width W is the same as when w is 4 times the value, Vce(sat) etc. basically do not change, and in this S, well length a/channel rl-] w is 5x
It is preferable to refine the structure to about 10-6 cd or less.

In addition, FIG. 4 shows an I
FIG. 4 is a cross-sectional perspective view schematically showing the general structure of a GBT, and the device of the embodiment shown in FIG. This structure includes an n-type buffer layer 21 for suppressing injection, and the same effects as the device of the embodiment shown in FIG. 1 can be obtained.

In each of the embodiments shown in FIGS. 1 and 4, the IGBT unit cells each have a stripe structure. As shown in b) and (c), it is of course applicable to cases where each unit cell has a square, polygonal, circular, etc. structure, and this method also applies to n-channel Although we have explained the type IGBT, it is also a p-channel type IGBT in which all the layers are of opposite conductivity type.
The same applies to BT.

(Effects of the Invention) As detailed above, according to the present invention, a drain layer of a first conductivity type, a body layer of a second conductivity type formed on this train layer, and a body layer selectively formed on this body layer are provided. The first formed
In an IGBT in which a plurality of unit cells are configured by providing a well layer of a conductivity type and a source layer of a second conductivity type selectively formed in the well layer, the well layer portion immediately below the source layer. By miniaturizing the unit cell in this IGBT and optimizing its bypass area, , it is possible to effectively improve the latch-up resistance of the parasitic thyristor, and to sufficiently suppress the increase in saturation current,
As a result, the short-circuit tolerance of the IGBT is significantly improved, and an IGBT that can operate stably even at high temperatures can be realized.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional perspective view schematically showing the general configuration of an IGBT to which an embodiment of the device of the present invention is applied, and FIGS. 2 and 3 show the saturation current rcg in the device of the embodiment shown in FIG.
(sat), latch-up current 11. and well length a
/Graph showing the relationship with channel width W. and a graph showing the relationship between the saturation current 1c, (sat,) and the well length a/channel width W with the bypass width Z/channel width W as a parameter. FIGS. 5(a) to 5(c) are explanatory diagrams showing examples of partial configurations in each of these embodiment devices;
Moreover, FIGS. 6 to 8 show the conventional IG
FIG. 3 is a cross-sectional view schematically showing the general configuration of BT. ! ... n-type drain layer, 2... n-type body layer,
3...p-type well layer, 4...n-type source layer, 4
1... Bypass region, 5... Gate oxide film, 6
...Dray electrode, 7...Source electrode, 8...
・Gate electrode agent Masu Oiwa Miscellaneous work 1 Figure 1; nuL-=Shi/layer 6; To...νA/house No.L 7: Source 8; Ga'-L 'E, &9; Drain IH (Cm2)

Claims (1)

[Claims] a drain layer of a first conductivity type; a body layer of a second conductivity type formed on the drain layer; a well layer of the first conductivity type selectively formed on the body layer; In an IGBT in which a plurality of unit cells are constituted by providing source layers of the second conductivity type formed in ×10^-^6cm^
A semiconductor device characterized by being miniaturized to about 2 or less.