JP2572210B2 - Vertical power MOS field effect semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a vertical power MOS field-effect semiconductor device, and more particularly to a vertical power MOS field-effect semiconductor device having improved breakdown strength.

[Prior Art] Conventionally, there has been a semiconductor device of this type shown in FIG. FIG. 5 is a sectional view of a conventional power MOS field effect transistor (hereinafter, the field effect transistor is referred to as FET). First, the configuration of this device will be described.
A first conductivity type high concentration drain region 1b which is a semiconductor substrate is formed on the surface of the drain electrode 8, and a first conductivity type low concentration drain region 1a is formed on the surface of this region.
On the surface of the low-concentration drain region 1a of the first conductivity type, a plurality of second conductivity type semiconductor regions 2 of a conductivity type opposite to this region are formed at an interval. Two source regions 3 of the first conductivity type are formed with a partial interval. Each second conductivity type semiconductor region 2 has a convex portion 21, and 7 is a channel forming region. Part of the surface of the source region 3 of each first conductivity type and a second region between these regions
A source electrode 6 is formed on the surface of the conductive semiconductor region 2, and the source electrode 6 extends right and left from the source electrode 6 parallel to the semiconductor substrate 1b. Further, the surface of the low-concentration drain region 1a of the first conductivity type between the second conductivity type semiconductor regions 2,
An insulating film 4 is formed on the surface of each semiconductor region 2 of the second conductivity type between the low-concentration drain region 1a of the conductivity type and the source region 3 of the first conductivity type, and a part of the surface of the source region 3 of each first conductivity type. Have been. A gate electrode 5 is formed on the surface of the insulating film 4, and a source electrode 6 is formed on the surface of the gate electrode 5 via the insulating film 4 so as to extend in parallel with the semiconductor substrate 1b. The power MOSFET has a structure in which many such basic units are connected in parallel.

Next, the operation of this device will be described. When a gate voltage is applied between the gate electrode 5 and the source electrode 6 in a state where a drain voltage is applied between the drain electrode 8 and the source electrode 6, a channel is formed in the channel formation region 7, and a channel is formed between the drain electrode 8 and the source electrode 6. Drain current flows. At this time, by controlling the gate voltage applied between the gate electrode 5 and the source electrode 6, the drain electrode 8
And the drain current flowing between the source electrode 6 can be controlled. Second conductivity type semiconductor region 2 by source electrode 6
The short circuit between the first conductive type and the source region 3 is indispensable for fixing the potential of the channel forming region 7.

Power MOSFETs have the advantage that high-speed operation is possible because the injection and accumulation of minority carriers are basically not a problem. On the other hand, bipolar (hereinafter abbreviated as BIP) transistors and thyristors have high conductivity due to conductivity modulation by minority carriers. Because there is no mechanism to reduce the ON resistance in the resistance area,
ON resistance is larger than BIP element. For this reason, power MOS
In the FET, an increase in the peripheral length of the active portion and a reduction in the thickness of the high-resistance region 1a, which is a low-concentration drain region of the first conductivity type, are pending for increasing the current capacity. It can be said that the effective design is to make the high-resistance region 1a as thin as the breakdown voltage characteristics of the semiconductor element allow. Nevertheless, the reason why the convex portion 21 exists is as follows.

FIG. 6 is a diagram showing output characteristics of a conventional power MOSFET. If there is no protrusion 21 in the second conductivity type semiconductor region 2, the semiconductor element tends to be destroyed instantaneously when a breakdown current flows. Hereinafter, this destruction mode will be described. FIG.
FIG. 7B is a cross-sectional view of a basic structural unit of the MOSFET when there is no convex portion 21, and FIG. 7B is a diagram showing an equivalent circuit of FIG. 7A. When the voltage applied between the source and the drain is increased to reach the breakdown voltage value of the low-concentration drain region 1a and the second conductivity type semiconductor region 2, a breakdown current indicated by an arrow in FIG. 7A flows. At both ends of the source region 3, as shown in FIG. 7B, the structure is such that a BIP transistor is substantially parasitic. Therefore, the current J _c flowing under the source region 3 is
It flows out of the source electrode 6 via the resistor Ra, but when the condition of the following equation (1) is satisfied, a state in which the parasitic transistor becomes conductive appears.

0.6V <J _c × Ra (1) This phenomenon firstly occurs in a very small region of the power MOSFET, and after the conduction, a stable state cannot be obtained and a blocking oscillation state is entered. In such a situation, the semiconductor element is destroyed in a short time. If the projection 21 is formed in the second conductivity type semiconductor region 2, the breakdown will occur only in the center of the second conductivity type semiconductor region 2, and the breakdown current below the source region 3 is reduced. That is, the resistance Ra under the source region 3 is reduced. As described above, the conventional structure can cope with the breakdown phenomenon between the source and the drain (generally, the temporary breakdown phenomenon of a semiconductor element).

[Problems to be Solved by the Invention] Generally, it is said that MOSFETs do not have a secondary destruction phenomenon that is a serious problem in BIP transistors. However, a vertical power MOSFET according to the present invention has a parasitic effect. There is a problem that a secondary breakdown phenomenon occurs due to the presence of the transistor. This destruction phenomenon is likely to occur in a high-voltage, high-speed switching operation, but does not cause a problem when the phase of the voltage applied to the semiconductor element is out of phase with the current, as in a normal switching regulator. That is, this phenomenon occurs for the first time in an operation mode in which a high voltage is applied while a current flows through a semiconductor element. For example, when high-speed switching is performed by the inverter circuit shown in FIG. 8, this secondary destruction phenomenon easily occurs. In order to control the current flowing to the load (L) 50 in this circuit, a pair of power MOSFETs 40a and 40d arranged diagonally or a power MOS
This is possible by turning on / off the pair of FETs 40b and 40c at an arbitrary ratio. Since the current flowing through the load (L) 50 is continuous, the power MOSFETs 40a and 40d are turned off and the power
When turning MOSFETs 40b and 40c ON and OFF, power MOSFETs 40b and 40c
Is OFF, the current flowing through the load (L) 50 is the power MOS
The power returns to the power supply 60 through the freewheel diodes 41a and 41d connected in anti-parallel with the FETs 40a and 40d, respectively. This freewheeling diode requires a high-speed one, so the power
Although another element is connected to the MOSFET chip, as shown in FIG. 7B, the power MOSFET has a structure in which a diode is built in. For this reason,
The part of the return current that should flow through the return diode is power
It will flow through the MOSFET chip. Subsequent to this state, the freewheeling diodes 41a and 41d on the (a) and (d) sides after the ON signal is input to the power MOSFETs 40b and 40c in the OFF state.
Voltage Vd waveform and the current Im flowing through the power MOSFETs 40b and 40c
FIG. 9 shows an example of the waveform. Power MOSFET (especially when the switching speed of the power MOSFET is not limited)
When the switches 40b and 40c are turned ON, the recovery currents of the return diodes 41a and 41d on the (a) and (d) sides increase substantially linearly. This rate of increase is determined by the ratio V _cc / L ₀ of the inductance L ₀ of the wiring and the power supply voltage V _cc. During no recovery, the return diodes 41a and 41d have extremely low impedance values, and the power MOSFETs 40b and 40c hold the power supply voltage. That is, the power MOSFETs 40b and 40c are exposed to a state where a large current flows while the power supply voltage is applied (this state is generally called a short-circuit state). (A),
A voltage starts to be rapidly applied to the element on the side (d) in the middle of the recovery period, and takes an excessive peak value when the recovery current is attenuated. Such a short-circuit condition may cause a remarkable power loss, particularly when the recovery characteristics of the freewheeling diode are poor in high-frequency operation, and may cause destruction of the power MOSFET. Typically, this mode of destruction is mainly caused by an increase in temperature due to heat generation, and is not a secondary destruction phenomenon.

Secondary destruction, which is a problem in the power MOSFET, occurs in the MOSFETs on the (a) and (d) sides described above. The necessary conditions for destruction of the MOSFETs on the (a) and (d) sides are as follows.

1) Return current flows through the MOSFET. (No breakdown occurs if a diode is connected in series with the MOSFET so that the freewheeling current flows exclusively through the freewheeling diode.) 2) The recovery time of the freewheeling current is longer in the MOSFET than in the freewheeling diode. (No damage occurs if a normal type is used for the freewheeling diode instead of a high-speed diode.) 3) The voltage applied during the recovery operation rises steeply. (Destruction does not occur if the voltage rise is suppressed by adding a snubber.) These are all basically the same as the secondary destruction phenomenon that becomes a problem when a BIP transistor is used for an inverter. The secondary destruction phenomenon in this mode can be explained as follows. Even a small amount of current flows through the power MOSFET during reflux,
It is assumed that the junction in the MOSFET cannot be fully recovered until a steep voltage is applied during recovery. At this time, the minority carriers remaining in the high resistance region 1a of the drain are accelerated by the electric field at the same time when the voltage is applied, and move to the second conductivity type semiconductor region 2 on the source side. If the rise of the high voltage is extremely steep, the avalanche multiplication of the minority carrier by the electric field may not be ignored until all the remaining minority carriers reach the second conductivity type semiconductor region 2. The minority carriers moving to the second conductivity type semiconductor region 2 correspond to the base current being supplied to the parasitic transistors formed at both ends of the source region 3. That is, if the avalanche multiplication phenomenon of the minority carrier satisfies the condition shown by the expression (1), the parasitic transistor becomes conductive. When the parasitic transistor is turned on, a new carrier is supplied to the high-resistance region 1a of the drain, so that a positive feedback loop can be established in which the carrier is injected again into the base region of the parasitic transistor by an avalanche multiplication phenomenon. The existence condition of this positive feedback loop basically depends on the electric field region in the high resistance region 1a of the drain, the resistance Ra value between the emitter and base of the parasitic transistor, and the DC current amplification factor _hFE value. That is, when the electric field strength is high and the resistance Ra and the DC current amplification factor _hFE are large, this positive feedback can easily occur. Once in the positive feedback state,
Unless the power supply voltage decreases and the electric field intensity decreases, conduction in this region does not stop. In this situation, the local region of the semiconductor element operates at a high current density while a high voltage is applied, and the semiconductor element is destroyed directly due to an increase in temperature due to heat generation immediately. As a result, the projection 21 of the second conductivity type semiconductor region 2 is effective in reducing such a phenomenon in the following point.

1) The part where the avalanche multiplication phenomenon occurs is located farther from the place where the parasitic transistor operation easily occurs.

2) Reduce the resistance Ra.

However, this protrusion can also have an adverse effect. In order to suppress the avalanche multiplication phenomenon of the parasitic transistor, it is only necessary to make the projection deep, but in this case, the effect of moving the avalanche multiplication phenomenon occurrence part away from the part where the parasitic transistor operation is likely to occur is reduced. Also, if you make the projection deeper,
The width occupied by the projections is increased, the area of the basic unit is increased, and the active region as a MOSFET is reduced.

In addition, a life time killer may be inserted in the built-in diode in order to cope with the case where the MOSFET is used for high-frequency operation.In this case, the life of the MOSFET is reduced because the MOSFET is close to the diode. The time is also reduced, and the operation characteristics deteriorate.

Also, in the case of a BIP transistor, there is an advantage that it does not operate as high as a MOSFET in the first place.However, by applying a sufficient reverse bias between the emitter and the base, the current flowing through the transistor at the time of reflux is cut off. You can escape the secondary destruction of the mode. However, the power MOSFET does not have a function of actively shutting off the current at the time of reflux unlike the BIP transistor. For this reason, it cannot be said that the conventional vertical power MOSFET has a serious defect as a general-purpose power element. Normally, a static drain-source voltage V _DSS is used for the voltage rating of the MOSFET. However, since the above operation is performed by including a parasitic transistor, the transistor has a static voltage characteristic V _DSS. not _CEO, in the same manner as defined in V _{CEO (SUS)} is dynamic characteristic, for example, V _CEO of the parasitic transistor (
It should be specified with a dynamic characteristic equivalent to _SUS ), in which case it is much lower than the current MOSFET voltage rating.

The present invention has been made to solve such a problem, and an object of the present invention is to provide a vertical power MOS field-effect semiconductor device having improved secondary breakdown strength.

[Means for Solving the Problems] A vertical power MOS field-effect semiconductor device according to the present invention includes a semiconductor substrate of a first conductivity type having a high impurity concentration and having a first main surface and a second main surface. A first conductive type semiconductor layer having a low impurity concentration and having a first main surface in contact with the first main surface of the first conductive type semiconductor substrate and a second main surface opposed to the first main surface; A part of the second main surface of the first conductivity type semiconductor layer is formed such that the depth to the bottom is uniform and the edges are adjacent to each other and opposed to each other via the first conductivity type semiconductor layer. A first second conductivity type semiconductor region provided, and a first conductivity type provided on a surface of the first second conductivity type semiconductor region so as to extend at a distance from an edge of the region. Semiconductor region, and the first conductive type semiconductor region and the second conductive surface of the first conductive type semiconductor layer. A gate electrode disposed on the surface of the first second conductivity type semiconductor region sandwiched between the first conductivity type semiconductor layer opposed to the region via an insulating film, and a first second conductivity type semiconductor region. The semiconductor device has a bottom portion closer to the first main surface of the first conductivity type semiconductor layer than a bottom portion of the semiconductor region and surrounds the plurality of first second conductivity type semiconductor regions through a part of the first conductivity type semiconductor layer. A second second conductivity type semiconductor region arranged on the second main surface of the first conductivity type semiconductor layer, and a first conductivity type semiconductor layer extending along the second second conductivity type semiconductor region. A gate electrode wiring provided on the second main surface of the first semiconductor device via an insulating film and connected to the gate electrode; a first second conductivity type semiconductor region; a first conductivity type semiconductor region; The gate electrode and the first conductivity type semiconductor are short-circuited to the two conductivity type semiconductor region and are inserted into the gate electrode wiring. A first main electrode disposed over the surface and the insulating layer, a second main electrode disposed on the second major surface of the semiconductor substrate, those having a.

[Operation] In the vertical power MOS field-effect semiconductor device according to the present invention, the edge of the first conductive semiconductor layer having a low impurity concentration is partially formed on the second main surface via the first conductive semiconductor layer. A first layer having a uniform depth to the bottom so as to be adjacent to and opposed to each other;
A plurality of second conductivity type semiconductor regions, and the first
A first conductivity type semiconductor region is provided on the surface of the conductivity type semiconductor region so as to extend at a distance from an edge of the region, and a second conductivity type semiconductor region and a second conductivity type semiconductor layer of the first conductivity type semiconductor layer. A gate electrode is disposed on the surface of the first second conductivity type semiconductor region sandwiched between the first conductivity type semiconductor layer opposed to the first conductivity type semiconductor region on the main surface of the first conduction type semiconductor region via an insulating film. And a bottom portion closer to the first main surface of the first conductivity type semiconductor layer than a bottom portion of the first second conductivity type semiconductor region. Is formed on the second main surface of the first conductivity type semiconductor layer so as to surround the second conductivity type semiconductor region.
Is disposed on the second main surface of the first conductive type semiconductor layer along the second second conductive type semiconductor region with a gate electrode via an insulating film. A gate electrode wiring is provided, and the first second conductivity type semiconductor region, the first conductivity type semiconductor region, and the second second conductivity type semiconductor region are short-circuited and the gate is formed so as to enter the gate electrode wiring. Since the first main electrode is provided via the electrode and the surface of the first conductivity type semiconductor layer and the insulating layer, the return current flowing to the portion functioning by the electric field effect flows also to the diode region and functions by the electric field effect. The return current flowing near a part of the parasitic transistor is reduced, the area ratio of the diode region is increased while the MOS field-effect semiconductor element region is widened, and the MOS field-effect semiconductor element region can be arranged at high density.

[Embodiments] From the above description, in order to improve the secondary breakdown strength of the power MOSFET, a) reduce the intensity of the electric field applied to the parasitic transistor.

b) The resistance Ra between the emitter and base of the parasitic transistor
The value and the DC current gain _hFE must be reduced.

c) Reduce the current flowing near the parasitic transistor during reflux.

It turns out that this is effective. D) The current flowing in the diode portion is desirably small because it becomes a power loss source even if it is not related to secondary destruction apart from the parasitic transistor.

The first object of the present invention is to provide the effect of c), but it also has the effects of a) and d). Also, by separating the convex part in the conventional structure from the MOSFET part,
The degree of integration of the MOSFET section increases, and the high current characteristics are improved.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that, in the following description of the embodiments, description of portions that are the same as those in FIGS. 5 to 9 will be omitted as appropriate.

FIG. 1 is a sectional view of a vertical power MOS field-effect semiconductor device on which the present invention is based. The configuration of this device is different from that of the device of FIG. 5 in that another second conductivity type semiconductor region 9 of a diode region is newly separated from the MOSFET portion on the surface of the lightly doped drain region 1a of the first conductivity type. And MO
The point is that the SFET portion is formed deeper than the second conductivity type semiconductor region 2 and that the protrusion 21 is eliminated. In such a structure, the return current flowing through the MOSFET part is reduced by the diode region 9.
Therefore, the size is smaller than that of the conventional field effect type semiconductor device. In addition, since there is no projection 21 of the conventional second conductivity type semiconductor region 2, a return current flows only at the very center of the MOSFET portion, and the effect on the parasitic transistor is substantially reduced. Further, the fact that the MOSFET portion is easily broken at a high voltage has a favorable effect as described below. That is, when a high voltage is applied, most of the voltage is held in the first conductivity type low concentration drain region 1a. If the width of this region is wide, the voltage effect due to its resistance increases, so in a typical high-voltage element, the width of the low-concentration drain region 1a is much lower than the rated voltage, and the depletion layer is of the first conductivity type. To reach the high-concentration drain region 1b. Therefore, in a voltage region where secondary breakdown is a problem, the depletion layer extends to the entire region of the high-concentration drain region 1b. Since the breakdown of the junction occurs at the place where the electric field is highest, it is determined by the distance between the diode region 9 having the shortest interval and the high-concentration drain region 1b. For example, in the breakdown mode as shown in FIG. 6, since the breakdown current flows only in the diode portion, the breakdown strength is determined by the breakdown strength of the diode, and secondary breakdown of the MOSFET portion does not matter. This is basically the same as the relationship between the convex portion 21 and the high-concentration drain region 1b in the conventional field-effect semiconductor device. However, according to this embodiment, the degree of freedom in setting the depth of the diode region 9 is great. It is easy to set an effective withstand voltage value. Increasing the depth of the diode region 9 lowers the withstand voltage of the semiconductor device as a whole, but this does not mean that its characteristics have deteriorated, but that the protection function has been provided so that the semiconductor device is not exposed to a dangerous voltage. Should be. The conventional projection 21 is destroyed when its depth to the low-concentration drain region 1a is increased, because the effective area of the semiconductor element is significantly reduced and the effect of the return current on the parasitic transistor is increased. Although a sufficient function could not be achieved in terms of strength, this embodiment can avoid the conventional limitation.

Although the protrusion 21 is not shown in FIG. 1, the protrusion has an effect of lowering R, so that the protrusion having the best overall characteristics in a certain range shallower than the diode region 9 is obtained. It is considered that there are 21 sizes, and this embodiment is not limited to the presence or absence of the protrusion.

In addition, the conventional basic unit depends on the area occupied by the protrusion.
Although it was difficult to reduce the size to about 60 μm square or less, according to this embodiment, the basic unit can be reduced to about 40 μm square, and the current capacity can be improved by 50%.

FIG. 2 shows a similar vertical power base on which the invention is based.
FIG. 3 is a cross-sectional view of a MOS field-effect semiconductor device. In this case, the depth of the diode region 9 to the low-concentration drain region 1a is not particularly limited, and is in contact with the diode region 9 and has the same conductivity type as the low-concentration drain region 1a of the first conductivity type and has a higher impurity concentration. A high high impurity concentration region 10 is formed. First
In the embodiment shown in the drawing, the breakdown voltage of the MOSFET portion and the diode region 9 is made different by the difference in the width of the low-concentration drain region 1a, whereas in this embodiment, the same effect is obtained by the difference in the impurity concentration. Except for this point, the principle is basically the same as that of the embodiment shown in FIG.

FIG. 3A is a vertical power MOS according to an embodiment of the present invention.
FIG. 3B is a partial sectional view taken along line XX of FIG. 3A, and FIG. 3C is a partial sectional view taken along line YY of FIG. 3A of the field-effect semiconductor device. Reference numeral 12 denotes a gate electrode wiring, and reference numeral 30 denotes a gate bonding pad. As shown in FIG. 3C, it is most efficient that the diode region 9 is formed immediately below the source bonding pad 31.
As shown in FIG. 3B, it can be formed also in a portion below the gate electrode wiring 12. Thus, the ratio of the diode region to the MOSFET portion can be increased, and the effect of the return current on the MOSFET portion can be reduced. Therefore, the stability of the field-effect semiconductor device during operation at high voltage is improved. It is generally not preferable to increase the area of the built-in diode, especially when a high-speed freewheeling diode is connected to the outside, but since the built-in diode is high-speed, the built-in diode can be returned without connecting the external freewheeling diode. It becomes necessary when it is used as a diode.

FIG. 4A shows another embodiment of the present invention.
FIG. 4B is a cross-sectional view of a basic structural unit of the MOS field-effect semiconductor device, and FIG. 4B is a partial top view of a portion Z in FIG. 4A. The diode region 9 comprises a peripheral deep diode region 9a and a shallow diode region 9b inside the peripheral region, and the connection between the diode region 9 and the source electrode 6 is made by a narrow electrode forming portion 110 from substantially the center of the shallow diode region 9b. Have been. Since the shallow diode region 9b becomes a resistor that is in series with the diode portion, in the circuit as shown in FIG. 8, when a freewheeling diode is connected in antiparallel to the semiconductor element, it flows to the semiconductor element at the time of freewheeling. Since the total current can be reduced, the heat generation of the semiconductor element can be reduced, and the resistance to breakdown of the semiconductor element caused by a thermal cause increases.

In addition, in conventional field-effect semiconductor devices, the introduction of a lifetime killer into the diode portion also shortens the lifetime of the current path in the adjacent MOSFET portion, thereby reducing the current capacity of the semiconductor element. Although the result was inevitably brought about, it is clear that this adverse effect can be greatly reduced by adopting a structure in which the MOSFET portion and the diode region are separated as in the above embodiment.

In the above embodiment, the description of the MOSFET has been made exclusively.However, the largest insulated gate transistor having a structure in which the conductivity of the portion corresponding to the high-concentration drain region 1b which is the low-resistance region of the power MOSFET is reversed. Since the key to controlling the thyristor operation, which is the problem, is to suppress the operation of the portion corresponding to the parasitic transistor of the power MOSFET, it is clear that the present invention can provide an effective effect as it is.

[Effect of the Invention] In the vertical power MOS field-effect semiconductor device according to the present invention, a part of the second main surface of the low-impurity-concentration first conductivity-type semiconductor layer is provided on the side thereof via the first conductivity-type semiconductor layer. A first with a uniform depth to the bottom so that the edges are adjacent and opposed to each other
A plurality of second conductivity type semiconductor regions, and the first
A first conductivity type semiconductor region is provided on the surface of the conductivity type semiconductor region so as to extend at a distance from an edge of the region, and a second conductivity type semiconductor region and a second conductivity type semiconductor layer of the first conductivity type semiconductor layer. A gate electrode is disposed on the surface of the first second conductivity type semiconductor region sandwiched between the first conductivity type semiconductor layer opposed to the first conductivity type semiconductor region on the main surface of the first conduction type semiconductor region via an insulating film. And a bottom portion closer to the first main surface of the first conductivity type semiconductor layer than a bottom portion of the first second conductivity type semiconductor region. Is formed on the second main surface of the first conductivity type semiconductor layer so as to surround the second conductivity type semiconductor region.
Is disposed on the second main surface of the first conductive type semiconductor layer along the second second conductive type semiconductor region with a gate electrode via an insulating film. A gate electrode wiring is provided, and the first second conductivity type semiconductor region, the first conductivity type semiconductor region, and the second second conductivity type semiconductor region are short-circuited and the gate is formed so as to enter the gate electrode wiring. Since the first main electrode is provided via the electrode and the surface of the first conductivity type semiconductor layer and the insulating layer, the return current flowing to the portion functioning by the electric field effect flows also to the diode region and functions by the electric field effect. Since the return current flowing near the parasitic transistor in the portion becomes smaller, the area ratio of the diode region increases while securing a wide MOS field effect type semiconductor device region, and the MOS field effect type semiconductor device region can be arranged at high density. In addition to the remarkable effect of improving the secondary breakdown strength of the power MOS field-effect semiconductor device, the area ratio of the diode region can be increased while securing a large MOS field-effect semiconductor element region, and the MOS field-effect semiconductor The effect of the return current on the element region can be reduced.
As a result, the stability of the vertical power MOS field-effect semiconductor device during operation at high voltage is improved, and the density of the MOS field-effect semiconductor element region can be increased.

[Brief description of the drawings]

FIG. 1 is a sectional view of a vertical power MOS field-effect semiconductor device on which the present invention is based. FIG. 2 shows a similar vertical power MO on which the invention is based.
FIG. 3 is a sectional view of an S field effect type semiconductor device. FIG. 3A is an electrode pattern diagram of a vertical power MOS field-effect semiconductor device according to an embodiment of the present invention, FIG. 3B is a partial cross-sectional view taken along line XX of FIG. 3A, and FIG. FIG. 3B is a partial sectional view taken along line YY of FIG. 3A. FIG. 4A is a cross-sectional view of a basic structural unit of a vertical power MOS field-effect semiconductor device according to another embodiment, and FIG. 4B is a partial top view of a portion Z in FIG. 4A. FIG. 5 is a sectional view of a conventional power MOSFET. FIG. 6 is a diagram showing output characteristics of a conventional power MOSFET. FIG. 7A shows the MO when the second conductivity type semiconductor region has no projection.
FIG. 7B is a sectional view of a basic structural unit of the SFET, and FIG. 7B is a diagram showing an equivalent circuit of FIG. 7A. FIG. 8 is an inverter circuit diagram using a power MOSFET. FIG. 9 is a diagram showing the waveform of the voltage Vd of the freewheel diode and the waveform of the current Im flowing through the power MOSFET in FIG. In the figure, 1a is a low-concentration drain region of the first conductivity type, 1b
Is a high-concentration drain region of the first conductivity type, 2 is a semiconductor region of the second conductivity type, 21 is a convex portion, 3 is a source region of the first conductivity type, 4
Is an insulating film, 5 is a gate electrode, 6 is a source electrode, 7 is a channel formation region, 8 is a drain electrode, 9 is a diode region, 9a is a deep diode region, 9b is a shallow diode region, and 10 is a first conductive type high region. An impurity concentration region, 11 is an electrode forming portion, 12 is a gate electrode wiring, 110 is a narrow electrode forming portion, 30 is a gate bonding pad, and 31 is a source bonding pad. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] A first conductive type semiconductor substrate having a high impurity concentration having a first main surface and a second main surface; and a first conductive type semiconductor substrate in contact with the first main surface of the first conductive type semiconductor substrate. A low-impurity-concentration first-conductivity-type semiconductor layer having a main surface and a second main surface opposed to the first main surface; and a part of the second main surface of the first-conductivity-type semiconductor layer. A plurality of first second-conductivity-type semiconductor regions arranged so that the depth to the bottom is uniform and the edges of the first second-conductivity-type semiconductor layers are adjacent to and opposed to each other via the first-conductivity-type semiconductor layer; A first conductivity type semiconductor region disposed on the surface of the second conductivity type semiconductor region so as to extend at a distance from an edge of the second conductivity type semiconductor region; and the first conductivity type semiconductor region and the first conductivity type. The first conductive type semiconductor layer opposed to the first conductive type semiconductor region on the second main surface of the semiconductor layer; A gate electrode disposed on the surface of the second conductivity type semiconductor region via an insulating film;
The first conductive type semiconductor layer has a bottom portion close to the first main surface, and has a first conductive type semiconductor layer surrounding a plurality of the first second conductive type semiconductor regions through a part of the first conductive type semiconductor layer. A second second conductivity type semiconductor region provided on a second main surface of the first semiconductor layer, and the first first semiconductor region extending along the second second conductivity type semiconductor region.
A gate electrode wiring provided on the second main surface of the conductive type semiconductor layer via an insulating film and connected to the gate electrode; the first second conductive type semiconductor region and the first conductive type A short-circuit between the semiconductor region and the second second-conductivity-type semiconductor region and a gate electrode and a first-conductivity-type semiconductor layer provided on the surface of the first-conductivity-type semiconductor layer via an insulating layer so as to enter each other. 1. A vertical power MOS field-effect semiconductor device comprising: a first main electrode; and a second main electrode disposed on a second main surface of the semiconductor substrate.