JPS59149056A - Vertical metal oxide semiconductor transistor - Google Patents
Vertical metal oxide semiconductor transistorInfo
- Publication number
- JPS59149056A JPS59149056A JP58023198A JP2319883A JPS59149056A JP S59149056 A JPS59149056 A JP S59149056A JP 58023198 A JP58023198 A JP 58023198A JP 2319883 A JP2319883 A JP 2319883A JP S59149056 A JPS59149056 A JP S59149056A
- Authority
- JP
- Japan
- Prior art keywords
- region
- well region
- type
- type well
- breakdown
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 4
- 229910044991 metal oxide Inorganic materials 0.000 title 1
- 150000004706 metal oxides Chemical class 0.000 title 1
- 239000000758 substrate Substances 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 abstract description 24
- 238000009792 diffusion process Methods 0.000 abstract description 6
- -1 boron ions Chemical class 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 4
- 230000006378 damage Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
Abstract
Description
【発明の詳細な説明】
この発明は、リーク電流の発生やブレークダウンによる
素子領域の破壊を防止するための改良を施した縦型ＭＯ
８ｌ−ランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a vertical MO
8l-Relating to a transistor.
従来の縦型ＭＯ８ｌ−ランジスタとしては、例えば第１
図に示すような構造のものが良く知られている。同図に
示す縦型ＭＯ８Ｉ−ランジスタは、ドレイン電極３が接
合されるＮ生型（Ｎ型高濃度）の半導体基板４と、この
Ｎ十型基板４の上面に積層されたＮ−型（Ｎ型紙Ｓ度）
領域５と、このＮ−型領域５内に所定間隔をおいて複数
形成されたＰ型ウェル領域７と、このＰ型ウェル領域７
内に形成されたＮ中型ソース領域８と、このＮ中型ソー
ス領域８と実質的なドレイン領域となる上記Ｎ−型領域
５の双方にまたがった状態でゲート酸化膜９を介して形
成されたゲート電極１ｏとを具備してなるものである。As a conventional vertical MO8l-transistor, for example, the first
The structure shown in the figure is well known. The vertical MO8I-transistor shown in the figure includes an N-type (high concentration of N-type) semiconductor substrate 4 to which a drain electrode 3 is bonded, and an N-type (N-type) (N Pattern S degree)
region 5, a plurality of P-type well regions 7 formed at predetermined intervals within this N-type region 5, and this P-type well region 7.
and a gate formed via a gate oxide film 9 in a state spanning both the N medium-sized source region 8 and the N- type region 5, which becomes a substantial drain region. It is equipped with an electrode 1o.
また、ゲート電極１０の引き出し部分を除く上面部分が
ＰＳＧ膜１２で被覆されており、更にソース電極１１が
、Ｐ型ウェル領域内に形成されたＰ生型コンタクト領域
１３とＮ中型ソース領域８に接合するように形成されて
いる。Further, the upper surface portion of the gate electrode 10 except for the extended portion is covered with a PSG film 12, and the source electrode 11 is further connected to the P type contact region 13 formed in the P type well region and the N medium type source region 8. formed to join.
この種のＭＯＳ ｌ−ランジスタでは、比較的高圧・大
電流のスイッチングを行なう必要性から、素子の耐圧を
向上させる工夫が種々なされており、例えば第１図に示
す如く、複数のＰ型ウェル領域７が形成された素子形成
領域の周囲にガードリングと呼ばれるＰ小型の浅く拡散
形成されたリング状ウェル領域１４を設けたものがある
。In this type of MOS l-transistor, various efforts have been made to improve the withstand voltage of the element due to the need to perform relatively high voltage and large current switching. There is a device in which a ring-shaped well region 14 called a guard ring, which is a small P-shaped shallow diffusion-formed well region, is provided around the element formation region in which P is formed.
これは、ソース・ドレイン間に高圧の逆方向電圧が印加
されたときに、素子形成領域周縁部のＰ型ウェル領域内
の曲率半径の小さい角部１５において電界集中が起こっ
てブレークダウンを生じ易いことから、上記のガードリ
ンク１４によって上記角部１５における空乏層１６の曲
率半径を大きくすることで素子の耐圧の向上を図ったも
のである。This is because when a high reverse voltage is applied between the source and drain, electric field concentration occurs at the corner 15 with a small radius of curvature in the P-type well region at the periphery of the element formation region, which tends to cause breakdown. Therefore, the guard link 14 increases the radius of curvature of the depletion layer 16 at the corner 15, thereby improving the breakdown voltage of the device.
ところが、このような従来の縦型ＭＯ８ｌ−ランジスタ
にあっては、ソース・ドレイン間に更に高圧（第２図Ａ
点で示す）が印加されると、ガードリング１４とＰ型ウ
ェル領域７の間のＮ−型領域５表面にＰ型反転層１７が
生じ、ガードリング１４とＰ型ウェル領域７とが導通し
てしまう。すると、ガードリング１４の角部１８に電界
集中が起こって、この角部１８でブレークダウンが起こ
り、上記Ｐ型層転層１７を通ってリーク電流が素子領域
内へ流れる。このリーク電流の電流値は反転層１７の抵
抗により制限されるため、それほど大きな値とはならな
いが、素子の耐圧特性上の信頼性を低下させることとな
る。However, in such a conventional vertical MO8l-transistor, even higher voltage (see Fig. 2A) is applied between the source and drain.
) is applied, a P-type inversion layer 17 is generated on the surface of the N- type region 5 between the guard ring 14 and the P-type well region 7, and the guard ring 14 and the P-type well region 7 are electrically connected. I end up. Then, electric field concentration occurs at the corner 18 of the guard ring 14, breakdown occurs at the corner 18, and leakage current flows into the element region through the P-type layer transfer layer 17. The current value of this leakage current is limited by the resistance of the inversion layer 17, so it is not a very large value, but it does reduce the reliability of the breakdown voltage characteristics of the device.
また、更に印加電圧が高くなると（第２図Ｂ点で示す）
、やはりＰ型ウェル領域内の角部１５でブレークダウン
が起こり、素子領域が熱破壊される虞れがある。Furthermore, when the applied voltage becomes higher (as shown by point B in Figure 2)
There is also a risk that breakdown will occur at the corner 15 in the P-type well region and the element region will be thermally destroyed.
この発明は上記の事情に鑑みてなされたもので、その目
的とするところは、上記のようなリーク電流の発生やブ
レークダウンによる素子破壊を防止することにある。The present invention has been made in view of the above circumstances, and its purpose is to prevent element destruction due to the occurrence of leakage current and breakdown as described above.
この発明は上記目的を達成するために、前記のような縦
型ＭＯ８ｌ−ランジスタにおいて、素子形成領域の周囲
に基板の導電型とは逆の導電型で、かつ高濃度のウェル
領域（ガードリングに相当）を設けるとともに、該高濃
度つＪル領域を基板側の電極とは反対の電極に導通させ
たことを特徴とするものである。In order to achieve the above object, the present invention provides a vertical MO8l-transistor as described above, in which a well region (with a guard ring) having a conductivity type opposite to that of the substrate and having a high concentration is provided around the element formation region. This is characterized in that the high concentration drop region is electrically connected to an electrode opposite to the electrode on the substrate side.
以下この発明の一実施例を第３図を用いて詳細に説明す
る。なお、同図において第１図に示した従来の縦型ＭＯ
８ｌ−ランジスタと同一構成部分には同一の符号を付し
てその説明は省略する。An embodiment of the present invention will be described in detail below with reference to FIG. In addition, in the same figure, the conventional vertical MO shown in FIG.
Components that are the same as those of the 8l-transistor are given the same reference numerals, and their explanations will be omitted.
第３図に示す如く、この実施例の縦型ＭＯＳトランジス
タの各単位素子領域は、第１図に示した従来例の縦型Ｍ
Ｏ８Ｉ−ランジスタと同様にＮ−型ドレイン領域５と、
Ｐ型ウェル領域７と、Ｎ生型ソース領域８と、ゲート電
極１０等から構成されている。As shown in FIG. 3, each unit element region of the vertical MOS transistor of this embodiment is different from the vertical MOS transistor of the conventional example shown in FIG.
Similar to the O8I-transistor, an N-type drain region 5,
It is composed of a P-type well region 7, an N-type source region 8, a gate electrode 10, and the like.
そして、前記従来例におけるガードリンク１４の如く、
前記素子領域の周囲に、Ｐ小型のウェル領域２０が形成
されており、このＰ生型ウェル領域２０には、ソース電
極１１が接合されている。And, like the guard link 14 in the conventional example,
A P-sized well region 20 is formed around the element region, and a source electrode 11 is connected to this P-type well region 20.
更に、上記Ｐ生型ウェル領域２０は、その拡散の深さが
上記Ｐ型ウェル領域７の深さよりも深く形成されている
。ずなわら、前記Ｐ型ウェル領域７の底面からＮ中型領
域４までの距離をｄ＋、前記Ｐ生型ウェル領域２０の底
面からＮ生型領域４５−
までの距離をｄ２とすればｄ２＜ｄ＋の関係が成り立つ
。Further, the P type well region 20 is formed so that its diffusion depth is deeper than the depth of the P type well region 7. If the distance from the bottom of the P-type well region 7 to the N medium-sized region 4 is d+, and the distance from the bottom of the P-type well region 20 to the N-type region 45- is d2, then d2<d+. The relationship holds true.
このように構成された縦型ＭＯ８ｌ−ランジスタにおい
て、ソース・ドレイン間に高圧の逆方向電圧が印加され
ると、前記従来例におけるガードリンク１４の場合と同
様にして、Ｐ生型ウェル領域２０の角部２１に電界集中
が起こり、この角部２１でブレークダウンが起こる。In the vertical MO8l-transistor configured in this way, when a high reverse voltage is applied between the source and drain, the P-type well region 20 is damaged in the same manner as in the case of the guard link 14 in the conventional example. Electric field concentration occurs at the corner 21, and breakdown occurs at this corner 21.
そして、Ｐ生型ウェル領域２０がソース電極１１に導通
しているため、上記ブレークダウンの発生によって流れ
るブレークダウン電流は、素子領域内は流れず、Ｐ十型
ウェル領域２０内を通って ・直接ソース電極１１
へ導出されることとなり、素子領域の破壊を防止するこ
とができる。Since the P type well region 20 is electrically connected to the source electrode 11, the breakdown current that flows due to the occurrence of the breakdown does not flow within the element region, but directly through the P type well region 20. Source electrode 11
Therefore, destruction of the element region can be prevented.
また、上記Ｐ生型ウェル領域２０の拡散深さをＰ型ウェ
ル領域７より深くしたことによって、上記高圧の逆方向
電圧が印加されても、Ｐ生型ウェル領域２０とＰ型ウェ
ル領域７との間のＮ−型ドレイン領域５の表面にＰ型層
転層が形成されないため、従来例のようなリーク電流が
素子領域内を６一
流れることがない。Furthermore, by making the diffusion depth of the P-type well region 20 deeper than that of the P-type well region 7, even if the high voltage in the reverse direction is applied, the P-type well region 20 and the P-type well region 7 can be separated. Since no P-type layer transfer layer is formed on the surface of the N-type drain region 5 between the two, leakage current does not flow through the device region as in the conventional example.
更に、上記Ｐ生型ウェル領域２０を設【プたことによっ
て、素子の耐圧は、このＰ＋型ウェル領域２０とＮ中型
領域４との間の耐圧で決まることとなる。そして、上記
Ｐ生型ウェル領域２０の下面からＮ中型領域４の上面ま
での距離ｄ２をリーチスルー降伏の起こる距離よりも短
くすれば、素子の耐圧は素子のオン抵抗を変えることな
く、上記路ＩＩＩｔｄ２を変えることによって調整する
ことができる。Further, by providing the above-mentioned P type well region 20, the breakdown voltage of the device is determined by the breakdown voltage between this P+ type well region 20 and the N medium size region 4. If the distance d2 from the bottom surface of the P-type well region 20 to the top surface of the N medium-sized region 4 is made shorter than the distance at which reach-through breakdown occurs, the withstand voltage of the device can be increased as described above without changing the on-resistance of the device. It can be adjusted by changing IIItd2.
上記リーチスルー降伏とは、上記路１１１ｔｄ２を、Ｐ
＋型ウェル領域２０の角部２１でブレークダウンが起こ
るときの空乏層の拡がり幅よりも短くすることによって
、上記角部２１でブレークダウンが起こる前にＰ＋型ウ
ェル領域２０の下面の空乏層１６がＮ中型領域４に到達
することによってこの部分で先にブレークダウンが起こ
る現象を表わしており、このとき、ブレークダウン電流
はＰ＋型ウェル領域２０の底面の広い範囲を通って流れ
るため、熱集中を起こすことがなく、より効果的に素子
を保護することができる。The above-mentioned reach-through yield means that the above-mentioned path 111td2 is
By making the expansion width of the depletion layer shorter than the width of the depletion layer when breakdown occurs at the corner 21 of the + type well region 20, the depletion layer 16 on the lower surface of the P+ type well region 20 is expanded before breakdown occurs at the corner 21. This represents a phenomenon in which breakdown occurs first in this part when the current reaches the N medium-sized region 4, and at this time, the breakdown current flows through a wide range at the bottom of the P+ type well region 20, causing heat concentration. The device can be more effectively protected without causing any damage.
次に、上記の縦型ＭｏＳトランジスタの製造工程の一例
を第４図を用いて簡単に説明する。Next, an example of the manufacturing process of the above vertical MoS transistor will be briefly explained using FIG. 4.
まず第４図（ａ ）に示す如く、Ｎ十型半導体基板４の
上面に例えばエピタキシャル成長法によってＮ−型領域
５を積層形成し、このＮ−型領域５の表面に熱酸化によ
ってゲート酸化膜９を形成する。First, as shown in FIG. 4(a), an N-type region 5 is layered on the upper surface of an N0-type semiconductor substrate 4 by, for example, epitaxial growth, and a gate oxide film 9 is formed on the surface of this N-type region 5 by thermal oxidation. form.
次に、所定のパターンのレジストをマスクとしてボロン
イオンをＮ−型領域５の表面に導入した後、熱拡散させ
て同図（ｂ）に示ず如く、Ｐ生型つェル領［２０を形成
する。Next, boron ions are introduced into the surface of the N-type region 5 using a resist with a predetermined pattern as a mask, and then thermally diffused to form a P-type well region [20] as shown in FIG. Form.
このとき、上記ボロンイオンの単位面積当りの導入数や
熱拡散処理時間を調整して、上記Ｐ生型ウェル領域２０
の拡散深さを所定の深さに設定する。At this time, the number of introduced boron ions per unit area and the thermal diffusion treatment time are adjusted to
The diffusion depth of is set to a predetermined depth.
次に同図（Ｃ）に示す如く、部分的にゲート酸化膜９を
成長させ、同じ（ポリシリコンをデポジットし、更にフ
ォトエツチング処理を行なって、所定の位置にゲート電
極１０を形成する。Next, as shown in FIG. 3C, a gate oxide film 9 is grown partially, the same polysilicon is deposited, and a photo-etching process is performed to form a gate electrode 10 at a predetermined position.
次に、上記ゲート電極１０およびレジスト３０をマスク
として、ボロンイオンをＮ−型領域５の表面に導入した
後、熱拡散を行ない、更に、レジスト３１を用いてボロ
ンイオンの導入および熱拡散を行なって、同図（ｄ ）
に示す如く、Ｐ型ウェル領域７とＰ生型コンタクト領域
１３を形成する。Next, using the gate electrode 10 and the resist 30 as a mask, boron ions are introduced into the surface of the N-type region 5, and then thermally diffused, and further, boron ions are introduced and thermally diffused using the resist 31. The same figure (d)
As shown in FIG. 2, a P-type well region 7 and a P-type contact region 13 are formed.
次に、上記Ｐ型ウェル領域７の表面のソース形成予定領
域のみに所定パターンのレジストを用いてリンイオンの
導入を行なった後、熱拡散を行なって、Ｎ生型ソース領
域８を形成し、次に、素子表面にＰＳＧ膜１２を形成し
た後、フォトエツチング処理によって、ソースコンタク
トホールの孔間けを行ない、アルミニウム蒸着によって
ソース電極１１を形成することによって、同図（ｅ）に
示すようなＭＯＳ トランジスタ構造を得ることができ
る。Next, phosphorus ions are introduced only into the region where the source is to be formed on the surface of the P-type well region 7 using a resist with a predetermined pattern, and then thermal diffusion is performed to form the N-type source region 8. After forming a PSG film 12 on the element surface, a source contact hole is formed by photo-etching, and a source electrode 11 is formed by aluminum evaporation, thereby creating a MOS as shown in FIG. A transistor structure can be obtained.
なお以上の説明では、Ｎチャンネル型の縦型ＭＯＳトラ
ンジスタについて記述しであるが、この発明は、Ｐチャ
ンネル型の縦型ＭＯ８Ｉ−ランジスタにも同様にして適
用できることは明らかであり、−９＝
この場合ＮをＰに又ＰをＮに変更することによって容易
に形成できる。Although the above description describes an N-channel type vertical MOS transistor, it is clear that the present invention can be similarly applied to a P-channel type vertical MO8I-transistor. The case can be easily formed by changing N to P and P to N.
以上詳細に説明したようにこの発明の縦型ＭＯＳトラン
ジスタにあっては、ソース・ドレイン間にサージ等の高
電圧が印加された場合に、ブレークダウン電流が素子領
域の周囲に設けられｌζ高高濃ウェル領域内を通って導
出されることによって、リーク電流やブレークダウン電
流が素子領域内を流れることがなく、素子領域を熱破壊
から守り、また素子の耐圧特性の信頼性を向上させるこ
とができる。As explained in detail above, in the vertical MOS transistor of the present invention, when a high voltage such as a surge is applied between the source and drain, a breakdown current is generated around the element region and By passing through the deep well region, leakage current and breakdown current do not flow within the device region, which protects the device region from thermal damage and improves the reliability of the device's breakdown voltage characteristics. can.
第１図は従来の縦型ＭＯ８ｔ−ランジスタを示す素子断
面図、第２図は同素子のドレイン電流とソース・ドレイ
ン間電圧の特性を示す図、第３図は本発明に係る縦型Ｍ
Ｏ８ｈランジスタの素子周縁部における構造を示す素子
断面図、第４図は同素子の製造工程図である。
３・・・ドレイン電極
４・・・Ｎ生型領域
１０−
５・・・・・・Ｎ−型領域
７・・・・・・Ｐ型ウェル領域
８・・・・・・ソース領域
１１・・・ソース電極
２１・・・Ｐ十型ウェル領域
特許出願人
日産自動車株式会社
１１−
第３図FIG. 1 is a cross-sectional view of a conventional vertical MO8T-transistor, FIG. 2 is a diagram showing the drain current and source-drain voltage characteristics of the same device, and FIG. 3 is a vertical MO8T transistor according to the present invention.
FIG. 4 is a cross-sectional view of the O8h transistor showing the structure at the peripheral edge of the element, and is a manufacturing process diagram of the same element. 3... Drain electrode 4... N-type region 10- 5... N- type region 7... P-type well region 8... Source region 11...・Source electrode 21...P-shaped well region Patent applicant Nissan Motor Co., Ltd. 11- Fig. 3
Claims (1)
に形成された第２導電型ウエル領域と、該第２導電型ウ
エル領域内に形成された第１導電型領域とを備え、前記
第１導電型領域をソース電極またはドレイン電極の一方
に導通させるとともに、他方の電極には前記基板の下面
側が導通する縦型ＭＯＳトランジスタにおいて； 前記素子形成領域の周囲に第２導電型で、かつ高濃度の
ウェル領域を設けるとともに、該高？１１麿ウェル領域
は前記第１導電型領域に導通する電極と同電位の電極に
導通することを特徴とする縦型ＭＯＳトランジスタ。(1) comprising a second conductivity type well region formed within an element formation region on the upper surface side of a first conductivity type semiconductor substrate, and a first conductivity type region formed within the second conductivity type well region; In a vertical MOS transistor in which the first conductivity type region is electrically connected to one of a source electrode or a drain electrode, and the lower surface side of the substrate is electrically connected to the other electrode; In addition to providing a high concentration well region, the high concentration? 11. A vertical MOS transistor, wherein the well region is electrically connected to an electrode having the same potential as the electrode electrically connected to the first conductivity type region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58023198A JPS59149056A (en) | 1983-02-15 | 1983-02-15 | Vertical metal oxide semiconductor transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58023198A JPS59149056A (en) | 1983-02-15 | 1983-02-15 | Vertical metal oxide semiconductor transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59149056A true JPS59149056A (en) | 1984-08-25 |
Family
ID=12103969
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58023198A Pending JPS59149056A (en) | 1983-02-15 | 1983-02-15 | Vertical metal oxide semiconductor transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59149056A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3540433A1 (en) * | 1984-11-20 | 1986-05-22 | Mitsubishi Denki K.K., Tokio/Tokyo | Integrated MOSFET component |
| JPS61182264A (en) * | 1985-02-08 | 1986-08-14 | Nissan Motor Co Ltd | Vertical type mos transistor |
| JPS63194366A (en) * | 1987-02-09 | 1988-08-11 | Toshiba Corp | High breakdown-voltage planar type semiconductor element |
| JPS6422067A (en) * | 1987-07-17 | 1989-01-25 | Toshiba Corp | Double diffusion type insulated-gate field effect transistor |
| JPH01215067A (en) * | 1988-02-24 | 1989-08-29 | Hitachi Ltd | Vertical insulating gate field effect transistor |
| JPH04767A (en) * | 1990-04-02 | 1992-01-06 | Fuji Electric Co Ltd | Mos semiconductor element |
| US5208471A (en) * | 1989-06-12 | 1993-05-04 | Hitachi, Ltd. | Semiconductor device and manufacturing method therefor |
| US5221850A (en) * | 1991-03-20 | 1993-06-22 | Fuji Electric Co., Ltd. | Conductivity-modulating mosfet |
| WO1998010469A1 (en) * | 1996-09-06 | 1998-03-12 | Mitsubishi Denki Kabushiki Kaisha | Transistor and method of manufacturing the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57206073A (en) * | 1981-06-12 | 1982-12-17 | Hitachi Ltd | Mis semiconductor device |
-
1983
- 1983-02-15 JP JP58023198A patent/JPS59149056A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57206073A (en) * | 1981-06-12 | 1982-12-17 | Hitachi Ltd | Mis semiconductor device |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3540433A1 (en) * | 1984-11-20 | 1986-05-22 | Mitsubishi Denki K.K., Tokio/Tokyo | Integrated MOSFET component |
| JPS61182264A (en) * | 1985-02-08 | 1986-08-14 | Nissan Motor Co Ltd | Vertical type mos transistor |
| US4819044A (en) * | 1985-02-08 | 1989-04-04 | Nissan Motor Co., Ltd. | Vertical type MOS transistor and its chip |
| JPH051626B2 (en) * | 1985-02-08 | 1993-01-08 | Nissan Motor | |
| JPS63194366A (en) * | 1987-02-09 | 1988-08-11 | Toshiba Corp | High breakdown-voltage planar type semiconductor element |
| JPS6422067A (en) * | 1987-07-17 | 1989-01-25 | Toshiba Corp | Double diffusion type insulated-gate field effect transistor |
| JPH01215067A (en) * | 1988-02-24 | 1989-08-29 | Hitachi Ltd | Vertical insulating gate field effect transistor |
| US5208471A (en) * | 1989-06-12 | 1993-05-04 | Hitachi, Ltd. | Semiconductor device and manufacturing method therefor |
| JPH04767A (en) * | 1990-04-02 | 1992-01-06 | Fuji Electric Co Ltd | Mos semiconductor element |
| US5221850A (en) * | 1991-03-20 | 1993-06-22 | Fuji Electric Co., Ltd. | Conductivity-modulating mosfet |
| WO1998010469A1 (en) * | 1996-09-06 | 1998-03-12 | Mitsubishi Denki Kabushiki Kaisha | Transistor and method of manufacturing the same |
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