JPH02202063A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a latch-up phenomenon from occurring in a semiconductor device of this design by a method wherein a current extracting layer, whose conductivity type is the same as those of well regions and which is to be connected to a source electrode, is provided between the well regions under a gate electrode. CONSTITUTION:A first conductivity type semiconductor layer is formed by diffusion in a part of a second conductivity type semiconductor layer 12 sandwiched between two or more well regions 131 and 132 under a gate oxide film 15 and connected to a source electrode 19 for the formation of a current extracting layer 24 which shunts a current introduced into the well regions 131 and 132 from the second conductivity type semiconductor layer 12. A part of a hole current introduced from the second conductivity type semiconductor layer 12 into two or more well regions 131 and 132 branches off to flow into the current extraction layer 24 and flows directly to the source electrode 19. As the current extraction layer 24 is located just under the gate, the layer 24 reduces a hole current which flows from the part just under the gate circuiting the part just under the source regions 141 and 142 and restrains the potential of the well regions 131 and 132 from increasing. By this setup, a semiconductor device of this design can be protected from a latch-up phenomenon.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to the structure of a semiconductor device, and in particular has a vertical insulated gate bipolar transistor structure, which can be used as a switching element for high voltage power, and which can be used as a latch. The present invention relates to a structure of a semiconductor device with improved upstand capability.

[Prior Art] In recent years, insulated gate bipolar transistors (insulated gate bipolar transistors in which the train region of a conventional vertical power MO8FET (metal oxide semiconductor field effect transistor) has a conductivity type opposite to that of the source region) have been developed as high-voltage power switching elements.
IGBT> is known. Insulated gate bipolar transistors have a lower on-resistance than conventional vertical power MO8FETs and are capable of passing large currents, so they are attracting attention as an alternative element.

The structure of this insulated gate bipolar transistor is shown in the seventh section.
As shown in the figure. In the figure, high concentrations, e.g. 1 X 10i
A substrate having an impurity concentration of 8/cd (here, for example, P
11 of the opposite conductivity type (for example, P
A low concentration layer 12 (for example, an impurity concentration of lXl0''/a! or less, a thickness of 50 μm or more) having an N type) is formed. Well regions 131 and 132 having a conductivity type opposite to that of the low concentration layer 12 (for example, P type for N type) are formed by diffusion on the surface of the well region 131 and 132. Source regions 141 and 142 of high concentration (for example, impurity concentration of 1×10 19 /- or more) having a conductivity type (for example, N type for P type) are formed by diffusion.These well regions 131 and 132 and the source Area 141,1
42 is formed by a double diffusion method, and is formed in the well region 13.
1.132 is diffused into the source region 1.
41.142 is used as a diffusion window.

The surface of the well region 131.132 sandwiched between the low concentration layer 12 and the source region 141.142 is the channel region 171.1.
72, and a gate electrode 16 is formed on the upper surface of the channel regions 171 and 172 and the low concentration layer 12 via the gate oxide WA15.

A source electrode 19 is formed by ohmic contact on the upper surface of the well region 131, 132 where the source region 141, 142 and the gate electrode 16 are not formed, with these regions short-circuited, and connects the contact hole 201 and the contact hole 202. are doing. The source electrode 19 and the gate electrode 16 are insulated and separated by a glabella insulating film 18 . Further, a drain electrode 21 is formed on the lower surface of the substrate 11 and is in ohmic contact therewith.

An insulated gate bipolar transistor (N
To explain the operation of the type), when the drain electrode 21 is biased to a positive potential with respect to the source electrode 19 and a voltage is applied to the gate electrode 16, electrons are accumulated in the channel region 171 and 172, forming an inversion layer. . The electron flow 22 from the source regions 141 and 142 through the channel regions 171 and 172 to the low concentration layer 12 causes the substrate
Holes are injected from there, causing conductivity modulation in the low concentration layer 12. The resistance of this slanted low concentration layer 12 is reduced, and a lower on-resistance than that of the conventional vertical MO8FET is possible.

[Problems to be Solved by the Invention] Incidentally, in an insulated gate bipolar transistor having such a structure, the source region 141, 142, the well region 131, 132, the low concentration M12, and the substrate 11 form an NP.
A NP thyristor structure is formed, and there is a problem that when the current flowing between the drain electrode 21 and the source electrode 19 exceeds a certain critical value, the thyristor operation begins.

In the case of an N-type device, the hole current flows from the entire surface of the drain electrode 21 toward the part of the source electrode 19 that is in contact with the well regions 131 and 132. In particular, the holes directly under the gate flow as shown by the arrow 23 in the figure. channel area 171.172
It exhibits a behavior in which it flows from directly below to circulating around the source regions 141 and 142. Therefore, when the hole current increases,
The channel region 171.1 is caused by the hole current flowing from directly under the gate to around the source region 141.142.
When the potential of the well region 131 . well area 131.132 without passing through .172
A so-called latch-up phenomenon occurs in which the current between the drain electrode 21 and the source electrode 19 cannot be controlled by the gate voltage, and in extreme cases, the device may be destroyed.

For this reason, for example, a deep P-type layer is formed directly under the connection between the well regions 131 and 132 and the source regions 141 and 142 to lower the resistance of the hole current path. However, in this method, all of the hole current reaches the source electrode 19 via the P-type well region, so even if the resistance of the hole current path becomes somewhat small, the potential of the well region still rises and latch-up occurs. It was not possible to make the critical current generated sufficiently high.

The present invention has been made in view of the above-mentioned circumstances, and it is an object of the present invention to provide a semiconductor device having a structure in which latch-up phenomenon is less likely to occur even during high current operation.

[Means for Solving the Problems] When the configuration of the semiconductor device of the present invention is explained with reference to FIG.
A conductive type semiconductor substrate 11, a high-resistance second conductive type semiconductor layer 12 formed on the substrate 11, and a first conductive type well formed by diffusion at multiple locations on the surface of the second conductive type semiconductor layer 12. Region 131.132 and well region 131.13
a well region surface 13 sandwiched between the source region 141, 142 and the second conductivity type semiconductor layer 12;
1. Gate electrode 1 formed on a part of 132 and the surface of the second conductivity type semiconductor layer 12 with a gate oxide film 15 interposed therebetween.
6 and a source electrode 19 in ohmic contact with both the surfaces of the source regions 141 and 142 and the remaining surfaces of the well regions 131 and 132, and the second conductive type semiconductor layer 1
2, a plurality of well regions 1 are formed under the gate oxide film 15.
A first conductive type semiconductor layer is formed by diffusion in a part of the region sandwiched by the second conductive type semiconductor layer 12 and connected to the source electrode 19, and current is introduced from the second conductive type semiconductor layer 12 into the well region 131 and 132. There is no current extraction layer 24 that shunts the current.

[Operation] In the above structure, the hole current (N
(in the case of a mold), a part of the current extraction layer 2 provided between these
4 and passes directly to the source electrode 19. Since the current extraction layer 24 is located directly under the gate, it effectively reduces the hole current that circulates from directly under the gate to directly under the source region 141, 142, and suppresses the rise in potential of the well region 131, 132. , prevent the occurrence of latch-up phenomenon.

[Example] A specific example of the semiconductor device of the present invention will be described with reference to FIGS. 1 and 2. Note that elements common to the above conventional structure are designated by the same numbers.

FIG. 1 shows an N-type insulated gate bipolar transistor with a design target of, for example, a withstand voltage of 600V. Concentration I x 10”
The N-type low concentration layer 12 having a thickness of /- or less is formed by an epitaxial method or a bonding method. A gate oxide M15 having a thickness of about 1000 A is formed on the N-type low concentration layer 12 by a thermal oxidation method, and a gate electrode 16 made of, for example, polycrystalline silicon or a high melting point metal is formed on its upper surface. It is.

On the surface of the N-type low concentration layer 12, this gate oxide film 15,
Using the gate electrode 16 as a diffusion mask, a plurality of P-type well regions 131 with a diffusion depth of 4 μm, for example, are formed by a double diffusion method.
．． 132, and heavily doped N-type source regions 141 and 142 with a diffusion depth of 0.8 μm, for example.

In the N-type low concentration layer 12, in a part of the region immediately below the gate oxide film 15 and sandwiched between the plurality of P-type well regions 131 and 132, a P-type conductivity layer is added in the case of an N-type semiconductor device. A semiconductor layer having a source electrode 19 is formed by diffusion.
The layer 24 is connected to the current extraction layer 24 for the correct current.

Extracted from Figure 2! 24 and the source electrode 19 are shown. FIG. 1 corresponds to the sectional view taken along line II in FIG. 2. An extraction layer is provided on the surface of the N-type low concentration layer 12 so that the hole current that flows into the extraction layer 24 directly reaches the source electrode 19 without passing through the well region 131.132 below the source region 141.142. P-type paths 251 and 252 are formed to connect the output layer 24 and the well regions 131 and 132, respectively.

Further, the gate electrode 16 is patterned in a concave shape along the paths 251 and 252. As a result, gate electrode 1
A part of the hole current flowing under 6 is diverted to the extraction layer 24,
The source electrode 19 is reached via paths 251 and 252. Therefore, the well region 131.132 below the source region 141.142 greatly affects the occurrence of latch-up phenomenon.
Since the current flowing through the well region 13 is reduced,
1.132 potential increase is suppressed.

The extraction layer 24 can be formed when forming the well regions 131 and 132 or during double diffusion.
For example, when the well regions 131 and 132 are formed at the same time, the size of the well regions 131 and 132 is limited by the diffusion depth thereof, and in this embodiment, including the window for diffusion, it is about 14 μm. In addition, in addition to forming the channel region during double diffusion, the extraction layer 24 is
By forming this, the depth and width can be freely set to the optimum values. At this time, the gate electrodes 16 formed of polycrystalline silicon are divided into islands by the extraction layer 24, so the surface of the extraction layer 24 is heat-treated or
By CVD (chemical vapor deposition), sputtering, vapor deposition, etc.
Either polycrystalline silicon is deposited again, or each gate electrode is connected to the polycrystalline silicon using a metal that can make an ohmic connection.

According to simulation studies, the diffusion depth (d)
If the width (W) is 1 μm or more and the width (W) is 3 μm or more, 20% or more of the hole current can be shunted to the extraction layer 24. Preferably, the diffusion depth (d) should be in the range of 1 to 2 μm and the width (W) should be in the range of 3 to 5 μm, taking mask accuracy into consideration and in order to avoid the influence of an increase in on-resistance and to make this effect effective. This is desirable. Further, when the latch-up critical current flows, the ratio of electron current increases, so if the ratio of the amount of hole current branched to the extraction layer 24 is about 20% as described above, the latch-up critical current will be about 25%. To increase. Therefore, if the transistor having the structure according to this embodiment is used, a larger current can flow than the transistor having the conventional structure.

Further, since no inversion layer is formed in the extraction layer 24, as shown in FIG.
By forming 5 thicker than other parts, the stray capacitance between the substrate 11 and the gate electrode 16 can be reduced.
It is possible to increase the speed of switching.

Furthermore, since it has the same conductivity type as the well regions 131 and 132, it functions similarly to a guard ring when off, making it possible to prevent breakdown directly under the gate electrode 16. Furthermore, in the conventional structure, when a high gate voltage is applied, the depletion layer in the channel region 171.172 extends toward the drain region 21, so that the well region 131.1
32, the path through which the hole current can flow is narrowed, effectively increasing the resistance to the source electrode and further reducing the resistance to latch-up. However, in the present invention, since the extraction layer 24 is not reversed, By branching more hole current to the extraction layer 24, the resistance to latch-up is improved.

FIG. 4 shows a third embodiment of the invention. In the above embodiment, the paths 251 and 252 connecting the extraction layer 24 and the well regions 131 and 132 were formed at positions facing each other with the extraction layer 24 in between. A path 251 connecting to the well region 132 and a path 252 connecting to the well region 132 are formed at different locations. This results in
The resistance value of the extraction 124 leading to the source electrode can be reduced.

FIG. 5 shows a fourth embodiment of the present invention. In this embodiment, a large number of rectangular N-type low concentration layers 12 are arranged, an extraction layer 24 is formed to surround them, and a well provided in the N-type low concentration layer 12 is formed from the negative side. Paths 251 and 252 are formed to connect to regions 131 and 132. Similar effects can also be obtained in this manner. Note that the number of routes is not limited to one side, and a plurality of routes may be formed.

FIG. 6 shows a fifth embodiment of the present invention. In this embodiment, as in the third embodiment, a hole extraction layer 24 is formed around the rectangular low concentration layer 12, and paths 251 and 252 are formed diagonally from each vertex. .

Generally, the larger the width of the gate electrode, the lower the latch-up critical current value. Therefore, in a square cell structure, the diagonal distance limits the latch-up resistance.
In this embodiment, routes 251 and 252 are on this diagonal.
, the width of the gate electrode can be reduced, and the critical latch-up current value can be improved compared to an element with a conventional square cell structure.

In the above embodiments, N-type semiconductor devices have been described, but the present invention has exactly the same effect on P-type semiconductor devices.

In addition, a first conductivity type semiconductor substrate with a high concentration and a second conductivity type semiconductor substrate with a low concentration
A structure may be provided in which a second conductive type semiconductor layer having a higher concentration than the second conductive type semiconductor layer is provided between the conductive type semiconductor layer and the second conductive type semiconductor layer.

Further, in the above embodiments, striped and striped patterns have been described, but hexagonal and circular patterns may also be used, and the same effect can be obtained in either case.

[Effects of the Invention] As described above, according to the present invention, an extraction layer having the same conductivity type as the well region and connected to the source electrode is formed between the well regions under the gate electrode, thereby preventing latch-up. The hole current (in the case of N-type, electron current in case of P-type) flowing into each well region from directly below the gate electrode, which causes the problem, can be efficiently shunted and allowed to directly reach the source electrode.

Therefore, the latch-up critical current increases and a large current can flow, making it extremely useful as, for example, a high-voltage power switching element.

[Brief explanation of the drawing]

1 and 2 show one embodiment of the present invention. FIG. 1 is an overall sectional view of a semiconductor device, FIG. 2 is a sectional view taken along the line ■-■ in FIG. FIG. 3 is an overall sectional view of a semiconductor device showing a second embodiment of the present invention, and FIGS. 4 to 6 are plan views of a semiconductor device showing third to fifth embodiments of the present invention. 7 are overall sectional views of a conventional semiconductor device. 11...P-type high concentration substrate (first conductivity type semiconductor substrate) 12...N-type low concentration layer (second conductivity type semiconductor layer) 131.132...P Type well area (first
conductivity type well region) 141.142...N type source region (second conductivity type source region) 16...gate electrode 19...source electrode 24...・Extraction layer (current extraction layer) Figure 1 Figure 2 Article 2 16 Figure 3 Figure 5 Figure 4 Figure 6

Claims (1)

[Claims] a semiconductor substrate of a first conductivity type; a high-resistance semiconductor layer of a second conductivity type formed on the substrate; and well regions of a first conductivity type diffused at multiple locations on the surface of the semiconductor layer of the second conductivity type. , a low resistance second conductivity type source region diffused in the well region, a part of the surface of the well region sandwiched between the source region and the second conductivity type semiconductor layer, and the second conductivity type semiconductor layer. The second conductivity type semiconductor layer has a gate electrode formed on the surface of the layer via a gate oxide film, and a source electrode in ohmic contact with both the surface of the source region and the remaining surface of the well region. , a first conductivity type semiconductor layer is diffused and formed in a part of the region sandwiched between the plurality of well regions under the gate oxide film and connected to the source electrode;
A semiconductor device comprising: a current extraction layer that shunts the current introduced into the well region from the second conductivity type semiconductor layer.