JPH0621358A - Insulated gate type bipolar transistor - Google Patents

Abstract

PURPOSE:To improve withstand voltage of a gird ring of IGBT without increasing an ON-resistance. CONSTITUTION:By implanting He ions in an N<-> layer 3 of a gird ring part (region B), a crystal defect is formed selectively. In a bipolar transistor formed internally of P layers 10 and 4' constituting the gird ring and of an N<-> layer 3 and a P<+> layer 2 operating as a collector, a base and an emitter respectively, the amount of hole reaching the collector through the base out of the one injected from the emitter is decreased thereby and the current amplification factor betaof the bipolar transistor is reduced. With the reduction of this current amplification factor beta, the withstand voltage BVCEO of the bipolar transistor is improved and, in other words, the withstand voltage of the gird ring part is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate bipolar transistor (hereinafter referred to as an IGBT) used as a high voltage and large current power switching element.

[0002]

2. Description of the Related Art An IGBT has a structure similar to that of a power MOSFET, but by providing a pn junction in the drain region, conductivity modulation occurs in a high resistance drain layer during operation, resulting in a high breakdown voltage and a low breakdown voltage that cannot be achieved by a power MOSFET. Both on-resistance can be achieved.

However, the breakdown voltage of the guard ring structure portion at the outer peripheral portion of the element, which is usually used as a high breakdown voltage increasing means, is n.
Taking the channel IGBT as an example, the breakdown voltage of the internal pnp3 layer structure determines the breakdown voltage, and compared with a power MOSFET whose breakdown voltage is determined by the breakdown of the pn2 layer structure, it has a high resistance drain layer of the same resistivity and thickness. In this case, the on-resistance is remarkably small, but the breakdown voltage is low.
On the other hand, according to Japanese Patent Laid-Open No. 62-219667,
N ^{+ is} formed on the surface of the high resistance drain layer 3 at the outer periphery of the IGBT element.
A structure is proposed in which a base region 15 is provided and the n ⁺ base region 15 and the substrate p ⁺ region 2 are electrically short-circuited by an external wiring (see FIG. 4).

However, in this conventional structure, the wire bonding electrode pad 14 for electrically short-circuiting the n ⁺ base region 15 and the p ⁺ drain layer 2 must be provided on the surface n ⁺ base region 15 and the device current The effective area that serves as a passage is reduced. There is also a problem that the effect of increasing the breakdown voltage is not great.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has a structure that does not require a new electrode pad in an IGBT element and improves the breakdown voltage of a guard ring portion without sacrificing on-resistance. Is provided.

[0006]

In the IGBT, a first conductivity type first semiconductor layer is formed from a drain electrode side, and a second conductivity type second semiconductor layer that causes conductivity modulation by carrier injection is formed on the first conductivity type first semiconductor layer. The first semiconductor is selectively formed on the surface of the second semiconductor layer.
A conductive type third semiconductor layer is formed, and a second conductive type fourth semiconductor layer is selectively formed on the surface of the third semiconductor layer;
A gate electrode is formed on the surface of the third semiconductor layer between the second semiconductor layer and the fourth semiconductor layer via a gate insulating film, and a source electrode is formed from the surface of the third semiconductor layer to the surface of the fourth semiconductor layer. There is.

In order to achieve the above object, the IGBT of the present invention
With respect to the second semiconductor layer in the region (hereinafter referred to as B region) from the edge of the region where the third and fourth semiconductor layers are arranged (hereinafter referred to as A region) to the peripheral end of the second semiconductor layer. It is characterized in that a means for selectively shortening the life of minority carriers of the second semiconductor layer is provided only in the peripheral region including the formed guard ring breakdown voltage structure.

More specifically, crystal defects are formed in the second semiconductor layer in the B region for the purpose of shortening the life of minority carriers. Another configuration is to provide a sixth semiconductor layer of the second conductivity type containing an impurity at a concentration higher than that of the second semiconductor layer at or near the boundary surface between the second semiconductor layer and the first semiconductor layer in the B region. Is what you are doing.

Still another structure of the present invention is the second B area.
A crystal defect is formed in the semiconductor layer, and a sixth semiconductor layer of the second conductivity type is provided at or near the boundary surface between the second semiconductor layer and the first semiconductor layer.

[0010]

[Operation and Effect] The operation and effect achieved by the above configuration will be described below. Consider a situation in which a voltage is applied between the drain electrode and the source electrode, the pn junction composed of the third semiconductor layer and the second semiconductor layer is in a reverse bias state, and the depletion layer spreads in the high-resistance second semiconductor layer. Here, in the A region, in the adjacent third semiconductor layers and the second semiconductor layer regions located between them, depletion layers extend from the adjacent third semiconductor layers to the second semiconductor layers located between them and overlap each other, so Mitigation is achieved. Then, the maximum electric field value E _A is taken at the pn junction at the bottom of the third semiconductor layer. On the other hand, at the edge of the A region where the repeated arrangement of the third semiconductor layer ends, the above-mentioned electric field relaxation effect disappears, and the maximum electric field value at the corner of the third semiconductor layer at the edge or the surface of the second semiconductor layer near the third semiconductor layer. Take E _B. Since E _A <E _B in general, the avalanche pattern occurs in the B region before in the A region,
The breakdown voltage of the device is determined by the breakdown voltage of the B region. Therefore, in order to increase the breakdown voltage of the device, in order to reduce the maximum electric field E _B of the B region, the second electric field from the edge of the repeatedly arranged third semiconductor layer is increased.
The breakdown voltage structure is provided in the B region reaching the peripheral edge of the semiconductor layer. Generally, a guard ring structure is used to improve the breakdown voltage of the element. Here, the IGBT guard ring breakdown voltage is A
The withstand voltage BV _{CEO of the} bipolar transistor is formed by the source electrode-third semiconductor layer-second semiconductor layer-first semiconductor layer-drain electrode at the edge of the region. Therefore, the breakdown voltage BV of the pn junction composed of the third semiconductor layer and the second semiconductor layer
_It has a lower breakdown voltage than _CBO . This phenomenon is explained by the following equation.

[0011]

[ _Formula 1] BV _CEO = BV _CBO / (1 + β) ^{1 / n}

[0012]

[Formula 2] β = γ · α _T / (1−γ · α _T ) Formula 1 and Formula 2 are excerpts from “Basics of Semiconductor Devices” (published by McGraw-Hill Company, translated by Yasuo Tarui), P259 and P244. It was done.

From equation 1, the breakdown voltage BV _CEO due to the avalanche of the guard ring is affected by the current amplification factor β of the bipolar transistor due to the operation of the internal bipolar transistor at the time of breakdown, and the breakdown voltage BV _CEO is due to the avalanche of the pn junction. There occurs a phenomenon that the voltage is lower than the down voltage BV _CBO . Here, by reducing the β value of the intrinsic bipolar transistor in the B region, BV _CEO can be brought closer to BV _CBO and the guard ring breakdown voltage can be improved.

In the present invention, a crystal defect that shortens the life of minority carriers is formed inside the second semiconductor layer from the edge of the A region to the B region. As a result, the arrival rate α _T of the minority carriers of the bipolar transistor in the guard ring region is
(Also referred to as transportation efficiency) becomes smaller, and as a result, the β value becomes smaller, as shown in Equation 2, and as a result, the value of BV _CEO increases.

Next, the operation and effect of another structure of the present invention will be described. By providing a sixth semiconductor layer of the second conductivity type containing a higher concentration of impurities than the second semiconductor layer at or near the boundary surface between the second semiconductor layer and the first semiconductor layer in the B region, Injection of minority carriers from the semiconductor layer is suppressed. That is, the injection efficiency γ of the intrinsic bipolar transistor decreases, and as shown in Equation 2,
The current amplification factor β decreases, and as a result BV _CEO increases.

In yet another configuration, the formation of crystal defects in the second semiconductor layer in the B region, the second semiconductor layer and the first semiconductor layer
If the formation of the sixth semiconductor layer at or near the boundary surface of the semiconductor layers is carried out in combination, the current amplification factor β is reduced by decreasing both the arrival rate α _T and the injection efficiency γ of the internal bipolar transistor in the B region. It becomes smaller, and BV becomes even more
An increase in _CEO is achieved.

In the structure described above, it is not necessary to form a new electrode pad on the device surface to reduce the area of the A region which is the cell region, and further reduce the current amplification factor β of the internal bipolar transistor in the B region. However, since there is no decrease in the current amplification factor of the intrinsic bipolar transistor in the region A, there is no increase in the resistance in the ON state. Therefore, the breakdown voltage of the guard ring can be improved without increasing the on-resistance of the element.

[0018]

The present invention will be described below based on the embodiments shown in the drawings. In the example, an n-channel IGBT using p-type as the first conductivity type and n-type as the second conductivity type will be described.

FIG. 1 is a block diagram of an I to which the first embodiment of the present invention is applied.
It is sectional drawing of a unit cell part (A area | region) and a guard ring part (B area | region) of a GBT element. This will be described according to the manufacturing process.

First, the p ⁺ drain layer 2 which is a semiconductor substrate
(First semiconductor layer) is prepared, and a high resistance n ^- drain layer 3 is formed on the first semiconductor layer by vapor deposition or wafer direct bonding.
The (second semiconductor layer) is formed with a predetermined impurity concentration N _D and a thickness t _e . Then, the p-well layer 4a (which forms a part of the third semiconductor layer), the p-layer 10 and the p-layer 4'are simultaneously formed to a depth of 3 to 6 m by the selective diffusion method. Here, the p-layer 10 is a guard ring formed for the purpose of increasing the breakdown voltage, and the p-layer 4'is an extraction layer for extracting excess carriers to the source electrode. Further, a p-channel layer 4b is formed so as to overlap the p-layer 4a, and a p-channel layer 4b is formed of the p-well layer 4a and the p-channel layer 4b.
An n ⁺ source layer 5 (fourth semiconductor layer) is formed in the layer (third semiconductor layer). In the above manufacturing process, n ⁻
Using the gate electrode 7 formed on the gate oxide film 6 formed by oxidizing the surface of the drain layer 3 as a mask, the so-called DSA technique (Diffusion Self Al) is used.
The p channel layer 14b and the n ⁺ source layer 5 are formed in a self-aligned manner by the ion implantation), thereby forming a channel.

Then, an interlayer insulating film 8 is formed, and subsequently, in order to form ohmic contact with the p layer 4 and the n ⁺ layer 5, a contact hole is opened in the gate oxide film 6 and the interlayer insulating film 8, and aluminum is formed. Is vapor-deposited by several μm and selectively etched to form the source electrode 9 and the gate electrode pad (not shown). Then, a metal film is deposited on the back surface of the p ⁺ drain layer 2 to form the drain electrode 1.

Further, using a metal mask (for example, a stainless mask), selectively in the guard ring region (B region),
For example, helium ions are implanted by the ion implantation method to form crystal defects in at least a part of the region (shown by hatching) 13. Further, heat treatment is performed to stabilize the electric characteristics of the device.

In the guard ring region of the thus-configured IGBT element, among minority carriers injected from the emitter region (substrate p ⁺ layer 2) of the internal bipolar transistor, via the base region (n ⁻ region 3). The amount reaching the collector region (p ⁺ layer 10) is reduced, and as a result, the current amplification factor β is reduced, as a result of the above equation 2, and as a result, the breakdown voltage BV _CEO of the guard ring region is reduced.
Is improved.

The formation of crystal defects is not limited to He ⁺ described above,
It is also possible by implanting Ar ions or H ⁺ ions, or irradiating with an electron beam or a neutron beam. FIG. 2 shows the structure of the second embodiment. The difference from FIG. 1 is that the n ⁺ layer 11 is selectively formed in the vicinity of the substrate pn junction 12 in the guard ring region (B region). The n ⁺ layer 11 selectively diffuses impurities on the surface of the p ⁺ layer 2, which is a semiconductor substrate, or forms an n ⁻ layer on the surface of the p ⁺ layer to a certain thickness and then selectively diffuses impurities on the surface. After that, by performing the manufacturing process shown in FIG. 1, it can be formed in the vicinity of the substrate pn junction 12.

In the guard ring region of the thus-configured IGBT element, minority carriers (holes) are injected from the emitter region (substrate p ⁺ layer 2) of the internal bipolar transistor to the base region (n ⁻ layer 3). This is suppressed, and the current amplification factor β shown in Formula 2 decreases as described above, and as a result, the breakdown voltage BV _{CEO in the} guard ring region increases.

Further, the first and second embodiments may be combined as in the third embodiment shown in FIG. According to this embodiment, the base region (n) of the minority carriers injected from the emitter region (substrate p ⁺ layer 2) of the intrinsic bipolar transistor in the guard ring region (B region).
^- region 3) was added to reduce the amount reaching the collector region (p ⁺ layer 10) via the emitter region (substrate p
Injection of minority carriers (holes) from the ⁺ layer 2) to the base region (n ⁻ layer 3) is suppressed, and as a result, the current amplification factor β shown in Formula 2 above is drastically reduced, and the breakdown voltage of the guard ring region is reduced. BV _CEO can be increased further.

In the above-described various embodiments, the p-type is used as the first conductivity type and the n-type is used as the second conductivity type. However, a p-channel type IGBT in which these conductivity types are reversed is used.
The present invention is effective for T.

[Brief description of drawings]

FIG. 1 is a sectional structural view of a cell region and an outer peripheral guard ring region of an IGBT according to a first embodiment of the present invention.

FIG. 2 is a sectional structural view of a cell region and an outer peripheral guard ring region of an IGBT according to a second embodiment of the present invention.

FIG. 3 is a sectional structural view of a cell region and an outer peripheral guard ring region of an IGBT according to a third embodiment of the present invention.

FIG. 4 is a sectional structural view of a cell region and a peripheral guard ring region of a conventional IGBT element.

[Explanation of symbols]

1 the drain electrode 2 P ⁺ layer (first semiconductor layer) 3 n ^- layer (second semiconductor layer) 4 p layer (third semiconductor layer) 5 n ⁺ layer (fourth semiconductor layer) 6 gate insulating film 7 a gate electrode 9 Source electrode 10 p layer (fifth semiconductor layer) 11 n ⁺ layer (sixth semiconductor layer) 12 substrate pn junction 13 lifetime killer formation region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location H01L 29/784 9168-4M H01L 29/78 321 J 9168-4M 321 K

Claims (5)

[Claims] 1. A first drain layer of the first conductivity type, a second drain layer of the second conductivity type in contact with an upper surface of the first drain layer, and a second drain layer formed in a region of the second drain layer. A first conductive type semiconductor layer formed on the surface of the second drain layer, and an insulated gate structure using the second conductive type semiconductor layer formed in the first conductive type semiconductor layer as a channel layer and a source layer, respectively. A first-conductivity-type guard ring structure formed in a peripheral region surrounding one region of the two drain layers, and first and second drain layers and a guard ring structure in the peripheral region selectively set only in the peripheral region And a means for reducing the current amplification factor of the bipolar transistor including the insulated gate bipolar transistor. 2. A first-conductivity-type first semiconductor layer, a second-conductivity-type second semiconductor layer in contact with the first-semiconductor layer, and a second semiconductor layer formed in the second-semiconductor layer. A third semiconductor layer of the first conductivity type which is partially formed on the surface of the layer so as to terminate the junction, and a junction which is formed in the third semiconductor layer and terminates at the surface of the third semiconductor layer. The fourth conductive type fourth semiconductor layer partially formed as described above, and the third semiconductor layer between the second semiconductor layer and the fourth semiconductor layer as a channel region, and at least a gate insulating film on the channel region. A gate electrode formed through the source electrode, a source electrode having a contact portion on both the third semiconductor layer and the fourth semiconductor layer, and a source electrode outside a region where a plurality of the third and fourth semiconductor layers are arranged. 2 semiconductor layers, formed on the second semiconductor layer An insulated gate bipolar transistor comprising: a peripheral region including a guard ring structure composed of the first conductive type fifth semiconductor layer; and a drain electrode for supplying a drain current through the first semiconductor layer. Minority carriers to the second semiconductor layer, which are selectively formed inside the second semiconductor layer or in the vicinity thereof from the edge portions of the arranged third and fourth semiconductor layers to the peripheral edge portion of the second semiconductor layer. An insulated gate bipolar transistor comprising means for limiting the implantation amount of or for shortening the life of minority carriers in the second semiconductor layer. 3. The insulated gate bipolar transistor according to claim 2, wherein the means for limiting the amount of the minority carriers injected into the second semiconductor layer is a defect formed by ion implantation. 4. The means for limiting the injection amount of minority carriers into the second semiconductor layer extends from an edge portion of the third and fourth semiconductor layers to a peripheral edge portion of the second semiconductor layer, The sixth semiconductor layer of the second conductivity type having a higher impurity concentration than that of the second semiconductor layer, the sixth semiconductor layer being formed at or near the junction surface between the semiconductor layer and the first semiconductor layer. Insulated gate bipolar transistor. 5. The means for limiting the injection amount of minority carriers into the second semiconductor layer extends from an edge portion of the third and fourth semiconductor layers to a peripheral edge portion of the second semiconductor layer, 4. The sixth conductivity type sixth semiconductor layer having an impurity concentration higher than that of the second semiconductor layer, which is formed at or near the junction surface between the semiconductor layer and the first semiconductor layer. Insulated gate bipolar transistor.