JPH03155167A - Vertical mosfet - Google Patents
Vertical mosfetInfo
- Publication number
- JPH03155167A JPH03155167A JP1294702A JP29470289A JPH03155167A JP H03155167 A JPH03155167 A JP H03155167A JP 1294702 A JP1294702 A JP 1294702A JP 29470289 A JP29470289 A JP 29470289A JP H03155167 A JPH03155167 A JP H03155167A
- Authority
- JP
- Japan
- Prior art keywords
- region
- diffusion region
- outermost
- source
- type diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 238000009792 diffusion process Methods 0.000 claims description 54
- 239000000758 substrate Substances 0.000 claims description 10
- 230000015556 catabolic process Effects 0.000 abstract description 16
- 230000002093 peripheral effect Effects 0.000 abstract description 3
- 238000009751 slip forming Methods 0.000 abstract description 2
- 230000003071 parasitic effect Effects 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 206010000060 Abdominal distension Diseases 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 208000024330 bloating Diseases 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明はアバランシェ降伏による破壊耐量を増大した縦
型ＭＯＳＦＥＴに関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a vertical MOSFET with increased breakdown resistance due to avalanche breakdown.
（ロ）従来の技術
縦型ＭＯ５ＦＥＴは、第５図に示すように、底部に高濃
度Ｎ０型層（１）を有するＮ−型シリコン基板（２）を
ドレインとして、その表面上に所定の間隔でゲート電極
（ポリＳｉゲート＞ （３）が配置され、このゲート電
極（３）の下にチャンネル部を作るように基体（２）表
面にＰ型拡散領域〈４）とＮ＋型ソース領域（５）を形
成したもので、ゲートへの電圧印加によってゲート下の
Ｐ型拡散領域（４）（チャンネル部）を通るドレイン電
流Ｉ０を制御するようにＭＯＳＦＥＴを動作させるもの
である（例えば、特開昭６３−２６０１７６号公報）。(b) Conventional technology As shown in FIG. 5, a vertical MO5FET uses an N- type silicon substrate (2) having a high concentration N0 type layer (1) at the bottom as a drain, and a predetermined interval on its surface. A gate electrode (poly-Si gate (3)) is placed on the surface of the substrate (2) to form a channel section under this gate electrode (3). ), and the MOSFET is operated so as to control the drain current I0 passing through the P-type diffusion region (4) (channel part) under the gate by applying a voltage to the gate (for example, 63-260176).
（６〉はＡＮ電極、（７）はガードリングである。(6> is an AN electrode, and (7) is a guard ring.
また、縦型ＭＯ３ＦＥＴのパターン形状には、Ｐ型拡散
領域（４）が点在するメツシュゲート型と、Ｐ型拡散領
域（４）が格子状に連続するマルチゲート型との２種類
がある。マルチゲート型のパターンは、第６図に示すと
おり基板（２）表面にＰ型拡散領域（４）を格子状に形
成し、格子状パターンの網目部分にゲート電極（３）を
点在させたもので、耐圧的に有利なことから特に高耐圧
型（例えば、４００ｖ以上）に利用される。Furthermore, there are two types of pattern shapes for vertical MO3FETs: a mesh gate type in which P-type diffusion regions (4) are scattered, and a multi-gate type in which P-type diffusion regions (4) are continuous in a lattice shape. As shown in Fig. 6, the multi-gate pattern has P-type diffusion regions (4) formed in a lattice pattern on the surface of the substrate (2), and gate electrodes (3) are dotted in the mesh portion of the lattice pattern. Since it is advantageous in terms of voltage resistance, it is particularly used for high voltage resistance types (for example, 400V or higher).
斯る縦型ＭＯ５ＦＥＴは、大電流高速スイッチングが可
能なので、モータ制御、スイッチングレギュレータ、Ｃ
ＲＴ偏向用として多用されている。Such a vertical MO5FET is capable of high-speed switching of large currents, so it can be used in motor control, switching regulators, and C
It is widely used for RT deflection.
（八）発明が解決しようとする課題
しかしながら、第７図のようにコイル負荷（７）をＭＯ
８）ランジスタ（８）でスイッチングする場合、リアク
トル負荷（７）を遮断した瞬間に高い電流変化率ｄ ｉ
／ ｄ ｔで大きなサージ電圧（９）が発生し、この
ようなサージ電圧がＭＯＳトランジスタ（８）のソース
・ドレイン間に印加きれることによりＭＯＳトランジス
タ（８）は容易にアバランシェ領域まで印加される。(8) Problems to be solved by the invention However, as shown in Fig. 7, the coil load (7) is
8) When switching with a transistor (8), the moment the reactor load (7) is cut off, a high current change rate di
A large surge voltage (9) is generated at /dt, and as such a surge voltage can be applied between the source and drain of the MOS transistor (8), the voltage is easily applied to the MOS transistor (8) up to the avalanche region.
アバランシェ領域まで印加されたＭＯＳトランジスタ（
８）は、第８図に示すように主にＰ型拡散領域（４）と
Ｎ−型基板（２）とが形成する接合ダイオード（１０）
がなだれ降伏することにより電流を吸収しようとする。MOS transistor applied up to the avalanche region (
8) is a junction diode (10) mainly formed by a P-type diffusion region (4) and an N-type substrate (2), as shown in FIG.
tries to absorb the current by avalanche breakdown.
ところが、ＭＯＳトランジスタ（８）はＮ＋ソース領域
（５）をエミッタ、Ｐ型拡散領域（４）をベース、Ｎ−
型基体（２）をコレクタとする寄生トランジスタ（１１
）が不可避的に形成きれてしまい、また、Ｎゝソース領
域（５）の底部はピンチ構造となるため、ソース領域（
５）とＰ型拡散領域（４）とのＰＮ接合はピンチ抵抗（
１２）により順バイアスきれる電位差に容易に達して寄
生トランジスタ（１１）が導通してしまう。−旦寄生ト
ランジスタ（１１）が導通すると、ＭＯＳ）ランジスタ
の阻止耐圧は寄生トランジスタ（１１）のｖｃｇ。まで
低下するので、アバランシェ電流が制御がきかない状態
で能動化したセルを流れ、結果的に素子が破壊されてし
まう現象がある。However, the MOS transistor (8) uses the N+ source region (5) as the emitter, the P-type diffusion region (4) as the base, and the N-
A parasitic transistor (11) whose collector is the type substrate (2)
) will inevitably be completely formed, and the bottom of the N source region (5) will have a pinch structure, so the source region (
5) and the P-type diffusion region (4) has a pinch resistance (
12), the potential difference that can break the forward bias is easily reached and the parasitic transistor (11) becomes conductive. - Once the parasitic transistor (11) becomes conductive, the blocking voltage of the MOS transistor is vcg of the parasitic transistor (11). As a result, avalanche current flows uncontrollably through the activated cell, resulting in destruction of the device.
そして、上記アバランシェ降伏は、空乏層（１３〉の内
部電界の差により基板（２）周囲のガードリング（７）
部分に近いＰ型拡散領域（４′）で生じ易い。The avalanche breakdown occurs when the guard ring (7) around the substrate (2) is caused by the difference in the internal electric field of the depletion layer (13).
This tends to occur in the P-type diffusion region (4') near the part.
ところが、マルチゲート型タイプは、Ｐ型拡散領域（４
）が連続するので、ガードリング（７）部分に近い領域
で生じた降伏電流（第５図ｉ）がセルのどこで寄生トラ
ンジスタ（１１）を導通きせるかはわからない。そのた
め、従来のマルチゲート型ＭＯＳトランジスタはアバラ
ンシェ降伏に対して無防備であり、破壊に至り易い欠点
があった。However, the multi-gate type has a P-type diffusion region (4
) are continuous, so it is not known where in the cell the breakdown current (FIG. 5i) generated in the region near the guard ring (7) will cause the parasitic transistor (11) to conduct. Therefore, conventional multi-gate MOS transistors are vulnerable to avalanche breakdown and have the disadvantage of being easily destroyed.
（ニ）課題を解決するための手段
本発明は上記従来の欠点に鑑み成されたもので、格子状
の拡散領域（２４）の最外周領域（２５）を内側の拡散
領域（２６）と分離し、前記最外周領域（２５）にはソ
ース領域（３０）を設けずにフローティング状態にする
と共に、最外周領域（２５）表面にソース電極（３５）
をコンタクトきせることにより、アバランシェ耐量を増
大した縦型ＭＯ８ＦＥＴを提供するものである。(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned conventional drawbacks, and the outermost peripheral region (25) of the lattice-shaped diffusion region (24) is separated from the inner diffusion region (26). The outermost region (25) is not provided with a source region (30) and is left in a floating state, and a source electrode (35) is provided on the surface of the outermost region (25).
The purpose of the present invention is to provide a vertical MO8FET with increased avalanche resistance by contacting.
（＊）作用
本発明によれば、アバランシェ降伏は先ず空乏層の伸び
が不安定な最外周のＰ型拡散領域（２５）で生じるので
、降伏電流は最外周領域（２５）に流れ込み、内側のＰ
型拡散領域（２６）と外側のＰ型拡散領域（２５）とは
分離されているので、前記降伏電流はセル内に流れ込む
こと無くソース電極（３５）に流れる。従って、内部セ
ルに降伏電流を流さずに済む。(*) Effect According to the present invention, avalanche breakdown first occurs in the outermost P-type diffusion region (25) where the extension of the depletion layer is unstable, so the breakdown current flows into the outermost region (25) and P
Since the type diffusion region (26) and the outer P type diffusion region (25) are separated, the breakdown current flows to the source electrode (35) without flowing into the cell. Therefore, no breakdown current needs to flow through the internal cells.
（へ）実施例
以下に本発明の一実施例を図面を参照しながら詳細に説
明する。(F) Example An example of the present invention will be described below in detail with reference to the drawings.
第１図は本発明の縦型ＭＯ８ＦＥＴを示す平面図、第２
図と第３図は夫々第１ｒｓＪの拡大平面図とＡＡ線拡大
断面図である。Figure 1 is a plan view showing the vertical MO8FET of the present invention, Figure 2 is a plan view showing the vertical MO8FET of the present invention.
The figure and FIG. 3 are an enlarged plan view and an enlarged sectional view taken along the line AA of the first rsJ, respectively.
共通ドレインとなるシリコン半導体基体（２１）は、裏
面電極形成用のＮ０型半導体層（２２）と、Ｎ−型半導
体層（２３）との２層構造から成る。Ｎ−型半導体層（
２３）の表面には、Ｐ型拡散領域（２４）が格子状に連
続的に形成され、且つ最外周のＰ型拡散領域（２５）は
、内側のＰ型拡散領域（２６）とは分離されて内側のＰ
型拡散領域（２６）を取り囲むように拡散形成される。The silicon semiconductor substrate (21) serving as the common drain has a two-layer structure including an N0 type semiconductor layer (22) for forming a back electrode and an N- type semiconductor layer (23). N-type semiconductor layer (
23), P-type diffusion regions (24) are continuously formed in a grid pattern, and the outermost P-type diffusion region (25) is separated from the inner P-type diffusion region (26). inside P
It is formed by diffusion so as to surround the mold diffusion region (26).
Ｐ型拡散領域（２４）の周囲には、これをさらに取り囲
むようにＰ型のガードリング（２７）が幾重にも形成さ
れる。（２８）はＮ０型チヤンネルストツパ、（２９）
はフィールド電極である。P-type guard rings (27) are formed in multiple layers around the P-type diffusion region (24) so as to further surround it. (28) is the N0 type channel stopper, (29)
is the field electrode.
内側のＰ型拡散領域（２６）の表面には、Ｎ＋型ソース
領域（３０）が形成され、ソース領域（３０）と基体（
２３）表面で挾まれたＰ型拡散領域（２４）の表面をチ
ャンネル部とする。チャンネル部（３１）上には、シリ
コン酸化膜から成るゲート絶縁膜（３２）を介してポリ
シリコンのゲート電極（３３）が格子状パターンの各網
目の上を覆うようにして配置きれている。内側のＰ型拡
散領域（２６）とは分離された最外周のＰ型拡散領域（
２５）にはソース領域（３０）を設けない。これで、最
外周のＰ型拡散領域（２５）はＭＯＳセルとして動作で
きないブローティングの状態となる０個々に独立したゲ
ート電極（３３）は、櫛歯状のアルミ電極（３４）によ
って共通接続され外部接続用の図示せぬポンディングパ
ッドに接続されている。Ｐ型拡散領域（２４）の表面に
は、Ｐ型拡散領域（２４）とソース領域（３０）の両方
にコンタクトするソース電極〈３５）が櫛歯状に形成さ
れて図示せぬソースポンディングパッドに接続されてい
る。An N+ type source region (30) is formed on the surface of the inner P type diffusion region (26), and the source region (30) and the substrate (
23) The surfaces of the P-type diffusion regions (24) sandwiched between the surfaces are used as channel portions. A polysilicon gate electrode (33) is disposed on the channel portion (31) via a gate insulating film (32) made of a silicon oxide film so as to cover each mesh of the grid pattern. The outermost P-type diffusion region (26) is separated from the inner P-type diffusion region (26).
25), no source region (30) is provided. Now, the outermost P-type diffusion region (25) is in a bloating state where it cannot operate as a MOS cell.The individual gate electrodes (33) are commonly connected by the comb-shaped aluminum electrode (34). It is connected to a bonding pad (not shown) for external connection. On the surface of the P-type diffusion region (24), a comb-shaped source electrode (35) that contacts both the P-type diffusion region (24) and the source region (30) is formed to form a source bonding pad (not shown). It is connected to the.
斯る構成の縦型ＭＯ３ＦＥＴにおいて、ソース・ドレイ
ン間にリアクトル負荷の逆起電圧によってアバランシェ
領域を超える逆方向電圧が印加された場合、その降伏電
流ｉは、空乏層（３６）の内部電界が高い部分つまりガ
ードリング（２７）に近い部分で特に生じ易く、従って
最外周のＰ型拡散領域（２５）に流入してソース電極（
３５）へと流れる。最外周のＰ型拡散領域（２５）はＮ
＋型ソース領域〈３０）が存在しないので寄生トランジ
スタは形成されない。また、最外周のＰ型拡散領域（２
５）と内側Ｐ型拡散領域（２６）とは分離されているか
ら、降伏電流ｉがＰ型拡散領域（２４）を伝ってＭＯＳ
セル部分に流れ込むことも無い。従って、ＭＯＳセル部
分において寄生トランジスタが導通してしまうことを防
止できる。In a vertical MO3FET with such a configuration, when a reverse voltage exceeding the avalanche region is applied between the source and drain due to the back electromotive force of the reactor load, the breakdown current i is caused by the high internal electric field of the depletion layer (36). It is particularly likely to occur in the part near the guard ring (27), and therefore flows into the outermost P-type diffusion region (25) and forms the source electrode (
35). The outermost P-type diffusion region (25) is N
Since there is no +-type source region <30), no parasitic transistor is formed. In addition, the outermost P-type diffusion region (2
5) and the inner P-type diffusion region (26) are separated, the breakdown current i is transmitted through the P-type diffusion region (24) and the MOS
It does not flow into the cell part. Therefore, it is possible to prevent the parasitic transistor from becoming conductive in the MOS cell portion.
上記Ｐ型拡散領域（２４）の分離は、以下の手法で行う
のが最も簡便である。先ず第４図Ａに示すようにＮ−型
半導体層（２３）の表面にＰ型拡散領域（２４）とＰ型
ガードリング領域（２７）とを選択拡散し、その時に形
成した表面の厚い熱酸化膜（３７）をホトエツチングし
てＭＯＳセル部分表面を開孔する。The P-type diffusion region (24) is most easily separated by the following method. First, as shown in FIG. 4A, a P-type diffusion region (24) and a P-type guard ring region (27) are selectively diffused on the surface of the N-type semiconductor layer (23), and the thick heat of the surface formed at that time is The oxide film (37) is photoetched to open a hole on the surface of the MOS cell portion.
Ｐ型拡散領域（２４）は内側（２６）と最外周（２５）
とを分離したホトマスクで形成される。また、ＭＯＳセ
ル部の開口用水トマスクは、第２図のライン（３８）で
示すように最も外側のゲート電極（３３）が厚い酸化膜
（３７〉に半分掛かるようなホトマスクに変更される。P-type diffusion region (24) is inside (26) and outermost periphery (25)
It is formed using a separate photomask. Further, the water mask for opening the MOS cell portion is changed to a photomask in which the outermost gate electrode (33) covers half of the thick oxide film (37), as shown by line (38) in FIG.
次に第４図Ｂに示すようにゲート酸化膜（３２）を形成
した後ポリシリコン層の堆積とホトエツチングによりゲ
ート電極（３３）を形成する。先の工程で厚い酸化膜（
３７）の端部が従来より内側にきているので、最も外側
のゲート電極（３３）はその約半分が厚い酸化膜（３７
）上を延在する。Next, as shown in FIG. 4B, after forming a gate oxide film (32), a gate electrode (33) is formed by depositing a polysilicon layer and photo-etching. A thick oxide film (
Since the end of the gate electrode (37) is on the inside than before, about half of the outermost gate electrode (33) is covered with a thick oxide film (37).
) extends above.
そして第４図Ｃに示すように、ゲート電極り３３）をマ
スクとしてＰ型拡散領域（２４）と重なるようにボロン
をチャンネルインプラする。最外周のＰ型拡散領域（２
５〉へは、厚い酸化膜（３７〉が選択マスクとなるので
チャンネルインプラされない、また、厚い酸化膜〈３７
）が選択マスクとなることにより、最外周のＰ型拡散領
域（２５）と内側のＰ型拡散領域（２６）とがチャンネ
ルインプラによって導入された不純物によって第２図図
示Ａの部分で連結されることもない。その後、チャンネ
ル拡散をしてＰ型拡散領域（２４）を所望深さまで拡散
し、リンをインプラしてソース領域（３０）を形成する
。ソース領域（３０）もまた、厚い酸化膜（２７）で遮
られることによって、Ｎ−型半導体層＜２３）との短絡
が防止される。Then, as shown in FIG. 4C, boron is channel-implanted using the gate electrode layer 33) as a mask so as to overlap the P-type diffusion region (24). The outermost P-type diffusion region (2
5>, the thick oxide film (37>) serves as a selection mask, so channel implantation is not performed.
) serves as a selection mask, so that the outermost P-type diffusion region (25) and the inner P-type diffusion region (26) are connected at the part A in FIG. 2 by the impurity introduced by channel implantation. Not at all. Thereafter, channel diffusion is performed to diffuse the P type diffusion region (24) to a desired depth, and phosphorus is implanted to form the source region (30). The source region (30) is also shielded by a thick oxide film (27) to prevent short circuits with the N-type semiconductor layer <23).
斯上した製造方法によれば、最外周のＰ型拡散領域（２
５）と内側のＰ型拡散領域（２６）とを分離するために
、従来のものに比べ、第４図Ａ工程のＰ型拡散領域（２
４）形成用のホトマスクと、厚い酸化膜〈２７）をエツ
チング除去するためのホトマスクの２枚を設計変更する
ものの、残りのホトマスクは厚い酸化膜（２７）をマス
クとして活用できるので変更せずに済み、変更マスクの
枚数を最少限にできる。According to the above manufacturing method, the outermost P-type diffusion region (2
5) and the inner P-type diffusion region (26), the P-type diffusion region (26) in the step A in FIG.
4) Although the design of two photomasks will be changed: the photomask for formation and the photomask for etching away the thick oxide film (27), the remaining photomasks will remain unchanged as the thick oxide film (27) can be used as a mask. The number of changed masks can be minimized.
（ト）発明の効果
以上に説明した如く、本発明によれば最外周のＰ型拡散
領域（２５）を内側の領域（２６）と分離したので、素
子のアバランシェ領域における降伏型ｉｔがＰ型拡散領
域（２４）を伝ってＭＯＳセル部に流れ込むことが無く
、従ってＭＯＳセルの寄生トランジスタが導通しないの
で、素子を破壊から保護でき、素子のアバランシェ耐量
を増大できる。(G) Effects of the Invention As explained above, according to the present invention, the outermost P-type diffusion region (25) is separated from the inner region (26), so that the breakdown type IT in the avalanche region of the element is P-type. Since it does not flow into the MOS cell portion through the diffusion region (24), and therefore the parasitic transistor of the MOS cell does not become conductive, the device can be protected from destruction and the avalanche resistance of the device can be increased.
また、厚い酸化膜り３７）を活用することにより、設計
変更に要するホトマスクの枚数を最少限に抑えることが
できる。Furthermore, by utilizing the thick oxide film 37), the number of photomasks required for design changes can be minimized.
第１図、第２図と第３図は夫々本発明を説明するための
平面図、拡大平面図と第１図のＡＡ線拡大断面図、第４
図Ａ−Ｃはその製造方法を説明するための断面図、第５
図〜第８図は夫々従来例を説明するための断面図、平面
図、回路図および拡大断面図である。
第２図
第５図
第６図
第
囚
第８図1, 2, and 3 are a plan view, an enlarged plan view, an enlarged sectional view taken along line AA of FIG. 1, and FIG.
Figures A-C are cross-sectional views for explaining the manufacturing method.
8 are a sectional view, a plan view, a circuit diagram, and an enlarged sectional view, respectively, for explaining the conventional example. Figure 2 Figure 5 Figure 6 Prisoner Figure 8
Claims (2)
散領域と、 前記逆導電型拡散領域の表面に形成した一導電型のソー
ス領域と、 前記ソース領域と前記基体の表面にはさまれたチャンネ
ル部上に絶縁膜を介して配置したゲート電極と、 前記ソース領域と前記逆導電型拡散領域との両方にコン
タクトするソース電極とを具備する縦型ＭＯＳＦＥＴに
おいて、 前記格子状拡散領域の最外周の拡散領域を内側の拡散領
域とは分離し、ソース領域を除去してフローティング状
態にすると共に、前記ソース電極を前記最外周拡散領域
にもコンタクトさせたことを特徴とする縦型ＭＯＳＦＥ
Ｔ。(1) A semiconductor substrate of one conductivity type serving as a common drain, a diffusion region of an opposite conductivity type formed in a lattice shape on the surface of the semiconductor substrate, and a source of one conductivity type formed on the surface of the diffusion region of the opposite conductivity type. a gate electrode disposed on a channel portion sandwiched between the source region and the surface of the base body with an insulating film interposed therebetween; and a source electrode in contact with both the source region and the opposite conductivity type diffusion region. In the vertical MOSFET, the outermost diffusion region of the lattice-shaped diffusion region is separated from the inner diffusion region, the source region is removed to create a floating state, and the source electrode is connected to the outermost diffusion region. A vertical MOSFE characterized by being in contact with
T.
領域が囲むことを特徴とする請求項第１項に記載の縦型
ＭＯＳＦＥＴ。(2) The vertical MOSFET according to claim 1, wherein a guard ring region surrounds the outermost diffusion region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1294702A JPH03155167A (en) | 1989-11-13 | 1989-11-13 | Vertical mosfet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1294702A JPH03155167A (en) | 1989-11-13 | 1989-11-13 | Vertical mosfet |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03155167A true JPH03155167A (en) | 1991-07-03 |
Family
ID=17811195
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1294702A Pending JPH03155167A (en) | 1989-11-13 | 1989-11-13 | Vertical mosfet |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03155167A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5430316A (en) * | 1992-02-18 | 1995-07-04 | Sgs-Thomson Microeletronics, S.R.L. | VDMOS transistor with improved breakdown characteristics |
| US5430324A (en) * | 1992-07-23 | 1995-07-04 | Siliconix, Incorporated | High voltage transistor having edge termination utilizing trench technology |
| US5905294A (en) * | 1996-01-24 | 1999-05-18 | Toyota Jidosha Kabushihi Kaisha | High rated voltage semiconductor device with floating diffusion regions |
| WO2000063972A1 (en) * | 1999-04-21 | 2000-10-26 | Infineon Technologies Ag | Semiconductor component |
| JP2003069016A (en) * | 2001-08-29 | 2003-03-07 | Denso Corp | Semiconductor device and method of manufacturing the same |
| US6639260B2 (en) | 2000-12-18 | 2003-10-28 | Denso Corporation | Semiconductor device having a vertical semiconductor element |
-
1989
- 1989-11-13 JP JP1294702A patent/JPH03155167A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5430316A (en) * | 1992-02-18 | 1995-07-04 | Sgs-Thomson Microeletronics, S.R.L. | VDMOS transistor with improved breakdown characteristics |
| US5589405A (en) * | 1992-02-18 | 1996-12-31 | Sgs-Thomson Microelectronics, S.R.L. | Method for fabricating VDMOS transistor with improved breakdown characteristics |
| US5430324A (en) * | 1992-07-23 | 1995-07-04 | Siliconix, Incorporated | High voltage transistor having edge termination utilizing trench technology |
| US5605852A (en) * | 1992-07-23 | 1997-02-25 | Siliconix Incorporated | Method for fabricating high voltage transistor having trenched termination |
| US5905294A (en) * | 1996-01-24 | 1999-05-18 | Toyota Jidosha Kabushihi Kaisha | High rated voltage semiconductor device with floating diffusion regions |
| WO2000063972A1 (en) * | 1999-04-21 | 2000-10-26 | Infineon Technologies Ag | Semiconductor component |
| US6936866B2 (en) | 1999-04-21 | 2005-08-30 | Infineon Technologies Ag | Semiconductor component |
| US6639260B2 (en) | 2000-12-18 | 2003-10-28 | Denso Corporation | Semiconductor device having a vertical semiconductor element |
| US6982459B2 (en) | 2000-12-18 | 2006-01-03 | Denso Corporation | Semiconductor device having a vertical type semiconductor element |
| JP2003069016A (en) * | 2001-08-29 | 2003-03-07 | Denso Corp | Semiconductor device and method of manufacturing the same |
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