JP2527160B2 - Field effect type semiconductor device - Google Patents
Field effect type semiconductor deviceInfo
- Publication number
- JP2527160B2 JP2527160B2 JP60262769A JP26276985A JP2527160B2 JP 2527160 B2 JP2527160 B2 JP 2527160B2 JP 60262769 A JP60262769 A JP 60262769A JP 26276985 A JP26276985 A JP 26276985A JP 2527160 B2 JP2527160 B2 JP 2527160B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- type semiconductor
- conductivity type
- semiconductor region
- conductivity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 74
- 230000005669 field effect Effects 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 description 17
- 230000003071 parasitic effect Effects 0.000 description 13
- 230000006378 damage Effects 0.000 description 9
- 230000005684 electric field Effects 0.000 description 8
- 239000000969 carrier Substances 0.000 description 7
- 238000011084 recovery Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000007423 decrease Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000003321 amplification Effects 0.000 description 2
- 230000020169 heat generation Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- TVZRAEYQIKYCPH-UHFFFAOYSA-N 3-(trimethylsilyl)propane-1-sulfonic acid Chemical compound C[Si](C)(C)CCCS(O)(=O)=O TVZRAEYQIKYCPH-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は電界効果型半導体装置に関し、特に破壊耐
量を改善した電界効果型半導体装置に関するものであ
る。TECHNICAL FIELD The present invention relates to a field effect semiconductor device, and more particularly to a field effect semiconductor device having improved breakdown resistance.
従来、この種の半導体装置として第２図に示すものが
あつた。第２図は、従来のパワーMOS電界効果トランジ
スタ（以下、電界効果トランジスタをFETと記す）の断
面図である。初めにこの装置の構成について説明する。
ドレイン電極８表面に半導体基板である第１導電形高濃
度ドレイン領域1bが形成されており、この領域表面に第
１導電形低濃度ドレイン領域1aが形成されている。第１
導電形低濃度ドレイン領域1aの表面に第２導電形半導体
領域２が間隔を隔てて複数個形成されており、各第２導
電形半導体領域２内に第１導電形ソース領域３が中央部
を開けて形成されている。各第２導電形半導体領域２は
凸部21を有しており、７はチヤンネル形成領域である。
各第１導電形ソース領域３表面の一部およびソース領域
３の中央部の第２導電形半導体領域２表面にソース電極
６が形成されている。また、各第２導電形半導体領域２
間の第１導電形低濃度ドレイン領域1a表面、第１導電形
低濃度ドレイン領域1aと各第１導電形ソース領域３間の
各第２導電形半導体領域２表面、および各第１導電形ソ
ース領域３表面の一部に絶縁膜４が形成されている。こ
の絶縁膜４の内部にゲート電極５が形成されており、絶
縁膜４表面に上述のソース電極６が延びている。パワー
MOSFETは、このような基本ユニツトが多数並列接続され
た構造をしている。Conventionally, there is a semiconductor device of this type shown in FIG. FIG. 2 is a cross-sectional view of a conventional power MOS field effect transistor (hereinafter, the field effect transistor is referred to as FET). First, the configuration of this device will be described.
A first conductivity type high concentration drain region 1b which is a semiconductor substrate is formed on the surface of the drain electrode 8, and a first conductivity type low concentration drain region 1a is formed on the surface of this region. First
A plurality of second conductivity type semiconductor regions 2 are formed at intervals on the surface of the conductivity type low concentration drain region 1a, and a first conductivity type source region 3 has a central portion in each second conductivity type semiconductor region 2. It is formed by opening. Each second conductivity type semiconductor region 2 has a convex portion 21, and 7 is a channel forming region.
A source electrode 6 is formed on part of the surface of each first conductivity type source region 3 and on the surface of the second conductivity type semiconductor region 2 at the center of the source region 3. In addition, each second conductivity type semiconductor region 2
The surface of the first conductivity type low concentration drain region 1a between them, the surface of each second conductivity type semiconductor region 2 between the first conductivity type low concentration drain region 1a and each first conductivity type source region 3, and each first conductivity type source The insulating film 4 is formed on a part of the surface of the region 3. A gate electrode 5 is formed inside the insulating film 4, and the above-mentioned source electrode 6 extends on the surface of the insulating film 4. power
The MOSFET has a structure in which many such basic units are connected in parallel.
次にこの装置の動作について説明する。ドレイン電極
８とソース電極６間にドレイン電圧を印加した状態でゲ
ート電極５とソース電極６間にゲート電圧を印加する
と、チヤンネル形成領域７にチヤンネルが形成され、ド
レイン電極８とソース電極６間にドレイン電流が流れ
る。このとき、ゲート電極５とソース電極６間に印加す
るゲート電圧を制御することによつて、ドレイン電極８
とソース電極６間を流れるドレイン電流を制御すること
ができる。ソース電極６による、第２導電形半導体領域
２とソース領域３の短絡は、チヤンネル形成領域７の電
位を固定さすために不可欠である。Next, the operation of this device will be described. When the gate voltage is applied between the gate electrode 5 and the source electrode 6 in the state where the drain voltage is applied between the drain electrode 8 and the source electrode 6, a channel is formed in the channel forming region 7, and the channel is formed between the drain electrode 8 and the source electrode 6. Drain current flows. At this time, the drain electrode 8 is controlled by controlling the gate voltage applied between the gate electrode 5 and the source electrode 6.
And the drain current flowing between the source electrode 6 can be controlled. The short circuit between the second conductivity type semiconductor region 2 and the source region 3 by the source electrode 6 is indispensable for fixing the potential of the channel forming region 7.
パワーMOSFETは、小数キヤリアの注入、蓄積が基本的
には問題にならないため高速動作が可能であるという利
点がある反面、バイポーラ（以下、BIPと記す）トラン
ジスタ、サイリスタでは少数キヤリアによる伝導度変調
により高抵抗領域のON抵抗が下がるという機構がないた
め、ON抵抗がBIP素子に比べて大きい。このため、パワ
ーMOSFETでは活性部の周辺長の増大と、高抵抗領域であ
る第１導電形低濃度ドレイン領域1aの薄層化が電流容量
増大のために懸案となつている。第１導電形低濃度ドレ
イン領域1aは、半導体素子の耐圧特性が許す限り薄くす
るのが効果的な設計といえる。それにもかかわらず、凸
部21が存在するのは次の理由による。The power MOSFET has the advantage that it can operate at high speed because the injection and storage of decimal carriers does not become a problem basically, but on the other hand, bipolar (hereinafter referred to as BIP) transistors and thyristors have conductivity modulation by a small number of carriers. Since there is no mechanism that the ON resistance in the high resistance region decreases, the ON resistance is higher than that of the BIP element. Therefore, in the power MOSFET, increasing the peripheral length of the active portion and thinning the first-conductivity-type low-concentration drain region 1a, which is a high-resistance region, are problems for increasing the current capacity. It can be said that an effective design is to make the first-conductivity-type low-concentration drain region 1a as thin as the withstand voltage characteristics of the semiconductor element allow. Nevertheless, the convex portion 21 exists for the following reason.
第３図は、パワーMOSFETの出力特性を示す図である。
第２導電形半導体領域２に凸部21がない場合、降伏電流
が流れるとパワーMOSFETは瞬時に破壊する傾向がある。
以下にこの破壊モードの説明を行なう。第4A図は、凸部
21がない場合のパワーMOSFETの基本構成単位の断面図で
あり、第4B図は、この部分の等価回路を示す図である。
ソース−ドレイン間に印加した電圧を増大させていき、
第１導電形低濃度ドレイン領域1aと第２導電形半導体領
域２の降伏電圧値に達すると、第4A図中に矢印で示した
降伏電流が流れる。第１導電形ソース領域３の両端で
は、第4B図に示すように実質的にBIPトランジスタが寄
生している構造となつている。このため、第１導電形ソ
ース領域３の下に流れ込む電流Jcは、抵抗Raを経てソー
ス電極６から流れ出るのであるが、以下の１式の条件を
満すとこの寄生トランジスタが導通する状態が出現す
る。FIG. 3 is a diagram showing the output characteristics of the power MOSFET.
If the second conductivity type semiconductor region 2 does not have the protrusion 21, the power MOSFET tends to be instantly destroyed when a breakdown current flows.
Hereinafter, this destruction mode will be described. Figure 4A shows the convex
FIG. 4B is a cross-sectional view of the basic structural unit of the power MOSFET in the case where 21 is not provided, and FIG. 4B is a diagram showing an equivalent circuit of this portion.
Increasing the voltage applied between the source and drain,
When the breakdown voltage values of the first-conductivity-type low-concentration drain region 1a and the second-conductivity-type semiconductor region 2 are reached, the breakdown current indicated by the arrow in FIG. 4A flows. At both ends of the first conductivity type source region 3, BIP transistors are substantially parasitic as shown in FIG. 4B. Therefore, the current Jc flowing into the source region 3 of the first conductivity type flows out from the source electrode 6 via the resistance Ra, but if the condition of the following formula 1 is satisfied, a state in which this parasitic transistor becomes conductive appears. To do.
0.6V＜Jc＊Ra ……（１） この現象は、パワーMOSFETのごく一部の領域でまず起
こるし、導通した後も安定な状態はとり得ず、ブロツキ
ング発振状態に入る。このような状況で半導体素子は短
時間で破壊する。0.6V <Jc * Ra (1) This phenomenon occurs first in a small part of the power MOSFET, and it cannot reach a stable state even after conduction, and enters the blocking oscillation state. In such a situation, the semiconductor element is destroyed in a short time.
このモードの破壊は、第２導電形半導体領域３に凸部
21を形成すれば、降伏は第２導電形半導体領域２の中央
のみで起こるようになり、第１導電形ソース領域３下の
降伏電流を小さくすることと、第１導電形ソース領域３
下の抵抗Raが小さくなることから著しく改善できる。こ
のように、従来の構造においてもソース−ドレイン間の
降伏現象（一般にいう半導体素子の一時降伏現象）には
対処できている。The destruction of this mode is caused by the protrusion on the second conductivity type semiconductor region 3.
By forming 21, the breakdown occurs only in the center of the second conductivity type semiconductor region 2, and the breakdown current under the first conductivity type source region 3 is reduced.
Since the lower resistance Ra becomes small, it can be remarkably improved. As described above, even in the conventional structure, the breakdown phenomenon between the source and the drain (generally called the temporary breakdown phenomenon of the semiconductor element) can be dealt with.
一般にパワーMOSFETは、BIPトランジスタで深刻な問
題となる２次破壊現象がないと言われているが、この発
明の対象にしている縦形のパワーMOSFETには、寄生トラ
ンジスタがあるため２次破壊現象が起きるという問題点
があつた。この現象は、高電圧、高速スイツチング動作
で起きやすいのであるが、通常のスイツチング・レギユ
レータのように、半導体素子に印加される電圧と電流の
位相がずれている場合には問題にならない。すなわち、
半導体素子に電流が流れたまま高電圧が印加される動作
モードで初めて起きる現象である。Generally, it is said that the power MOSFET does not have a secondary breakdown phenomenon which is a serious problem in the BIP transistor. However, the vertical power MOSFET which is the target of the present invention has a parasitic transistor, so that the secondary breakdown phenomenon does not occur. There was a problem that it would happen. This phenomenon is likely to occur in a high-voltage, high-speed switching operation, but it does not cause a problem when the voltage and current applied to the semiconductor element are out of phase as in a normal switching regulator. That is,
This is a phenomenon that occurs for the first time in an operation mode in which a high voltage is applied while a current flows through a semiconductor element.
たとえば、第５図に示すインバータ回路で高速スイツ
チングを行なうと、この２次破壊現象はたやすく発生す
る。この回路で負荷（Ｌ）50に流れる電流を制御するた
めには、対角線上に配置されたパワーMOSFET40a,40dの
対あるいはパワーMOSFET40b,40cの対を任意の割合でON,
OFFすることによつて可能である。負荷（Ｌ）50を流れ
る電流は連続するから、パワーMOSFET40a,40dの対をOFF
にしておいて、パワーMOSFET40b,40cの対をON,OFFさす
場合、パワーMOSFET40b,40cがOFFのとき、負荷（Ｌ）50
を流れる電流はパワーMOSFET40a,40dのそれぞれと逆並
列に接続されている還流ダイオード41a,41dを通つて電
源に戻ることになる。この還流ダイオードは高速用のも
のが必要なので、パワーMOSFETチツプとは別の素子が接
続されているのであるが、第4B図に示すように、パワー
MOSFETの内部には、ダイオード領域が内蔵されている構
造となつている。このため、還流ダイオードを流れるべ
き還流電流の一部は、パワーMOSFETチツプ中を流れるこ
とになる。この状態に続いて、OFF状態のパワーMOSFET4
0b,40cにON信号を入力した時点以降の（ａ），（ｄ）側
の還流ダイオード41a,41dの電圧Vd波形と、パワーMOSFE
T40b,40cに流れる電流Im波形の例を第６図に示す。（特
にパワーMOSFETのスイツチング・スピードを制御しなか
つた場合）パワーMOSFET40b,40cがONすると、（ａ），
（ｄ）側の還流ダイオード41a,41dのリカバリー電流が
ほぼ直線的に増大していく。この上昇率は、電源電圧Ｖ
CCと配線のインダクタンスＬoの比ＶCC/Loで決まつてい
る。リカバリーしていない間は、還流ダイオード41a,41
dはごく低いインピーダンスの値をとり、パワーMOSFET4
0b,40cが電源電圧を保持している。すなわち、パワーMO
SFET40b,40cは電源電圧が印加されたまま大電流が流れ
る状態にさらされる（この状態は、一般に短絡状態と呼
ばれている）。（ａ），（ｄ）側の素子には、リカバリ
ー期間の途中から急峻に電圧が加わり始め、リカバリー
電流の減衰時に過大なピーク値をとる。このような短絡
状態は、特に高周波動作で還流ダイオードのリカバリー
特性が悪い場合著しいパワー・ロスをもたらしパワーMO
SFETの破壊の原因となることがある。このモードの破壊
は、典型としては発熱による温度上昇が主な要因であ
り、２次破壊現象ではない。For example, when high speed switching is performed in the inverter circuit shown in FIG. 5, this secondary breakdown phenomenon easily occurs. In order to control the current flowing through the load (L) 50 with this circuit, the pair of power MOSFETs 40a, 40d or the pair of power MOSFETs 40b, 40c arranged diagonally can be turned on at an arbitrary ratio.
It is possible to turn it off. Since the current flowing through the load (L) 50 is continuous, turn off the pair of power MOSFETs 40a and 40d.
When turning on and off the pair of power MOSFETs 40b and 40c, when the power MOSFETs 40b and 40c are off, the load (L) 50
The current flowing through the power supply returns to the power supply through the freewheeling diodes 41a and 41d connected in antiparallel with the power MOSFETs 40a and 40d, respectively. Since this freewheeling diode is required for high speed, an element different from the power MOSFET chip is connected, but as shown in Figure 4B,
The structure is such that the diode region is built inside the MOSFET. Therefore, a part of the return current that should flow through the return diode flows through the power MOSFET chip. Following this state, the power MOSFET 4 in the OFF state
The voltage Vd waveforms of the free wheeling diodes 41a and 41d on the (a) and (d) sides after the ON signal is input to 0b and 40c, and the power MOSFE
An example of the waveform of the current Im flowing through T40b and 40c is shown in FIG. (Especially when the switching speed of the power MOSFET is not controlled) When the power MOSFETs 40b and 40c are turned on, (a),
The recovery currents of the free wheeling diodes 41a and 41d on the (d) side increase almost linearly. This rate of increase is the power supply voltage V
It is determined by the ratio V CC / L o of CC and the inductance L o of the wiring. While not recovering, free wheeling diodes 41a, 41
d has a very low impedance value and power MOSFET 4
0b and 40c hold the power supply voltage. That is, power MO
The SFETs 40b and 40c are exposed to a state in which a large current flows while the power supply voltage is being applied (this state is generally called a short circuit state). A voltage suddenly starts to be applied to the elements on the sides (a) and (d) from the middle of the recovery period and takes an excessive peak value when the recovery current is attenuated. Such a short-circuited state causes a significant power loss especially when the recovery characteristic of the free wheeling diode is bad at high frequency operation.
This may cause damage to the SFET. Typically, this mode of destruction is mainly caused by an increase in temperature due to heat generation, and is not a secondary destruction phenomenon.
パワーMOSFETで問題となる２次破壊は、上述の
（ａ），（ｄ）側のパワーMOSFETで起こる。（ａ），
（ｄ）側のパワーMOSFETが破壊するための必要条件は、
次のものである。The secondary breakdown which is a problem in the power MOSFET occurs in the power MOSFETs on the above (a) and (d) sides. (A),
The necessary conditions for the power MOSFET on the (d) side to break down are:
It is the next one.
（１） 還流電流がパワーMOSFETに流れること（パワー
MOSFETに直列にダイオードを結線し、還流電流が専ら還
流ダイオードにのみ流れるようにすると破壊は起こらな
い）。(1) The return current flows through the power MOSFET (power
If you connect a diode in series with the MOSFET and let the freewheeling current flow exclusively to the freewheeling diode, no destruction will occur.
（２） 還流電流のリカバリー時間が、還流ダイオード
よりもパワーMOSFETの方が長いこと（還流ダイオードに
高速用でなく通常型を使用すれば破壊は起きない）。(2) The recovery time of the freewheeling current is longer in the power MOSFET than in the freewheeling diode (no damage occurs if the normal type is used for the freewheeling diode instead of for high speed).
（３） リカバリー動作時に加わる電圧の立ち上がりが
急峻であること（スナバをつけ電圧の立ち上がりを抑え
ると破壊は起きない）。(3) The rise of the voltage applied during the recovery operation is steep (breakdown does not occur if a snubber is used to suppress the rise of the voltage).
これらは、すべてBIPトランジスタをインバータに使
用した場合に問題となる２次破壊現象と基本的に同一で
ある。このモードの２次破壊現象は、次のように説明し
得る。還流時にわずかでもパワーMOSFETに電流が流れ、
引続きリカバリー時に急峻な電圧が印加されるまでの間
に、パワーMOSFET内の接合がリカバリーされきれない場
合を考える。このとき、高抵抗領域である第１導電形低
濃度ドレイン領域1aに残留している少数キヤリアは、電
圧が印加されると同時に電界により加速されソース側の
第２導電形半導体領域２に移動していく。高電圧の立ち
上がりが極めて急峻な場合には、残留している少数キヤ
リアがすべて第２導電形半導体領域２に到達するまで
に、電界による少数キヤリアのなだれ増倍現象が無視で
きなくなり得る。第２導電形半導体領域２に移動する少
数キヤリアは、第１導電形ソース電極３の両端部に形成
されている寄生トランジスタにとつてベース電流が供給
されていることに相当する。すなわち、少数キヤリアの
なだれ増倍現象が１式で示す条件を満せば、寄生トラン
ジスタは導通する。寄生トランジスタが導通すると、第
１導電形低濃度ドレイン領域1aに新たなキヤリアが供給
されるわけで、このキヤリアが、なだれ増倍現象により
再び寄生トランジスタのベース領域に注入されるという
生帰還ループが成立し得る。この正帰還ループの存立条
件は、基本的に高抵抗領域である第１導電形低濃度ドレ
イン領域1a中の電界強度、寄生トランジスタのエミツタ
・ベース間の抵抗Ra値と直流電流増幅率ｈFE値に依存す
る。すなわち、電界強度が強く、抵抗Raと直流電流増幅
率ｈFEが大きいと、この正帰還は簡単に起こり得る。一
旦正帰還状態に入ると、電源電圧が下がり電界強度が小
さくならない限りこの領域の導通は止まることはない。
この状況は、半導体素子の局所領域に高電圧が印加され
たまま大電流密度動作をしているわけで、素子は早晩発
熱による温度上昇が直接の原因となつて破壊することに
なる。結局、このような現象を低減するのに第２導電形
半導体領域２の凸部21は次の点で効果的である。These are basically the same as the secondary breakdown phenomenon that becomes a problem when BIP transistors are used in an inverter. The secondary destruction phenomenon in this mode can be explained as follows. Even a small amount of current flows through the power MOSFET during reflux,
Consider a case where the junction in the power MOSFET cannot be completely recovered before a steep voltage is applied during recovery. At this time, the minority carriers remaining in the first-conductivity-type low-concentration drain region 1a, which is a high-resistance region, are accelerated by the electric field at the same time when a voltage is applied and move to the second-conductivity-type semiconductor region 2 on the source side. To go. When the rise of the high voltage is extremely steep, the avalanche multiplication phenomenon of the minority carriers due to the electric field may not be ignored until all the remaining minority carriers reach the second conductivity type semiconductor region 2. The minority carriers that move to the second conductivity type semiconductor region 2 correspond to the base current being supplied to the parasitic transistors formed at both ends of the first conductivity type source electrode 3. That is, if the avalanche multiplication phenomenon of the minority carriers satisfies the condition shown by the equation 1, the parasitic transistor becomes conductive. When the parasitic transistor becomes conductive, a new carrier is supplied to the first-conductivity-type low-concentration drain region 1a, and this carrier is injected into the base region of the parasitic transistor again due to the avalanche multiplication phenomenon, which causes a live feedback loop. Can be established. The existence condition of this positive feedback loop is basically the electric field strength in the first conductivity type low concentration drain region 1a which is a high resistance region, the resistance Ra value between the emitter and base of the parasitic transistor and the direct current amplification factor h FE value. Depends on. That is, if the electric field strength is high and the resistance Ra and the direct current amplification factor h FE are large, this positive feedback can easily occur. Once in the positive feedback state, conduction in this region does not stop unless the power supply voltage decreases and the electric field strength decreases.
In this situation, a high voltage is applied to a local region of the semiconductor device while operating at a high current density, and the device is destroyed due to a temperature rise due to heat generation sooner or later. As a result, the projection 21 of the second conductivity type semiconductor region 2 is effective in reducing such a phenomenon in the following point.
（１） なだれ増倍現象の発生部を寄生トランジスタ動
作が起こりやすい場所より遠ざける。(1) Place the avalanche multiplication phenomenon occurrence part away from the place where parasitic transistor operation is likely to occur.
（２） 抵抗Raを小さくする。(2) Reduce the resistance Ra.
しかしながら、この凸部21は悪影響も及ぼし得る。寄
生トランジスタのなだれ増倍現象を抑えるためには凸部
21を深くすればよいが、その場合、なだれ増倍現象の発
生部を寄生トランジスタ動作が起こりやすい場所より遠
ざけるという効果は小さくなる。また、凸部21を深くす
ると、凸部21の占める幅が広くなり基本ユニツトの面積
が減少する。However, this convex portion 21 may also adversely affect. In order to suppress the avalanche multiplication phenomenon of the parasitic transistor,
Although the depth of 21 may be increased, in that case, the effect of moving the avalanche multiplication phenomenon occurrence portion away from the place where the parasitic transistor operation is likely to occur is small. Further, if the convex portion 21 is deepened, the width occupied by the convex portion 21 becomes wider and the area of the basic unit decreases.
BIPトランジスタの場合は、そもそもパワーMOSFETほ
どの高周波動作をさせないという楽な点があるが、エミ
ツタ・ベース間に逆バイアスを十分印加することによ
り、トランジスタに流れる還流時の電流を遮断してこの
モードの２次破壊から逃れることができる。しかしなが
ら、パワーMOSFETには、BIPトランジスタのように積極
的に還流時の電流を遮断する機能はない。このため、従
来の縦形パワーMOSFETには、汎用電力用素子としては重
大な欠陥があると言わざるを得ない。パワーMOSFETの電
圧定格は、通常静的なドレイン・ソース間の電圧ＶDSS
が使用されるが、寄生トランジスタを含むことにより上
記のような動作を行なうことから、トランジスタが静的
な電圧特性であるＶCEOでなく、動特性であるＶ
CEO(SUS)に相当するような動的な特性で規定されるべき
であり、その場合現在のパワーMOSFETの電圧定格よりも
大幅に低いものとなる。In the case of a BIP transistor, there is an easy point that it does not operate at a high frequency as much as a power MOSFET in the first place, but by applying a sufficient reverse bias between the emitter and base, the current flowing back into the transistor is cut off and this mode is set. You can escape from the secondary destruction of. However, the power MOSFET, unlike the BIP transistor, does not have the function of positively interrupting the current during the return. Therefore, it must be said that the conventional vertical power MOSFET has a serious defect as a general-purpose power element. The voltage rating of the power MOSFET is usually the static drain-source voltage V DSS.
However, since the above-mentioned operation is performed by including the parasitic transistor, the transistor is not the static voltage characteristic V CEO but the dynamic characteristic V CEO.
It should be specified with a dynamic characteristic equivalent to CEO (SUS) , in which case it will be significantly lower than the voltage rating of current power MOSFETs.
この発明は上記のような問題点を解消するためになさ
れたもので、２次破壊耐量を改善した電界効果型半導体
装置を得ることを目的とする。The present invention has been made to solve the above problems, and an object of the present invention is to obtain a field effect semiconductor device with improved secondary breakdown resistance.
この発明にかかる電界効果型半導体装置は、第１導電
形半導体基板と、前記基板表面に形成される第２導電形
半導体領域と、前記第２導電形半導体領域内のその表面
に中央部をあけて形成される第１導電形半導体領域と、
前記第２導電形半導体領域と前記第１導電形半導体領域
とを短絡したソース電極と、前記基板と前記第１導電形
半導体領域間の前記第２導電形半導体領域表面に形成さ
れる絶縁膜と前記絶縁膜表面に形成されるゲート電極と
を備えた縦方向に主電流の経路を有する電界効果型半導
体装置において、前記基板表面に前記第２導電形半導体
領域と隔てて形成される第２導電形ダイオード領域を備
え、前記第２導電形ダイオード領域は先端部が凹凸をな
し、その凸部の先端深さが前記第２導電形半導体領域の
深さと同等にしている。A field effect semiconductor device according to the present invention has a first conductivity type semiconductor substrate, a second conductivity type semiconductor region formed on the surface of the substrate, and a central portion formed in the surface of the second conductivity type semiconductor region. A first conductivity type semiconductor region formed by:
A source electrode short-circuiting the second conductivity type semiconductor region and the first conductivity type semiconductor region, and an insulating film formed on the surface of the second conductivity type semiconductor region between the substrate and the first conductivity type semiconductor region. In a field effect semiconductor device having a main current path in a vertical direction, comprising a gate electrode formed on a surface of the insulating film, a second conductivity type formed on the surface of the substrate so as to be separated from the second conductivity type semiconductor region. Type diode region, the tip of the second conductivity type diode region is uneven, and the depth of the tip of the protrusion is equal to the depth of the second conductivity type semiconductor region.
この発明においては、第２導電形ダイオード領域をFE
T領域と隔てて構成し、第２導電形ダイオード領域は先
端部が凹凸をなし、その凸部の先端深さがFET領域の第
２導電形半導体領域の深さと同等であるため、半導体素
子に高電圧が印加されたときFET領域よりダイオード領
域が電界強度が大きくなり、なだれ増倍現象はFET領域
から離れたダイオード領域で発生する。In the present invention, the second conductivity type diode region is made FE.
The second conductivity type diode region is separated from the T region, and the tip of the second conductivity type diode region is uneven, and the depth of the tip of the protrusion is equal to the depth of the second conductivity type semiconductor region of the FET region. When a high voltage is applied, the electric field strength in the diode region becomes larger than that in the FET region, and the avalanche multiplication phenomenon occurs in the diode region away from the FET region.
以下、この発明の実施例を図について説明する。な
お、以下の実施例の説明において、第２図〜第６図の説
明と重複する部分については適宜その説明を省略する。Embodiments of the present invention will be described below with reference to the drawings. In the following description of the embodiments, the description of the same parts as those in FIGS. 2 to 6 will be omitted as appropriate.
第１図は、この発明の一実施例であるパワーMOSFETの
断面図である。この装置の構成は以下の点を除いて第２
図の構成と同じである。第１導電形低濃度ドレイン領域
1a表面に、FET領域の第２導電形半導体領域２と隔て
て、ダイオード領域を形成している。ダイオート領域は
拡散深さの浅い第２導電形半導体領域22と深い第２導電
形半導体領域23から構成されている。深い第２導電形半
導体領域23は、FET領域の第２導電形半導体領域２と同
程度以上の深さである。FIG. 1 is a sectional view of a power MOSFET according to an embodiment of the present invention. The configuration of this device is the second except for the following points.
The configuration is the same as that shown in FIG. First conductivity type low concentration drain region
A diode region is formed on the surface 1a so as to be separated from the second conductivity type semiconductor region 2 in the FET region. The die-auto region is composed of a second conductivity type semiconductor region 22 having a shallow diffusion depth and a second conductivity type semiconductor region 23 having a deep diffusion depth. The deep second conductivity type semiconductor region 23 has a depth equal to or greater than that of the second conductivity type semiconductor region 2 in the FET region.
このような拡散深さの浅い第２導電形半導体領域22と
深い第２導電形半導体領域23から構成されるダイオード
領域をFET領域と隔てて形成することによつて、半導体
素子に高電圧が印加されたとき曲率半径の小さい第２導
電形半導体領域22,23からなるダイオード領域の電界強
度が大きくなり、なだれ増倍現象がFET領域から離れた
ダイオート領域で発生する。なだれ増倍現象の発生部が
FET領域にある寄生トランジスタから遠ざけることがで
き、縦形パワーMOSFETの２次破壊耐量を改善することが
できる。By forming the diode region composed of the second conductivity type semiconductor region 22 having a shallow diffusion depth and the second conductivity type semiconductor region 23 having a deep diffusion distance from the FET region, a high voltage is applied to the semiconductor element. Then, the electric field strength of the diode region composed of the second conductivity type semiconductor regions 22 and 23 having a small radius of curvature becomes large, and the avalanche multiplication phenomenon occurs in the die auto region apart from the FET region. The avalanche multiplication phenomenon occurs
It can be kept away from the parasitic transistor in the FET region, and the secondary breakdown resistance of the vertical power MOSFET can be improved.
この発明の他の実施例として、前記実施例のダイオー
ト領域の第２導電形半導体領域23の不純物濃度FET領域
の第２導電形半導体領域２の不純物濃度より高くすると
さらに電界強度は大きくなり、より大きな効果が得られ
る。As another embodiment of the present invention, if the impurity concentration of the second conductivity type semiconductor region 23 of the die auto region of the above embodiment is higher than the impurity concentration of the second conductivity type semiconductor region 2 of the FET region, the electric field strength further increases. Great effect can be obtained.
尚、上記実施例ではパワーMOSFETについての説明を専
ら行つてきたが、パワーMOSFETの低抵抗領域である第１
導電形高濃度ドレイン領域1bにあたる部分の導電性を反
対にした構造を有する絶縁ゲート・トランジスタと言わ
れている素子にも、この発明の効果がある。Although the power MOSFET has been mainly described in the above embodiments, the first embodiment, which is the low resistance region of the power MOSFET, has been described.
An element called an insulated gate transistor having a structure in which the conductivity type high-concentration drain region 1b has the opposite conductivity has the effect of the present invention.
以上のように、この発明によれば縦方向に主電流の経
路を有する電界効果型半導体装置において、第１導電形
半導体基板表面にFET領域の第２導電形半導体領域２と
隔てて第２の導電形ダイオート領域22,23を形成し、そ
の第２導電形ダイオード領域22,23は先端部が凹凸をな
し、その凸部23の先端深さを第２導電形半導体領域２の
深さと同等にしたため、２次破壊耐量を改善した電界効
果型半導体装置を得ることができる。As described above, according to the present invention, in the field effect semiconductor device having the main current path in the vertical direction, the second conductivity type semiconductor region 2 of the FET region is separated from the second conductivity type semiconductor region 2 on the surface of the first conductivity type semiconductor substrate. Conductive type die-auto regions 22 and 23 are formed, and the tips of the second conductive type diode regions 22 and 23 are uneven, and the tip depth of the convex portion 23 is made equal to the depth of the second conductive type semiconductor region 2. Therefore, it is possible to obtain a field effect semiconductor device with improved secondary breakdown resistance.
第１図は、この発明の一実施例であるパワーMOSFETの断
面図である。第２図は従来のパワーMOSFETの断面図であ
る。第３図は、従来のパワーMOSFETの出力特性を示す図
である。第4A図は、MOSFET領域の第２導電形半導体領域
に凸部がない場合のパワーMOSFETの基本構成単位の断面
図であり、第4B図は、第4A図の等価回路を示す図であ
る。第５図は、パワーMOSFETを使つたインバータ回路図
である。第６図は、第５図における還流ダイオードの電
圧Vd波形とパワーMOSFETに流れる電流Im波形を示す図で
ある。 図において、1aは第１導電形低濃度ドレイン領域、1bは
第１導電形高濃度ドレイン領域、2,22,23は第２導電形
半導体領域、３は第１導電形ソース領域、４は絶縁膜、
５はゲート電極、６はソース電極、７はチヤネル形成領
域、８はドレイン電極、21は凸部である。 尚、各図中同一符号は同一または相当部分を示す。FIG. 1 is a sectional view of a power MOSFET according to an embodiment of the present invention. FIG. 2 is a sectional view of a conventional power MOSFET. FIG. 3 is a diagram showing output characteristics of a conventional power MOSFET. FIG. 4A is a sectional view of a basic structural unit of the power MOSFET in the case where there is no convex portion in the second conductivity type semiconductor region of the MOSFET region, and FIG. 4B is a diagram showing an equivalent circuit of FIG. 4A. FIG. 5 is an inverter circuit diagram using a power MOSFET. FIG. 6 is a diagram showing the voltage Vd waveform of the free wheeling diode and the current Im waveform flowing through the power MOSFET in FIG. In the figure, 1a is a first-conductivity-type low-concentration drain region, 1b is a first-conductivity-type high-concentration drain region, 2,22,23 are second-conductivity-type semiconductor regions, 3 is a first-conductivity-type source region, and 4 is an insulating region. film,
Reference numeral 5 is a gate electrode, 6 is a source electrode, 7 is a channel forming region, 8 is a drain electrode, and 21 is a convex portion. In the drawings, the same reference numerals indicate the same or corresponding parts.
Claims (2)
形成される第２導電形半導体領域と、前記第２導電形半
導体領域内のその表面に中央部をあけて形成される第１
導電形半導体領域と、前記第２導電形半導体領域と前記
第１導電形半導体領域とを短絡したソース電極と、前記
基板と前記第１導電形半導体領域間の前記第２導電形半
導体領域表面に形成される絶縁膜と前記絶縁膜表面に形
成されるゲート電極とを備えた縦方向に主電流の経路を
有する電界効果型半導体装置において、前記基板表面に
前記第２導電形半導体領域と隔てて形成される第２導電
形ダイオード領域を備え、 前記第２導電形ダイオード領域は先端部が凹凸をなし、
その凸部の先端深さが前記第２導電形半導体領域の深さ
と同等であることを特徴とする電界効果型半導体装置。1. A first-conductivity-type semiconductor substrate, a second-conductivity-type semiconductor region formed on the surface of the substrate, and a first-concentration first-region formed in the surface of the second-conductivity-type semiconductor region.
A conductive type semiconductor region, a source electrode short-circuiting the second conductive type semiconductor region and the first conductive type semiconductor region, and a surface of the second conductive type semiconductor region between the substrate and the first conductive type semiconductor region. In a field effect semiconductor device having an insulating film to be formed and a gate electrode formed on the surface of the insulating film and having a main current path in the vertical direction, the field effect type semiconductor device is provided on the surface of the substrate with the second conductivity type semiconductor region separated. A second conductivity type diode region is formed, and the tip of the second conductivity type diode region is uneven.
The field effect semiconductor device is characterized in that the tip depth of the protrusion is equal to the depth of the second conductivity type semiconductor region.
度が電界効果によって機能する領域の前記第２導電形半
導体領域の不純物濃度よりも高い特許請求の範囲第１項
記載の電界効果型半導体装置。2. The field effect semiconductor device according to claim 1, wherein the impurity concentration of the second conductivity type diode region is higher than the impurity concentration of the second conductivity type semiconductor region in a region functioning by a field effect. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60262769A JP2527160B2 (en) | 1985-11-22 | 1985-11-22 | Field effect type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60262769A JP2527160B2 (en) | 1985-11-22 | 1985-11-22 | Field effect type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62123771A JPS62123771A (en) | 1987-06-05 |
| JP2527160B2 true JP2527160B2 (en) | 1996-08-21 |
Family
ID=17380331
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60262769A Expired - Lifetime JP2527160B2 (en) | 1985-11-22 | 1985-11-22 | Field effect type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2527160B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2692350B2 (en) * | 1990-04-02 | 1997-12-17 | 富士電機株式会社 | MOS type semiconductor device |
| JP4967487B2 (en) * | 2006-07-10 | 2012-07-04 | 株式会社デンソー | Insulated gate bipolar transistor |
| JP4492735B2 (en) | 2007-06-20 | 2010-06-30 | 株式会社デンソー | Semiconductor device and manufacturing method of semiconductor device |
| JP6092680B2 (en) * | 2013-03-26 | 2017-03-08 | 新電元工業株式会社 | Semiconductor device and manufacturing method of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL7907680A (en) * | 1979-10-18 | 1981-04-22 | Philips Nv | ZENERDIODE. |
| JPS57206073A (en) * | 1981-06-12 | 1982-12-17 | Hitachi Ltd | Mis semiconductor device |
-
1985
- 1985-11-22 JP JP60262769A patent/JP2527160B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62123771A (en) | 1987-06-05 |
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