KR950004600A - Polycrystalline silicon thin film transistor - Google Patents

Polycrystalline silicon thin film transistor Download PDF

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Publication number
KR950004600A
KR950004600A KR1019930014706A KR930014706A KR950004600A KR 950004600 A KR950004600 A KR 950004600A KR 1019930014706 A KR1019930014706 A KR 1019930014706A KR 930014706 A KR930014706 A KR 930014706A KR 950004600 A KR950004600 A KR 950004600A
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KR
South Korea
Prior art keywords
polycrystalline silicon
thin film
film transistor
silicon thin
channel
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KR1019930014706A
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Korean (ko)
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KR100297706B1 (en
Inventor
장낙원
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김광호
삼성전자 주식회사
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Priority to KR1019930014706A priority Critical patent/KR100297706B1/en
Publication of KR950004600A publication Critical patent/KR950004600A/en
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Publication of KR100297706B1 publication Critical patent/KR100297706B1/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Abstract

본 발명은 다결정 실리콘 박막 트랜지스터에 관한 것으로, 특히 오프-셋 구조의 다결정 실리콘 박막 트랜지스터에 관해 기술한다.The present invention relates to a polycrystalline silicon thin film transistor, and more particularly, to a polycrystalline silicon thin film transistor of an off-set structure.

본 발명 박막 트랜지스터는 석영기판과, 상기 기판에 형성되며 상기 다결정 실리콘의 채널의 양측에 불순물이 도핑된 소오스와 게이트이 마련된 활성층과, 상기 활성층과 전기적인 절연을 유지하며 상기 채널의 상부에 위치되는 게이트를 갖추며, 상기 드레인에 인접된 상기 채널의 상방에 다결정 실리콘 마스크층이 마련되어 있는 구조적 특징을 갖는다. 이로써 오프-커런트의 감소가 이루어 지고 결과적으로 LCD의 콘트라스트 비와 휘도를 향상시킨다.The thin film transistor of the present invention includes a quartz substrate, an active layer formed on the substrate and having an impurity doped source and a gate on both sides of a channel of the polycrystalline silicon, and a gate positioned on an upper portion of the channel while maintaining electrical insulation with the active layer. And a polycrystalline silicon mask layer provided above the channel adjacent to the drain. This reduces off-current and consequently improves the contrast ratio and brightness of the LCD.

Description

다결정 실리콘 박막 트랜지스터Polycrystalline silicon thin film transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 종래 다결정 실리콘 박막 트랜지스터의 개략적 단면도. 제 2 도는 제 1 도에 도시된 종래 다결정 실리콘 박막 트랜지스터의 개략의 배치도. 제 3 도는 본 발명에 따른 다결정 실리콘 박막 트랜지스터의 개략적 단면도. 제 4 도는 제 2 도에 도시된 본 발명 다결정 실리콘 박막 트랜지스터의 개략적 평면 배치도.1 is a schematic cross-sectional view of a conventional polycrystalline silicon thin film transistor. 2 is a schematic layout view of a conventional polycrystalline silicon thin film transistor shown in FIG. 3 is a schematic cross-sectional view of a polycrystalline silicon thin film transistor according to the present invention. 4 is a schematic plan layout of the present invention polycrystalline silicon thin film transistor shown in FIG.

Claims (5)

유리기판과, 상기 기판에 형성되며 상기 다결정 실리콘의 채널의 양측에 불순물이 도핑된 소오스와 게이트가 마련된 활성층과, 상기 활성층과 전기적인 절연을 유지하며 상기 채널의 상부에 위치되는 게이트를 갖춘 다결정 실리콘 박막 트랜지스터에 있어서, 상기 드레인에 인접된 상기 채널의 상방에 다결정 실리콘 마스크층이 마련된 것을 특징으로 하는 다결정 실리콘 박막 트랜지스터.A polycrystalline silicon having a glass substrate, an active layer formed on the substrate and having an impurity doped source and a gate on both sides of the channel of the polycrystalline silicon, and a gate positioned on top of the channel to maintain electrical insulation with the active layer. A thin film transistor, wherein a polycrystalline silicon mask layer is provided above the channel adjacent to the drain. 제 1 항에 있어서, 상기 게이트와 상기 마스크층간의 간격이 0.3 내지 0.7㎛의 범위인 것을 특징으로 하는 다결정 실리콘 박막 트랜지스터.The polycrystalline silicon thin film transistor according to claim 1, wherein an interval between the gate and the mask layer is in a range of 0.3 to 0.7 mu m. 제 1 항 또는 제 2 항에 있어서, 상기 게이트와 상기 마스크층을 동일 평면상에 위치하는 것을 특징으로 하는 다결정 실리콘 박막 트랜지스터.The polycrystalline silicon thin film transistor according to claim 1 or 2, wherein the gate and the mask layer are located on the same plane. 제 3 항에 있어서, 상기 디스크층의 폭이 0.3 내지 0.7㎛의 범위인 것을 특징으로 하는 다결정 실리콘 박막 트랜지스터.4. The polycrystalline silicon thin film transistor according to claim 3, wherein the disk layer has a width in the range of 0.3 to 0.7 mu m. 제 1 항 또는 제 2 항에 있어서, 상기 디스크층의 폭이 0.3 내지 0.7㎛의 범위인 것을 특징으로 하는 다결정 실리콘 박막 트랜지스터.The polycrystalline silicon thin film transistor according to claim 1 or 2, wherein the disk layer has a width of 0.3 to 0.7 mu m. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930014706A 1993-07-30 1993-07-30 Polycrystalline thin film transistor KR100297706B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930014706A KR100297706B1 (en) 1993-07-30 1993-07-30 Polycrystalline thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930014706A KR100297706B1 (en) 1993-07-30 1993-07-30 Polycrystalline thin film transistor

Publications (2)

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KR950004600A true KR950004600A (en) 1995-02-18
KR100297706B1 KR100297706B1 (en) 2001-10-24

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8018545B2 (en) 2004-08-26 2011-09-13 Lg Display Co., Ltd. Method of fabricating a liquid crystal display device
US8049830B2 (en) 2004-09-09 2011-11-01 Lg Display Co., Ltd. Liquid crystal display device and fabrication method thereof

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101043992B1 (en) 2004-08-12 2011-06-24 엘지디스플레이 주식회사 Liquid crystal display device and method of fabricating thereof
KR101037322B1 (en) 2004-08-13 2011-05-27 엘지디스플레이 주식회사 Liquid crystal display device and method of fabricating thereof
KR101078360B1 (en) 2004-11-12 2011-10-31 엘지디스플레이 주식회사 Liquid Crystal Display Panel of Poly-type and Method of Fabricating The Same
KR101066489B1 (en) 2004-11-12 2011-09-21 엘지디스플레이 주식회사 Thin Film Transistor Substrate of Poly-type and Method of Fabricating The Same
KR101192746B1 (en) 2004-11-12 2012-10-18 엘지디스플레이 주식회사 Method of Fabricating Thin Film Transistor Substrate of Poly-type
KR101153297B1 (en) 2004-12-22 2012-06-07 엘지디스플레이 주식회사 Liquid crystal display device and method of fabricating the same
KR101086487B1 (en) 2004-12-24 2011-11-25 엘지디스플레이 주식회사 Poly Thin Film Transistor Substrate and Method of Fabricating The Same
KR101107252B1 (en) 2004-12-31 2012-01-19 엘지디스플레이 주식회사 Thin film transistor substrate in electro-luminescence dispaly panel and method of fabricating the same
KR101107251B1 (en) 2004-12-31 2012-01-19 엘지디스플레이 주식회사 Poly Thin Film Transistor Substrate and Method of Fabricating The Same
KR101125252B1 (en) 2004-12-31 2012-03-21 엘지디스플레이 주식회사 Poly Liquid Crystal Dispaly Panel and Method of Fabricating The Same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8018545B2 (en) 2004-08-26 2011-09-13 Lg Display Co., Ltd. Method of fabricating a liquid crystal display device
US8049830B2 (en) 2004-09-09 2011-11-01 Lg Display Co., Ltd. Liquid crystal display device and fabrication method thereof

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