JPH02183565A - Semiconductor device - Google Patents

Abstract

PURPOSE:To form gate electrodes in a unified body without deteriorating gate characteristics by using a complementary type MIS structure constituted of a barrier layer to prevent impurity diffusion, and high melting point metal or its silicide. CONSTITUTION:Gate electrodes 7a, 7b of an MIS.FET are constituted of the following; polysilicon 8a, 8b doped with impurity, a barrier layer 9 to prevent said impurity from diffusing, and high melting point metal or its silicide 10. Diffusion of impurity into the silicide 10 is surely prevented. Hence, a gate electrode 7b of an N-channel MIS.FET whose gate electrode is constituted of the polysilicon 8b doped with N-type impurity, and a gate electrode 7a of a P-channel MIS.FET whose gate electrode is constituted of the polysilicon 8a doped with P-type impurity can be formed integrally. Thereby, the gate electrodes can be formed integrally without deteriorating gate characteristics.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, for example, a complementary MIS
(complementary MTS, hereafter C
Static RAM with a memory cell structure loaded with high-resistance polysilicon
(Stanic Random Access Mem
The present invention relates to a technology that is effective when applied to SRAM (hereinafter referred to as SRAM).

[Conventional technology]

C in which an integrated circuit consisting of an n-channel MIS-FET and a p-channel MIS-FET is formed on the same semiconductor substrate.
Since MIS devices have the advantage of not consuming direct current other than transient current, their importance in MrS devices has increased in recent years.

Conventionally, the gate electrode material of the above CMIS has n
Channel MIS-FET Sp channel MIS-FET both use n-type polysilicon doped with n-type impurities such as phosphorus (P). Furthermore, in recent years, a so-called polycide gate structure in which a high melting point metal oxide is laminated on the n-type polysilicon has been adopted for the purpose of improving wiring delays due to the resistance of polysilicon.

n-channel MIS-FET and p-channel MIs-F
In the above-mentioned CMIS device in which both the ET gate electrodes are formed of n-type polysilicon, the n-channel MIS-
The FET side adopts a surface channel type MIS structure in which a p-type channel doped layer is formed on the substrate surface, and the p-channel MIS-FET side has its threshold voltage matched to that of the n-channel MIS. Therefore, a buried channel type MfS structure in which a p-type channel doped layer is formed in an n-well region on the substrate surface is employed.

Regarding the above CMIS device structure, for example, "Nikkei Electronics 19, published by Nikkei McGraw-Hill.
86.3.10 (!Jo, 390)J P199~
There is a description on page 217.

However, in the buried channel type MrS structure, compared to the surface channel type MIS structure, the depletion layer tends to extend near the substrate surface, so the short channel effect becomes noticeable, which is disadvantageous for device miniaturization. Therefore, in recent years, n
By forming the gate electrode on the channel MIS-FET side with n-type polysilicon and the gate electrode on the p-channel MTS-FET side with p-type polysilicon, the n-channel MIS-FETll! :p channel/l/M
A CMIS device has been proposed in which both the IS and FET have a surface channel type MIS structure.

[Problem to be solved by the invention]

However, n-channel M f S−F E Tff
l! In the CMIS device described above, the gate electrode of the n-channel MIS-FET is formed of n-type polysilicon, and the gate electrode of the p-channel MIS-FET is formed of p-type polysilicon.
Gate electrode of IS-FET and p-channel MIS-FET
Since the gate electrode and the gate electrode are continuously formed in the same layer and p-type and n-type impurities are introduced using a mask, a pn junction is formed at the connection part, and as a result, the voltage applied to the gate electrode There is a problem in that the gate characteristics decrease and the desired gate characteristics cannot be obtained.

In addition, CMIS has a polycide gate structure in which n-type polysilicon is laminated on each of n-type and p-type polysilicon.
Similar problems exist in devices. In other words, since the silicide film has a high impurity diffusion rate, when silicide is laminated on polysilicon doped with impurities and heat-treated, the impurities in the n-type polysilicon and the p-type There is a problem in that impurities in polysilicon interdifuse with each other through the silicide layer.

As a countermeasure, a method can be considered to form the gate electrode of the n-channel MIS-FET and the gate electrode of the p-channel MIS-FET independently, and connect the gate electrodes through a metal wiring such as aluminum. The method is
To complicate the gate formation process, highly integrated CM r
It is not suitable for S devices.

On the other hand, even in an SRAM having a memory cell structure loaded with p-channel type high-resistance polysilicon, there is a demand for interconnecting n-type polysilicon and p-type polysilicon. In other words, a pair of resistors and a pair of driving MIS-FETs.
In order to keep the standby current low and improve the soft error resistance in an SRAM memory cell that constitutes a flip-flop circuit, for example, drive! JIM
It is effective to form the IS-FET with an n-channel MIS-FET and to form the resistance element with a p-channel type high-resistance polyconductor.

However, if you do this, the resistance element and drive MIS-
When connecting the gate electrode of the FET, a pn junction is formed at the connection portion, resulting in a problem similar to that of the CMIS device.

The present invention has been made with attention to the above-mentioned problems, and its purpose is to form the gate electrode on the n-channel MIS-FET side with n-type polysilicon, and to
Gate 1 on the FET side is made of p-type polysilicon
An object of the present invention is to provide a technique that can integrally form gate electrodes in MIS devices without deteriorating gate characteristics.

Another object of the present invention is to improve memory cell characteristics in a memory cell having a flip-flop circuit configuration in which the gate electrode of the driving M5-FET and the resistance element are formed of polysilicon doped with impurities of different conductivity types. It is an object of the present invention to provide a technique that allows a gate electrode of a driving MIS-FET to be directly connected to a resistance element without reducing the resistance.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief description of typical aspects of the invention disclosed in this application is as follows.

That is, in the present invention, the gate electrode of MIS-FET is
It is composed of polysilicon doped with impurities, a barrier layer for preventing diffusion of the impurities, and a high melting point metal or its oxide.

[Effect]

According to the above means, the barrier layer reliably prevents impurities in polysilicon from diffusing into the high melting point metal or its silicide. As a result, an n-channel MIS-FE with a gate electrode made of polysilicon doped with n-type impurities was created.
It becomes possible to integrally form the gate electrode of T and the gate electrode of p-channel MIS-FET whose gate electrode is polysilicon doped with p-type impurities. Also, drive M
In a memory cell with a flip-flop circuit configuration in which the gate electrode of the Is-FET and the resistance element are formed of polysilicon doped with impurities of different conductivity types, the gate electrode of the driving MIS/FET and the resistance element are directly connected. It becomes possible to connect.

[Example 1] FIG. 1 is a sectional view taken along the line I-1 in FIG. 2 showing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a schematic plan view of this semiconductor device, and FIG. , is an equivalent circuit diagram of this semiconductor device. Note that in FIG. 2, insulating films other than the field insulating film are not shown in order to make the configuration of the first embodiment easier to understand.

The CMIS inverter, which is the semiconductor device of the first embodiment, has an n-channel MIS-FETQ and a p-channel MIS-FETQ connected in series, as shown in FIG.
It consists of FETQ, and.

As shown in FIGS. 1 and 2, an n-well region 2 and an n-well region 3 are formed on the main surface of a semiconductor substrate 1 made of p-type silicon single crystal.

The n-well region 2 is formed by implanting boron (B) ions into the n-channel MIs-FET formation region, and the n-well region 3 is formed by implanting phosphorus (P) into the p-channel MTS-FET formation region.
) or arsenic (As) is ion-implanted.

A field insulating film 4 and a gate insulating film 5 made of, for example, 5IO2 are formed on the surface of the semiconductor substrate l, and a p-type channel stopper region 6 into which boron ions are implanted is formed under the field insulating film 4. There is.

A gate electrode 7a of the n-channel MIS-FETQ is formed on the gate insulating film 5 in the n-channel MIS-FET formation region, and a gate electrode 7a of the n-channel MIS-FETQ is formed on the gate insulating film 5 in the p-channel MIS-FET formation region. , p-channel MIS-FE
A gate electrode 7b of TQ2 is formed.

The gate electrode 7a of the n-channel MIS-FETQ+ is made of polysilicon 3a, titanium nitride (TiN) 9, WSi2 (or MO3i, . . .
TaSi2. It is formed by stacking silicides 10 such as Ti5i2), and the bottom layer polysilicon 8a is doped with an n-type impurity such as phosphorus or arsenic.

The gate electrode 7b of pf+ channel MrS-FETQ2 is n
Gate electrode 7a of channel MI S-FETQ
Similarly, polysilicon 8b is formed sequentially from the bottom layer.

It is formed by laminating titanium nitride 9 and silicide 10, and the polysilicon 8b at the bottom 19 is doped with a p-type impurity (boron).

In the first embodiment, the film thickness of titanium nitride 9 is made thinner than the film thickness of polysilicon 3a, 3b and silicide 10 in order to lower the resistance value of gate electrodes 7a, 7b.

On the surface of the n-well region 2, there is an n-channel MIS/FET.
A lightly doped n-type semiconductor region 11a and a highly doped n-type semiconductor region 12a are formed to serve as the source and drain of Q, and form a so-called LDD (Jightly Dope).
d drain) structure. The n-type semiconductor region 11a is formed by ion-implanting, for example, phosphorus into the surface of the n-well region 2 using the gate electrode 7a as a mask. The n°-type semiconductor region 12a is formed by ion-implanting, for example, arsenic into the surface of the n-well region 2 using, as a mask, a spacer 13 made of, for example, Sin, formed on the gate electrode 7a and its sidewall. .

On the surface of the n-well region 3, there is a p-channel MIS/FET.
A lightly doped p-type semiconductor region 11b and a highly doped square semiconductor region 12b, which serve as a Ch source and drain, are formed to have the same <LDD structure. The p-type semiconductor region 11b is formed by implanting boron ions into the surface of the n-well region 3 using the gate electrode 7b as a mask.
The p-type semiconductor region 12b is formed by ion-implanting arsenic into the surface of the n-well region 3 using the gate electrode 7b and the spacer 13 formed on its sidewall as a mask.

The upper layer of MfS-FETQ, ,Q2 includes a semiconductor substrate l.
An interlayer insulating film 14 is formed to cover the surface. The interlayer insulating film 14 is made of, for example, BPSG (boro ph
ospho 5ilicate glass) membrane
It is formed by applying the VD method.

In the upper layer of the interlayer insulating film 14, wirings 15a, 151) and 15c made of, for example, an aluminum alloy are formed. One end of the wiring 15a is connected to one n'-type semiconductor region 12a of the n-channel MIS-FETQ through a contact hole 16, and the other end is connected to a reference potential of, for example, OV (V
ss). One end of the wiring 15b is connected to a p-channel MIS/FET through a contact hole 16.
Q, and the other end thereof is connected to a power supply potential (VOO) of, for example, 5V.

n channel MTS-F ETQ, the other n
type semiconductor region 12a and p-channel MIS-FET
The other p type semiconductor region 12b of Q2 is connected to each other via a wiring 15c connected to the output (VOLI?).

As shown in FIG. 2, an n-channel MIS-FETQ,
gate electrode 7a and p-channel MIS・FETQ2
is formed integrally with the gate electrode 7b, and is manually operated (vI,
I). Then, the connection part shown in Fig. 2 (
C), the gate electrode 7a side has a three-rfJ structure of polysilicon 8a1 doped with n-type impurities, titanium nitride 9, and silicide 10, and the gate electrode 7b side has a polysilicon doped with p-type impurities. 3b, titanium nitride 9, and silicide 10.

At this time, at the connection part (C), the n-type polysilicon 8a and the p-type polysilicon 8b are in direct contact, but the titanium nitride 9 formed between the polysilicon 3a, 3b and the silicide 10 is an impurity. Since it acts as a diffusion barrier layer, impurities in polysilicon 3a and 3b do not interdiffuse through silicide 10.

The CMIS inverter of the first embodiment configured as described above has 21 inputs! When the voltage level is p-channel M
I S-F E "T' (h conductive, n channel M
Since l5-FETQ, becomes non-conductive, p-channel M
It operates so that the power supply voltage level is output via IS•FETQ2. Also, when human power is at the power supply voltage level, n
Channel MIS-FETQ, is conductive, p-channel MI
Since S-FETQ2 becomes non-conductive, n-channel MI
It operates so that the reference voltage level is output via S-FETQ.

As described above, according to the first embodiment, the following effects can be obtained.

(1), n + 2 M I S-F E T
The gate electrode 7a of Q + is made of polysilicon 8a doped with n-type impurities, titanium nitride 9, and silicide 10, and the gate electrode 7b of p-channel MIS-FETQ2 is made of polysilicon 8a doped with p-type impurities.
b, composed of 9 titanium nitride and 10 silicide,
Since the impurities in the polysilicon 3a, 3b are prevented from mutually diffusing through the silicide 10 at the connection part (C) of the gate electrodes 7a, 7b, the gate electrodes 7a, 7b
Even if they are integrally formed, there is no risk of deterioration of gate characteristics.

(2), Juki (1) +,: Yori, 'r' -)
1i poles 7a and 7b are formed independently, and gate electrodes are connected via metal wiring such as aluminum. a, 7
Since there is no need for a process for connecting between the gates b, the gate formation process is simplified.

(3), n-channel MI S-F ETQ, and p
Since both channels M r S-F ET Q2 have a surface channel type MIS structure, miniaturization of integrated circuits can be promoted and power consumption can be reduced.

[Embodiment 2] FIG. 4 is a sectional view taken along the line rV-rV in FIG. 5 showing a memory cell of a semiconductor device according to another embodiment of the present invention.
The plan view of this memory cell, FIG. 6, is an equivalent circuit diagram of this memory cell. Note that in FIG. 5, insulating films other than the field insulating film are not shown in order to make the configuration of the second embodiment easier to understand.

As shown in FIG. 6, the memory cell of the CMIS-3RAM, which is the semiconductor device of the second embodiment, includes a flip-flop circuit, a pair of input/output terminals thereof, a complementary data line DL,
Selected M I S -FET Qt connected between end τ
,, Qt2, the flip-flop circuit is composed of resistor elements R,,R, and drive MIS-FETQd, ,
It is composed of Qd.

A word line WL is connected to the selected MI S-FETQt, . . . Qt. The data line DL is connected to the drain of the selected MIS-FETQt, and the selected MIS-
Data lines 1ff are connected to the drains of FETQt2, respectively.

As shown in FIGS. 4 and 5, the memory cell has p-
It is formed on the main surface of a semiconductor substrate l made of silicon single crystal. A field insulating film 4 and a gate insulating film 5 made of, for example, 5102 are formed on the surface of the semiconductor substrate l, and a p-type channel stopper region 6 into which boron ions are implanted is formed below the field insulating film 4. There is.

The drive MIS-FETs Qd, Qd, have a gate insulating film 5, a gate electrode 17a, an n'-type semiconductor region 18, 19 that becomes a drain, and an n'-type semiconductor region 1 that becomes a source.
It consists of 8. The gate electrode 17a is formed by laminating polysilicon 3a, titanium nitride 9, and silicide 1o in order from the bottom layer, and the polysilicon 8a includes:
It is doped with n-type impurities such as phosphorus or arsenic.

The selected MIS-FETQt, Qt, includes a gate insulating film 5, a gate electrode 17b formed integrally with the word line WL, and an n-type semiconductor region 18.19 that becomes a source when reading information. , and an n-type semiconductor region 18 which becomes a drain. The gate electrode 17b is
Like the gate electrode 17a, it is formed by stacking polynolylic silicon 8a doped with n-type impurities, titanium nitride 9, and silicide 1o. In the second embodiment, in order to reduce the resistance value of the gate electrodes 17a and 17b, the film thickness of the titanium nitride 9 is made thinner than the film thickness of the polysilicon 8a and the silicide 1a.

The n° type semiconductor region 18.19 which becomes the source of the selected MIS-FETQt2 at the time of reading is the source of the selected MIS-FETQt2.
It is formed integrally with the drain of d. One end of the gate electrode I7a of the drive MIS-FET Qd is connected to the surface of the n-type semiconductor device 19, which is a part of the drain, through a contact hole 20.

One end of the gate electrode 17a of the drive MIS-FETQd is n, which is a part of the drain of the drive MIS-FeTQd.
It is connected to the surface of the + type semiconductor region 19 via a contact hole 20, and the other end is connected to the selected MIS- at the time of reading.
n-type semiconductor region 1 which becomes part of the source of FETQt.
9 through a contact hole 20.

In this way, the gate electrode 1 of the drive Mr, -FETQd,
One end of 7a is the drive MIS-FET Qd2 (II) drain and selected MIS-FET at the time of reading.
n-type semiconductor region 19 which is part of the source of TQt2
and drive MIS-FET Q
One end of the gate electrode 17a of d2 is connected to the drive MIS・F E
The n″-type semiconductor region 419, which is a part of the drain of T
The cross-connection of the flip-flop circuit is achieved by connecting to the n-type semiconductor region 19 which becomes a part of the source of S-FETQt+.

An insulating film 21 is formed above the gate electrodes 17a, 17b (7-domain line WL) so as to cover the surface of the memory cell. The insulating film 21 is, for example, a 5in2 film formed by CVD.
It is formed by applying the D method.

Resistance elements R, , R2 are formed in the upper layer of the insulating film 21 . These resistance elements R, , R2 made of the second layer of polysilicon are connected to the driving M I S FET Qd,
A conductive layer 22 made of a second layer of polysilicon doped with a p-type impurity (boron) is integrally formed on both sides of the insulating film 21 in a layout overlapping with the gate electrode 17a. There is.

One end of the resistance element R is connected to a power supply potential (vn.) of, for example, 5V via this conductive layer 22, and the other end is
The conductive layer 22 and the through hole 23 are driven by Mr.
S-FETQd217) Gate electrode 17aO) Connected to the end. That is, the resistance element R3 is connected to the n-type semiconductor region 19, which is substantially a part of the drain of the drive MIS-FET Qd.

In this way, the resistance element R1 is driven by the driving Mfs-FETQd
By arranging the insulating film 21 to overlap with the gate electrode 17a of the resistor R1, the insulating film 21 is a gate insulating film, the p-type impurity-doped conductive layer 22 is a source and drain, the resistor R1 is a channel region, and the resistor R1 is a channel region. A p-channel MIS-FET is configured using the lower gate electrode 17a as a gate electrode. That is, resistance element R1 becomes equivalent to a p-channel MI S-FET.

The resistance element R1 consisting of the p-channel MIS-FET is connected in series with the driving Mr and -FETQd, and operates so as to be turned off when the gate electrode 17a below the resistance element R1 is at the power supply voltage level. It operates so that it is turned on when 17a is at the reference voltage level.

On the other hand, the resistive element R2, like the resistive element R2, is arranged on the insulating film 21 in a layout that overlaps with the gate electrode 17a of the driving MIS-FET Qd2, and on both sides thereof, a second layer doped with p-type impurities is disposed. A conductive layer 22 made of polysilicon is integrally formed. Resistance element R
One end of 2 is connected to a power supply potential via a conductive layer 22,
The other end is connected to the end of the gate electrode 17a of the drive MIS/FET Qd via the conductive layer 22 and the through hole 23. That is, the resistance element R2 is substantially a part of the drain of the drive MIS-FET Qd2.
”-shaped semiconductor region 19.

In this way, the resistance element R2 is connected to the driving MIS-FET
By arranging the insulating film 21 to overlap with the gate electrode 17a of Qd2, the insulating film 21 is a gate insulating film, the p-type impurity-doped conductive layer 22 is a source and drain, the resistor R2 is a channel region, and the resistor R2 is p-channel MrS-FE with lower gate electrode 17a as the gate electrode
T is configured. That is, resistance element R2 becomes equivalent to a p-channel MI S-FET.

The resistance element R2 made of the p-channel MIS-FET is connected in series with the driving MIS-FETQd2,
The drive M I S - operates so as to be turned OFF when the FET Qd2 is in a conductive state.

As described above, since each of the resistive elements R, R2 is equivalent to a p-channel MIS-FET, the flip-flop circuit of the memory cell consists of two series circuits consisting of an n-channel MIS-FET and a p-channel MIS-FET. (CM
It is equivalent to cross-connecting ISFET).

An insulating film 24 is formed above the resistance elements R1 and R2 so as to cover the surface of the memory cell.

The insulating film 24 is formed by depositing, for example, a BPSG film using the CVD method.

Data lines DL and TfT made of, for example, an aluminum alloy are formed in the upper layer of the edge film 24.

The data line DL is connected to the selected M through the contact hole 25.
IS-FETQt, connected to the drain of the data line D
L is selected through the contact hole 25.
- connected to the drain of FETQt.

According to the second embodiment consisting of the above IT, the following effects can be obtained.

(1), Drive MIS-FETQd, Qd2
The gate electrode 17a is made of polysilicon 8as doped with n-type impurities, titanium nitride 9, and silicide 10, and the resistance elements R, R2, right side, source, and drain that constitute the channel region of the p-channel MIS/FET are Since the constituting conductive layer 22 is made of polysilicon doped with p-type impurities, one end of the resistor R3 is directly connected to the gate electrode 17a of the driving MrS-FET Qd2 for the same reason as in Example 1, and the resistor It becomes possible to directly connect one end of the element R2 to the gate electrode 17a of the drive MIS/FET Qd.

(2) According to (1) above, the drive MIS-FETQd,
, Qd, and the resistance element R=R2 consisting of a p-channel MrS FET, there is no need to interpose metal wiring such as aluminum, so the degree of freedom in routing the gate electrode 17a and the conductive layer 22 is improved. Moreover, the process for forming the memory cell is simplified.

(3) According to the above [1], since the flip-flop circuit of the memory cell is constituted by CMIS-FET, the standby current of the flip-flop circuit can be reduced.

Furthermore, even if the drain voltage of the drive MIS/FET in the OFF state is reduced by α rays, the current from the parasitic p-channel MIS/FET increases, so that the flip-flop circuit is prevented from being inverted.

As above, the invention made by the present inventor has been specifically explained based on Examples, but it should be noted that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Not even.

For example, in Example 1.2, the gate electrode was made of polysilicon, titanium nitride, and silicide.
Instead of silicide, tungsten (W), molybdenum (
A similar effect can be obtained even when a high melting point metal such as Mo) is used.

Further, in the second embodiment, the drive MIS-FET and the selection M■S-FET were configured with n-channel MIS-FET, and the resistance element was configured with p-channel MIS-FET.
Drive MIS-FET and selection MIS-FET as p++
Similar effects can be obtained even when the resistor element is configured with an n-channel MIS-FET and the resistance element is configured with an n-channel MIS-FET.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

(1), the gate electrode on the n-channel MIs-FET side,
It is composed of polysilicon doped with n-type impurities, a barrier layer for preventing the diffusion of the impurities, and a high melting point metal or its silicide, and the gate electrode on the p-channel MIS-FET side is made of polysilicon doped with p-type impurities. By making the CMIS structure composed of silicon, a barrier layer for preventing the diffusion of the impurities, and a high-melting point metal or its silicide, these gate electrodes can be integrally formed without deteriorating the gate characteristics. becomes possible.

(2) The gate electrode of the drive MIS-FET is composed of polysilicon doped with impurities of a predetermined conductivity type, a barrier layer for preventing diffusion of the impurity, and a high melting point metal or its silicide, and the drive MIS-FET is The drive M
It becomes possible to directly connect the gate electrode of the IS-FET and the resistance element.

[Brief explanation of the drawing]

1 is a sectional view taken along the line II in FIG. 2 showing a semiconductor device as an embodiment of the present invention, FIG. 2 is a schematic plan view of this semiconductor device, and FIG. 3 is a schematic plan view of this semiconductor device. The equivalent circuit diagram, FIG. 4, is the rV-
5 is a plan view of this memory cell, and FIG. 6 is an equivalent circuit diagram of this memory cell. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... P well region, 3...
N-well region, 4... Field insulating film, 5... Gate insulating film, 6... Channel stopper region, 7a, 7
b, 17a, 17b...gate electrode, 3a, 3b...
・Polysilicon, 9...Titanium nitride (barrier layer), 10...Silicide, lla...N-type semiconductor region, llb...P-type semiconductor region, 12a, 18
19...N'-type semiconductor region, 12b...P'-type semiconductor region, 13...Spacer, 14...Interlayer insulating film, 15a, 15b, 15c... Wiring, 16.20.2
5... Contact hole, 21°24... Insulating film,
22... Conductive layer, 23... Through hole, C...
Connection n, DL, completion T-/complementary data line, Q,...
-n-channel MIS-FET5Ql...p-channel MIS-FET. Qd1. Qd2...Drive MrS-FET, Qt, , Q
t2...Selection MIS-FET, R,,R,・
...Resistance element, WL...Word line. Agent Patent Attorney Daiwa Tsutsui

Claims (1)

[Claims] 1. The gate electrode of the MIS/FET is formed by laminating polysilicon doped with impurities, a barrier layer for preventing diffusion of the impurities, and a high melting point metal or its silicide. semiconductor device. 2. The semiconductor device according to claim 1, wherein the barrier layer is made of titanium nitride. 3. N-channel MIS/FET and p-channel on the same semiconductor substrate
A semiconductor device having an integrated circuit formed with a channel MIS/FET, wherein the gate electrode of the n-channel MIS/FET is made of polysilicon doped with an n-type impurity, a barrier layer for preventing diffusion of the impurity, The gate electrode of the p-channel MIS/FET is formed by laminating a high melting point metal or its silicide, and the gate electrode of the p-channel MIS/FET is made of polysilicon doped with p-type impurities, a barrier layer for preventing diffusion of the impurity, and a high melting point metal or its silicide. A semiconductor device characterized by being formed by laminating silicide. 4. The semiconductor device according to claim 3, wherein the barrier layer is made of titanium nitride. 5. A semiconductor device in which a flip-flop circuit of a memory cell is composed of a pair of resistive elements and a pair of driving MIS/FET, wherein the gate electrode of the driving MIS/FET is
The resistance element is formed by laminating polysilicon doped with an impurity of one conductivity type, a barrier layer for preventing diffusion of the impurity, and a high melting point metal or its silicide, and the resistance element is doped with an impurity of a conductivity type different from the impurity. A semiconductor device comprising doped polysilicon. 6. The semiconductor device according to claim 5, wherein the barrier layer is made of titanium nitride.